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CBTU04082BS
1.8 V, wide bandwidth, 4 differential channel, 2 : 1 multiplexer/demultiplexer switch with single enable
1. General descriptionCBTU04082 is an 8-to-4 differential channel multiplexer/ demultiplexer switch. The
CBTU04082 can switch four differential signals to one of two locations. Using a unique
design technique, NXP has minimized the impedance of the switch such that the
attenuation observed through the switch is negligible, and also minimizes the
channel-to-channel skew as well as channel-to-channel crosstalk, as required by the
high-speed serial interface.
2. Features and benefits 4 differential channel, 2: 1 multiplexer/demultiplexer High-speed signal switching; 5.0 Gbit/s Low intra-pair skew: 10 ps maximum (between positive and negative bits) Low crosstalk: −23 dB at 3 GHz Low off-state isolation: −23 dB at 3 GHz VDD operating range: 1.8V±10% ESD tolerance: 6kV HBM1 kV CDM Low inter-pair skew: 35 ps maximum Fit, form and function compatible to PI2PCIE2412 HVQFN42 package
3. Applications Routing of high-speed differential signals with low signal attenuation PCIe Gen2 DisplayPort 1.1a LVDS SATA 3 Gbit/s
CBTU04082
1.8 V, wide bandwidth, 4 differential channel, :1 multiplexer/demultiplexer switch with single enable
Rev. 2 — 13 July 2010 Product data sheet
NXP Semiconductors CBTU04082
1.8 V, wide bandwidth, 4 differential channel, 2 : 1 MUX/deMUX switch
4. Ordering information
5. Functional diagram
Table 1. Ordering informationCBTU04082BS HVQFN42 plastic thermal enhanced very thin quad flat package; no leads; terminals; body 3.5×9× 0.85 mm
SOT1144-1
NXP Semiconductors CBTU04082
1.8 V, wide bandwidth, 4 differential channel, 2 : 1 MUX/deMUX switch
6. Pinning information
6.1 PinningNXP Semiconductors CBTU04082
1.8 V, wide bandwidth, 4 differential channel, 2 : 1 MUX/deMUX switch
6.2 Pin description Table 2. Pin descriptionA0_P 2 I/O channel 0, port A differential signal input/output
A0_N 3 I/O
A1_P 6 I/O channel 1, port A differential signal input/output
A1_N 7 I/O
A2_P 11 I/O channel 2, port A differential signal input/output
A2_N 12 I/O
A3_P 15 I/O channel 3, port A differential signal input/output
A3_N 16 I/O
B0_P 38 I/O channel 0, port B differential signal input/output
B0_N 37 I/O
B1_P 36 I/O channel 1, port B differential signal input/output
B1_N 35 I/O
B2_P 29 I/O channel 2, port B differential signal input/output
B2_N 28 I/O
B3_P 27 I/O channel 3, port B differential signal input/output
B3_N 26 I/O
C0_P 34 I/O channel 0, port C differential signal input/output
C0_N 33 I/O
C1_P 32 I/O channel 1, port C differential signal input/output
C1_N 31 I/O
C2_P 25 I/O channel 2, port C differential signal input/output
C2_N 24 I/O
C3_P 23 I/O channel 3, port C differential signal input/output
C3_N 22 I/O
SEL 9 CMOS
single-ended input
operation mode select
SEL= 0: A→B
SEL= 1: A→C
VDD 5, 8, 13, 18, 20,
30, 40, 42
power positive supply voltage, 1.8 V to 2.0 V (± 0.1V)
GND 1, 4, 10, 14, 17,
19, 21, 39, 41,
center pad
power supply ground
NXP Semiconductors CBTU04082
1.8 V, wide bandwidth, 4 differential channel, 2 : 1 MUX/deMUX switch
7. Functional descriptionRefer to Figure 1 “Functional diagram of CBTU04082”.
7.1 Function selection
8. Limiting values
9. Static characteristics[1] Typical values are at VDD=1.8 V, Tamb =25 °C, and maximum loading.
[2] Input leakage current is ±50 μA if differential pairs are pulled to HIGH and LOW.
Table 3. Function selection An to Bn An to Cn
Table 4. Limiting valuesIn accordance with the Absolute Maximum Rating System (IEC 60134).
VDD supply voltage referenced to GND −0.5 +2.5 V input voltage −0.5 VDD V output current - 120 mA power dissipation - 0.5 W
Tstg storage temperature −65 +150 °C
Table 5. Static characteristicsVDD = 1.8V±10 %; Tamb= −40 °C to +85 °C; unless otherwise specified.
IDD supply current VDD= max.; VI =GNDor VDD --4 mA
IIH HIGH-level input current VDD= max.; VI =VDD -- ±5[2] μA
IIL LOW-level input current VDD= max.; VI =GND - - ±5[2] μA
VIH HIGH-level input voltage guaranteed HIGH level 0.65VDD -- V
VIL LOW-level input voltage guaranteed LOW level −0.5 - 0.15VDD V
VIK input clamping voltage VDD= max.; II= −18 mA - −0.7 −1.2 V
NXP Semiconductors CBTU04082
1.8 V, wide bandwidth, 4 differential channel, 2 : 1 MUX/deMUX switch
10. Dynamic characteristics[1] Typical values are at VDD=1.8 V; Tamb =25 °C, and maximum loading.
Table 6. Dynamic characteristicsVDD =1.8V±10 %; Tamb= −40 °C to +85 °C; unless otherwise specified.
αct crosstalk attenuation f=3 GHz - −23 - dB
f=100MHz - −58 - dB
αiso(off) off-state isolation f=3 GHz - −23 - dB
f=100MHz - −58 - dB
DDIL differential insertion loss f=3 GHz - −2- dB
B−3dB −3 dB bandwidth - 4.1 - GHz
tPD propagation delay from left-side port to
right-side port, or vice versa
-80 - ps
Switching characteristicstPZH OFF-state to HIGH propagation delay - - 8.0 ns
tPZL OFF-state to LOW propagation delay - - 8.0 ns
tPHZ HIGH to OFF-state propagation delay - - 8.0 ns
tPLZ LOW to OFF-state propagation delay - - 8.0 ns
tsk(dif) differential skew time intra-pair - - 10 ps
tsk skew time inter-pair - - 35 ps
NXP Semiconductors CBTU04082
1.8 V, wide bandwidth, 4 differential channel, 2 : 1 MUX/deMUX switch
11. Test information
Table 7. Test datatPLZ, tPZL (output on B side) 50pF 200Ω 2× VDD
tPHZ, tPZH (output on B side) 50pF 200Ω GND
tPD 50pF 200Ω open
NXP Semiconductors CBTU04082
1.8 V, wide bandwidth, 4 differential channel, 2 : 1 MUX/deMUX switch
12. Package outline
Fig 6. Package outline SOT1144-1 (HVQFN42)
