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CBTL12131ET ,DisplayPort multiplexer for bidirectional video in all-in-one computer systemsGeneral descriptionCBTL12131 is an integrated DisplayPort high-speed path switch/multiplexer that a ..
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CBTL12131ET
DisplayPort multiplexer for bidirectional video in all-in-one computer systems
1. General description
CBTL12131 is an integrated DisplayPort high-speed path switch/multiplexer that allows
all-in-one computer systems to efficiently manage path switching between different
display modes of operation. With the CBTL12131, video can be routed either from one
DisplayPort source (GPU1) to an integrated DisplayPort panel and simultaneously from a
second DisplayPort source (GPU2) to an external DisplayPort sink; or from an external
DisplayPort source to the integrated DisplayPort panel.
The device is configured as four main Ports A through D, each providing four high-speed
differential lanes for DisplayPort Main Link (ML) channels, one high-speed differential lane
for the DisplayPort AUX channel, and one single-ended lane for the HPD (Hot Plug
Detect) signal. One port (Port A) provides an additional alternate lane for the AUX
channel, in order to allow bypassing of external AC-coupling capacitors for support of the
DDC channel in case an external connected sink is a ‘++DP’ type cable adapter.
For the path supporting the ‘external source to integrated DisplayPort panel’ mode, a
programmable equalizer is provided which allows compensation for channel loss that the
external source or internal sink are unable to adequately compensate for. The equalizer is
self-biasing and is programmable to five gain-frequency curves, of which one is a flat
response and four are active equalization. The equalizer output can also be set to one of
two levels of pre-emphasis (including flat), and also differential swing level can be set to
one of two levels. All options (EQ, pre-emphasis, level) are easily programmed using
board-strapping (resistor, short or open) of three unique Quinary Input programming pins.
The CBTL12131 includes additional features that support use of the external DisplayPort
connector in both directions: either an external sink (monitor or cable adapter) or external
source (notebook computer) can be connected, while CBTL12131 configures the direction
and termination of the related signals accordingly. The port facing the external DisplayPort
connector (Port B) is equipped with dedicated sensing circuitry which detects and reports
the status of the HPD and AUX lines, to support the system controller in determining and
setting the proper connection status. The AUX channel of Port B also has switchable
integrated termination, to allow the system controller to apply the correct DC termination
in case an external DisplayPort source is connected. Moreover, it affords the system
controller the means to detect the type of system (sink, source or all-in-one computer)
connected at Port B, and apply the proper termination required in each scenario.
The CBTL12131 is powered from a single 3.3 V power supply, consumes very little
current while providing low insertion loss and low return loss high-speed differential switch
channels suitable for use in DisplayPort v1.1a interconnect. All switch and configuration
settings can be performed by board-strapping or driving simple CMOS inputs—no
software or bus configuration is required. CBTL12131 is available in a 6 mm× 6mm
CBTL12131
DisplayPort multiplexer for bidirectional video in all-in-one
computer systems
Rev. 1 — 25 February 2011 Product data sheet
NXP Semiconductors CBTL12131
DisplayPort multiplexer for bidirectional video
TFBGA64 package with 0.5 mm ball pitch; owing to its high level of integration and
versatility, it is eminently suitable for use in computers employing bidirectional DisplayPort
video.
2. Features and benefits
2.1 High-speed DisplayPort Main Link multiplexing Switch path topologies supporting: ‘dual through’ mode (two GPUs to two displays simultaneously) ‘external source’ mode (external source to internal display) Supports DisplayPort v1.1a at 2.7 Gbit/s High-bandwidth analog pass-gate technology Configurable equalization in ‘external source’ mode path Pre-emphasis level control for equalizer in ‘external source’ mode path Very low intra-pair differential skew of <5ps Very low inter-pair skew of < 180ps
2.2 DDC and AUX multiplexing Switch path topologies supporting: ‘dual through’ mode (two GPUs to two displays) ‘external source’ mode (external source to internal display) ‘AC coupling bypass’ mode on Port A (for external ++DP sink) Supports DisplayPort v1.1a AUX channel Supports DDC/I2 C-bus multiplexing High-bandwidth analog pass-gate technology
2.3 HPD channel management Active logic management of HPD signals Bidirectional HPD I/O for external connector (PortB) HPD input for integrated DisplayPort display (PortD) Two HPD outputs to both GPUs, one for internal (Port C) and one for external video
(PortA)5V tolerance on all HPD inputs 3.3 V LVTTL logic output levels for all HPD outputs Internal 200 kΩ pull-down resistor on Port B and Port D HPD input ensures default
LOW when no sink is connected
2.4 Link state detection, configuration and reporting Detection of DC state of AUX_P and AUX_N lines of external display (PortB) Filtering of HPD interrupt pulse from external display (PortB) Reporting of detected/filtered Port B AUX and HPD states via CMOS outputs (to
external system controller) AUX channel bias control inputs for Port B to allow configuration as source or sink
NXP Semiconductors CBTL12131
DisplayPort multiplexer for bidirectional video Integrated high-ohmic pull-down (4.7 MΩ) and switchable 100 kΩ and 500 kΩ
resistors for Port B AUX bias control
2.5 Equalizer Programmable equalizer for channel loss compensation from Port B to PortD
(external source mode) Five levels of input equalization (including flat) Two levels of output pre-emphasis (including flat) Two output voltage swing levels Three quinary input control pins allow equalization, pre-emphasis and output voltage
swing selection by simple board strapping
2.6 General Power supply 3.3V±10% Low active mode supply current of 30 mA typical (Dual-through mode) Active mode supply current of 120 mA typical (External source mode, EQ= on) ESD resilience to 4 kV HBM, 1 kV CDM Available in TFBGA64 6 mm×6 mm package
3. Typical system configuration
4. Ordering information
Table 1. Ordering information
CBTL12131ET TFBGA64 plastic thin fine-pitch ball grid array package; 64 balls; body6×6× 0.8 mm SOT543-1
NXP Semiconductors CBTL12131
DisplayPort multiplexer for bidirectional video
5. Functional diagram
NXP Semiconductors CBTL12131
DisplayPort multiplexer for bidirectional video
6. Pinning information
6.1 Pinning
NXP Semiconductors CBTL12131
DisplayPort multiplexer for bidirectional video
6.2 Pin descriptionTable 2. Pin description
Control inputs
PATH_SEL E1 3.3 V low-voltage CMOS
single-ended input
Input to set the path configuration of the CBTL12131. When LOW,
Ports A and B are mutually connected, as well as Ports C and D.
When HIGH, Port B is connected to PortD.
DDC_AUX_SEL D10 3.3 V low-voltage CMOS
single-ended input
Input to select between DDC and AUX terminals for Port A. When
HIGH, the DDC_A_P and DDC_A_N terminals are connected to their
respective AUX_B_P and AUX_B_N terminals on Port B. When
LOW, the AUX_A_P and AUX_A_N terminals are connected to their
respective AUX_B_P and AUX_B_N terminals on PortB.
EQ5 E10 3.3 V low-voltage CMOS
quinary input
Equalizer setting input pin. This pin can be board-strapped to one of
five decode values: short to GND, resistor to GND, open-circuit,
resistor to VDD, short to VDD. See Table 7 for truth table.
PL5 D9 3.3 V low-voltage CMOS
quinary input
Pre-emphasis level setting input pin. This pin can be board-strapped
to one of five decode values: short to GND, resistor to GND,
open-circuit, resistor to VDD, short to VDD. See Table 8 for truth
table.
LV5 F9 3.3 V low-voltage CMOS
quinary input
Output differential swing setting input pin. This pin can be
board-strapped to one of five decode values: short to GND, resistor
to GND, open-circuit, resistor to VDD, short to VDD. See Table 9 for
truth table.
TST_REXT F1 3.3 V low-voltage CMOS
single-ended input with
current sensing analog
input
Test pin for NXP use, combined with external current sensing
function. Should be tied to ground via an external resistor of value kΩ±1 %. This pin must not be left open-circuit to avoid possible
erroneous engagement of test mode in normal operation.
AUX_TERM_SRC G1 3.3 V low-voltage CMOS
single-ended input
Input to enable source-type termination on the Port B AUX pair.
When HIGH, 100 kΩ termination resistors are applied to the PortB
AUX pair. When LOW, the termination resistors will be disabled
(high-impedance).
AUX_TERM_SNK G2 3.3 V low-voltage CMOS
single-ended input
Input to enable sink-style termination on the Port B AUX pair. When
HIGH, a 500 kΩ termination resistor to VDD is applied to AUX_B_P.
When LOW, the termination resistor will be disabled
(high-impedance).
Status outputs
HPD_B_FLT F10 3.3 V low-voltage CMOS
single-ended output
This outputs a filtered version of HPD_B.
AUX_B_P_STATE D1 3.3 V low-voltage CMOS
single-ended output
DC state (HIGH or LOW) of AUX_B_P signal.
AUX_B_N_STATE D2 3.3 V low-voltage CMOS
single-ended output
DC state (HIGH or LOW) of AUX_B_N signal.
NXP Semiconductors CBTL12131
DisplayPort multiplexer for bidirectional video
Port A terminals
ML_A_0P K7 differential port terminal Four high-speed differential pairs for DisplayPort Main Link signals,
Port A. Designated as port facing the GPU for external video. PortA
will be exclusively connected to Port B when PATH_SEL= LOW, and
will be high-impedance when PATH_SEL= HIGH.
ML_A_0N J7 differential port terminal
ML_A_1P K8 differential port terminal
ML_A_1N J8 differential port terminal
ML_A_2P K9 differential port terminal
ML_A_2N J9 differential port terminal
ML_A_3P K10 differential port terminal
ML_A_3N J10 differential port terminal
AUX_A_P H10 differential port terminal High-speed differential pair for DisplayPort AUX signals, PortA.
These terminals are active when DDC_AUX_SEL= LOW only;
when DDC_AUX_SEL = HIGH, these are high-impedance.AUX_A_N H9 differential port terminal
DDC_A_0 G10 differential port terminal Port A terminal intended for AUX AC coupling capacitor bypass.
These terminals are active when DDC_AUX_SEL= HIGH only;
when DDC_AUX_SEL = LOW, these are high-impedance.DDC_A_1 G9 differential port terminal
HPD_A K6 3.3 V LVTTL
single-ended output
3.3 V LVTTL HPD output for Port A. When PATH_SEL= LOW, this
output follows the state of HPD_B (from external DP or ++DP sink).
When PATH_SEL= HIGH, this output is always LOW.
Port B terminals
ML_B_0P A7 differential port terminal Four high-speed differential pairs for DisplayPort Main Link signals,
Port B. Designated as port facing the external DP connector. PortB
will be exclusively connected to Port A when PATH_SEL= LOW and
HPD_B_FLT= HIGH, and will be exclusively connected to PortD
when PATH_SEL= HIGH. When PATH_SEL= HIGH, the signal
ordering and association to Port D ML signals is automatically
corrected by internal routing, to map to the DP connector's inverted
signal ordering for a DP sink-side connector.
ML_B_0N B7 differential port terminal
ML_B_1P A8 differential port terminal
ML_B_1N B8 differential port terminal
ML_B_2P A9 differential port terminal
ML_B_2N B9 differential port terminal
ML_B_3P A10 differential port terminal
ML_B_3N B10 differential port terminal
AUX_B_P C10 differential port terminal High-speed differential pair for DisplayPort AUX signals, PortB.
AUX_B_N C9 differential port terminal
HPD_B A6 3.3 V bidirectional
LVTTL I/O with high-Z
state
HPD input with 5V tolerance or output for Port B, to be connected to
the external DP connector. When PATH_SEL= LOW, HPD_B is
configured as input (from external DP or ++DP sink). When
PATH_SEL= HIGH, HPD_B is configured as output and follows the
state of HPD_D (from internal sink), to be connected via DP
connector to an external DP source.
Table 2. Pin description …continued
NXP Semiconductors CBTL12131
DisplayPort multiplexer for bidirectional video
Port C terminals
ML_C_0P K1 differential port terminal Four high-speed differential pairs for DisplayPort Main Link signals,
Port C. Designated as port facing the GPU for internal video. PortC
will be exclusively connected to Port D when PATH_SEL= LOW, and
will be high-impedance when PATH_SEL= HIGH.
ML_C_0N J1 differential port terminal
ML_C_1P K2 differential port terminal
ML_C_1N J2 differential port terminal
ML_C_2P K3 differential port terminal
ML_C_2N J3 differential port terminal
ML_C_3P K4 differential port terminal
ML_C_3N J4 differential port terminal
AUX_C_P H1 differential port terminal High-speed differential pair for DisplayPort AUX signals, PortC.
AUX_C_N H2 differential port terminal
HPD_C K5 3.3 V LVTTL
single-ended output
3.3 V LVTTL HPD output for Port C. When PATH_SEL= LOW, this
output follows the state of HPD_D (from internal sink). When
PATH_SEL = HIGH, this output is always LOW.
Port D terminals
ML_D_0P A1 differential port terminal Four high-speed differential pairs for DisplayPort Main Link signals,
Port D. Designated as port facing the internal eDP display module
connector. Port D will be exclusively connected to Port C when
PATH_SEL= LOW, and will be exclusively connected to Port B when
PATH_SEL= HIGH.
ML_D_0N B1 differential port terminal
ML_D_1P A2 differential port terminal
ML_D_1N B2 differential port terminal
ML_D_2P A3 differential port terminal
ML_D_2N B3 differential port terminal
ML_D_3P A4 differential port terminal
ML_D_3N B4 differential port terminal
AUX_D_P C1 differential port terminal High-speed differential pair for DisplayPort AUX signals, PortD.
AUX_D_N C2 differential port terminal
HPD_D A5 3.3 V LVTTL
single-ended input V tolerant HPD input for Port D, to be connected to the internal
sink.
Supply and ground
VDD B5,
E2,
E9,
power supply 3.3 V power supply pins.
GND B6,
F2,
ground Ground pins.
Table 2. Pin description …continued
NXP Semiconductors CBTL12131
DisplayPort multiplexer for bidirectional video
7. Functional description
7.1 General
The CBTL12131 is a high-bandwidth DisplayPort channel switching device designed for
use in all-in-one computers. It contains high-bandwidth switches arranged between four
Ports (A through D) to allow two different channel topologies, where each channel
comprises a Main Link (ML), AUX and HPD path for comprehensive DisplayPort channel
switching. One can select between two basic configurations: either Ports A and C are
connected to Ports B and D respectively, or Port B is connected to Port D while Ports A
and C are high-impedance. In addition, the CBTL12131 includes circuitry to assist in
detection and configuration of Port B designated as the port facing the external
DisplayPort connector. This section describes these functional blocks in detail.
7.2 Main Link DisplayPort switches/multiplexers
The Main Link path topology provides for four differential pairs in each Port, and an
equalizer for each differential pair in the path from Port B to Port D, as shown in Figure5.
The Main Link switches are operated by CMOS input PATH_SEL and further qualified by
the state of internally derived signal HPD_B_FLT (see Section 7.6 for details). When
PATH_SEL is LOW, Ports C and D are mutually connected, Ports A and B are mutually
connected only when HPD_B_FLT is HIGH, and the equalizer is turned off (isolating).
When PATH_SEL is HIGH, Ports A and C are disconnected (high-impedance) and Port D
is connected to Port B via the equalizer. The equalizer can by bypassed or configured by
quinary input EQ5 to any of five equalizer settings (including a flat response) depending
on specific application conditions. For details on the Equalizer function, please refer to
Section 7.7.
Table 3. Main Link channel configuration
Legend: high-Z = isolating, high-impedance; ACT = active, low-impedance. 0 ACT high-Z high-Z Normal mode; internal display only 1 ACT ACT high-Z Normal mode with dual display 0 high-Z high-Z ACT External source mode with internal
display not yet asserting HPD 1 high-Z high-Z ACT External source mode with internal
display asserting HPD
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NXP Semiconductors CBTL12131
DisplayPort multiplexer for bidirectional video
Rem
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Signal order
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NXP Semiconductors CBTL12131
DisplayPort multiplexer for bidirectional video
7.3 AUX and DDC switches/multiplexers
For all ports except Port A, only a single pair of signal lines is provided. The path
configuration for the AUX/DDC channels follows that of the Main Link: when
PATH_SEL= LOW, Ports C and D are connected; when PATH_SEL= LOW and
HPD_B_FLT= HIGH, also Ports A and B are connected; when PATH_SEL= HIGH,
Port D is connected to Port B, and Ports A and C are isolated (see Figure 6).
Port A additionally provides a second pair of signal lines, to allow bypassing of external
AC-coupling capacitors (normally placed in series with the AUX channel) in the case when
an external ++DP cable adapter is detected, and therefore a DC path needs to be
provided from the external DP connector’s AUX_P and AUX_N lines, in order to support
DDC communication across those lines between the External Graphics GPU (facing
Port A) and the external ++DP cable adapter. Selection between the DDC and AUX
channels of Port A is determined by the input DDC_AUX_SEL: when
DDC_AUX_SEL= LOW, the active channel is AUX_A; when DDC_AUX_SEL= HIGH,
the active channel is DDC_A. Typically, DDC_AUX_SEL is driven by a qualified version of
the DP ‘Cable Detect’ signal (pin 4 of a miniDP connector or pin 13 of a normal DP
connector) and will be HIGH when such a cable adaptor is connected and powered.
NXP Semiconductors CBTL12131
DisplayPort multiplexer for bidirectional video
7.4 HPD signal path
The HPD signal path, unlike the Main Link and AUX/DDC paths, uses active LVTTL logic
rather than passive switching. As shown in Figure 7, the topology follows that of the
Main Link and AUX channels but with the signal direction in reverse direction (since the
HPD signal direction is always from sink to source). When PATH_SEL is LOW, output
HPD_C follows and re-drives input HPD_D and similarly HPD_A follows the logic state of
input HPD_B. An integrated 200 kΩ resistor (RPD_HPD) between HPD_B and GND
ensures a logic LOW when no device is connected to Port B. When PATH_SEL is HIGH,
HPD_B becomes an output and follows the logic state of HPD_D. Please also refer to
Section 7.6 for specific details on the HPD filtering function.
Table 5. AUX/DDC channel configuration
Legend: high-Z = isolating, high-impedance; ACT = active, low-impedance.
NXP Semiconductors CBTL12131
DisplayPort multiplexer for bidirectional video
[1] Steady-state is shown only. A HIGH-to-LOW transition will be filtered (~4 ms delay).
7.5 AUX logic state detection
CBTL12131 includes a helpful function to determine the DC state of the AUX_B_P and
AUX_B_N pins thereby aiding in the detection of devices connected to the external DP
connector. The DC state of these pins is output on pins AUX_B_P_STATE and
AUX_B_N_STATE respectively, after the 1 Mbit/s (typ) Manchester-encoded bitstream is
removed by filtering.
7.6 HPD logic state detection
To further aid in detection of externally connected devices on Port B, the HPD_B_FLT pin
outputs a filtered version of pin HPD_B. The filtering function suppresses the 1 ms (typ)
LOW interrupt pulse from a DisplayPort sink, thereby avoiding a false disconnect
detection. Only a LOW pulse greater than 4 ms will result in a LOW output on
HPD_B_FLT.
7.7 Equalizer
The Equalizer function equalizes the signal on the Main Link channel of Port B and
re-drives them to Port D and ultimately to the internal display panel.
The Equalizer is only active when PATH_SEL is HIGH. When PATH_SEL is LOW, the
equalizer is effectively disabled and presents minimum parasitic load to the Main Link
channels.
The Equalizer has configurable Equalization (EQ) settings for its input (Port B side), which
can be set to one of five options by quinary input pin EQ5. See Table 7 for programming
options.
Table 6. HPD channel configuration
NXP Semiconductors CBTL12131
DisplayPort multiplexer for bidirectional video
The Equalizer also has two different levels of Pre-emphasis for its output (Port D side),
which can be set by quinary input pin PL5; as well as two different output differential swing
levels, which can be set by quinary input pin LV5. See Table 8 and Table 9 for
programming options.
[1] Only available with 400 mV output voltage swing setting (see Table9).
Table 7. Equalizer settings
short to GND 05 0dB kΩ resistor to GND 15 2dB
open-circuit 25 3.5dB kΩ resistor to VDD 35 6.5dB
short to VDD 45 9dB
Table 8. Pre-emphasis settings
short to GND 05 0dB kΩ resistor to GND 15 3.5dB[1]
open-circuit 25 reserved kΩ resistor to VDD 35 reserved
short to VDD 45 reserved

Partno	Mfg	Dc	Qty	Available	Descript
CBTL12131ET	NXP	N/a	1164	avai	DisplayPort multiplexer for bidirectional video in all-in-one computer systems