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CBTL06122AHF-CBTL06122BHF
High-performance DisplayPort/PCIe Gen2 hex display multiplexer
General descriptionThe CBTL06122isa six-channel (‘hex’) multiplexerfor DisplayPort and PCI Express Gen2
applications. It provides four differential channels capable of switching or multiplexing
(bidirectional and AC-coupled) PCI Express Gen2 or DisplayPort signals, using
high-bandwidth pass-gate technology. Additionally,it providesfor switching/multiplexingof
the Hot Plug Detect signalas wellas the AUXor DDC (Direct Display Control) signals,for
a total of six channels.
The CBTL06122 is designed for high-performance PCI Express Gen2 and DisplayPort
applications. The device is available in two different pinouts (A and B, orderable as
separate part numbers) to suit different motherboard layout requirements.
The typical application of CBTL06122 is on motherboards, docking stations or add-in
cards where the graphics and I/O system controller chip utilizes I/O pins that are
configurablefor either PCI Expressor DisplayPort operation. The hex display MUX canbe
used in such applications to route the signal from the controller chip to either a physical
DisplayPort connectorora PCI Express connector usingits1:2 multiplexer topology. The
controller chip selects which path to use by setting a select signal (which can be latched)
HIGH or LOW.
Optionally, the hex MUX device canbe usedin conjunction withan HDMI/DVI level shifter
device (PTN3300A, PTN3300Bor PTN3301)to allowfor DisplayPortas wellas HDMI/DVI
connectivity.
CBTL06122
High-performance DisplayPort/PCIe Gen2 hex display
multiplexer
Rev. 02 — 16 April 2009 Product data sheet
NXP Semiconductors CBTL06122
High-performance DP/PCIe Gen2 hex display multiplexer
NXP Semiconductors CBTL06122
High-performance DP/PCIe Gen2 hex display multiplexer Features1: 2 multiplexing of DisplayPort (v1.1 - 2.7 Gbit/s) or PCI Express (Gen2 - 5.0 Gbit/s)
signals 4 high-speed differential channels 1 channel for AUX differential signals or DDC clock and data 1 channel for HPD High-bandwidth analog pass-gate technology Very low intra-pair differential skew (<5 ps) Very low inter-pair skew (< 180 ps) All path delays matched including between RX1− to X− and RX1+ to X+ Switch/MUX position select with latch function Shutdown mode CMOS input Shutdown mode minimizes power consumption while switching all channels off Very low operation current of 0.2 mA typ Very low shutdown current of <10 μA Standby mode minimizes power consumption while switching all channels off Single 3.3 V power supply ESD 4 kV HBM, 1 kV CDM Two pinouts (A and B) available as separate ordering part numbers Available in 11 mm×5 mm HWQFN56R package
NXP Semiconductors CBTL06122
High-performance DP/PCIe Gen2 hex display multiplexer Applications Motherboard applications requiring DisplayPort and PCI Express Gen2
switching/multiplexing Docking stations Notebook computers Chip sets requiring flexible allocation of PCI Express or DisplayPort I/O pins to board
connectors
Ordering information[1] The A and B suffix in the part number correspond to the A and B pinouts, respectively (see Figure 5 and Figure6).
[2] HF is the package designator for the HWQFN package.
[3] Total height after printed-circuit board mounting = 0.8 mm (max.).
Table 1. Ordering informationCBTL06122AHF [1][2] HWQFN56R plastic thermal enhanced very very thin quad flat package; no leads; terminals; resin based; body 11×5× 0.7 mm[3] SOT1033-1
CBTL06122BHF [1][2]
NXP Semiconductors CBTL06122
High-performance DP/PCIe Gen2 hex display multiplexer Functional diagram
NXP Semiconductors CBTL06122
High-performance DP/PCIe Gen2 hex display multiplexer Pinning information
6.1 Pinning
NXP Semiconductors CBTL06122
High-performance DP/PCIe Gen2 hex display multiplexer
6.2 Pin description
Table 2. Pin descriptionSEL 18 2 3.3 V low-voltage CMOS
single-ended input
SEL controls the MUX through a flow-through latch.
LE_N 19 3 3.3 V low-voltage CMOS
single-ended input
The latch gate is controlled by LE_N.
XSD 50 50 3.3 V low-voltage CMOS
single-ended input
Optional shutdown pin. Should be driven HIGH or
connected to VDD for normal operation. When LOW, all
paths are switchedoff (non-conducting) and supply current
consumption is minimized.
RX0+ 33 26 differential input Differential input from PCIe connector or device. RX0+
makes a differential pair with RX0−. RX0+ is passed
through to the OUT+ pin when SEL=0.
RX0− 32 25 differential input Differential input from PCIe connector or device. RX0−
makes a differential pair with RX0+. RX0− is passed
through to the OUT− pin when SEL=0.
RX1+ 31 24 differential input Differential input from PCIe connector or device. RX1+
makes a differential pair with RX1−. RX1+ is passed
through to the X+ pin when SEL=0.
RX1− 30 23 differential input Differential input from PCIe connector or device. RX1−
makes a differential pair with RX1+. RX1− is passed
through to the X− pin on a path that matches the RX1+ to
X+ path.
IN_0+ 2 4 differential input Differential input from display source PCIe outputs.
IN_0+ makes a differential pair with IN_0−.
IN_0− 3 5 differential input Differential input from display source PCIe outputs.
IN_0− makes a differential pair with IN_0+.
IN_1+ 4 7 differential input Differential input from display source PCIe outputs.
IN_1+ makes a differential pair with IN_1−.
IN_1− 5 8 differential input Differential input from display source PCIe outputs.
IN_1− makes a differential pair with IN_1+.
IN_2+ 7 9 differential input Differential input from display source PCIe outputs.
IN_2+ makes a differential pair with IN_2−.
IN_2− 8 10 differential input Differential input from display source PCIe outputs.
IN_2− makes a differential pair with IN_2+.
IN_3+ 9 12 differential input Differential input from display source PCIe outputs.
IN_3+ makes a differential pair with IN_3−.
IN_3− 10 13 differential input Differential input from display source PCIe outputs.
IN_3− makes a differential pair with IN_3+.
HPD 24 31 high-voltage
single-ended input
Low frequency,0Vto5 V/3.3V (nominal) input signal. This
signal comes from the HDMI/DP connector. Voltage HIGH
indicates a ‘plugged’ state; voltage LOW indicates
‘unplugged’. 14 18 (SEL = HIGH); HPD:
high-voltage single-ended
input
Low frequency,0Vto5 V/3.3V (nominal) input signal. This
signal comes from the HDMI/DP connector.
(SEL = LOW); X+:
pass-through output
Analog ‘pass-through’ output corresponding to RX1+.
NXP Semiconductors CBTL06122
High-performance DP/PCIe Gen2 hex display multiplexer[1] HWQFN56R package die supply ground is connected to both GND pins and exposed center pad. GND pins must be connected to
supply groundfor proper device operation.For enhanced thermal, electrical, and board level performance,the exposed pad needstobe
soldered to the board using a corresponding thermal pad on the board and for proper heat conduction through the board, thermal vias
need to be incorporated in the PCB in the thermal pad region. 15 19 pass-through output
from RX1− inputisan analog ‘pass-through’ output correspondingto the
RX1− input. The path from RX1−toX−is matched with the
path from RX1+ to X+. X+ and X− form a differential pair
when the pass-through MUX mode is selected.
D0+ 43 54 pass-through output1,
option1
Analog ‘pass-through’ output 1 corresponding to IN_0+
and IN_0−, when SEL=1.D0− 42 53
D1+ 41 52 pass-through output2,
option1
Analog ‘pass-through’ output 1 corresponding to IN_1+
and IN_1−, when SEL=1.D1− 40 51
D2+ 39 47 pass-through output3,
option1
Analog ‘pass-through’ output 1 corresponding to IN_2+
and IN_2−, when SEL=1.D2− 38 46
D3+ 37 45 pass-through output4,
option1
Analog ‘pass-through’ output 1 corresponding to IN_3+
and IN_3−, when SEL=1.D3− 36 44
TX0+ 54 43 pass-through output1,
option2
Analog ‘pass-through’ output 2 corresponding to IN_0+
and IN_0−, when SEL=0.TX0− 53 42
TX1+ 52 41 pass-through output2,
option2
Analog ‘pass-through’ output 2 corresponding to IN_1+
and IN_1−, when SEL=0.TX1− 51 40
TX2+ 47 39 pass-through output3,
option2
Analog ‘pass-through’ output 2 corresponding to IN_2+
and IN_2−, when SEL=0.TX2− 46 38
TX3+ 45 37 pass-through output4,
option2
Analog ‘pass-through’ output 2 corresponding to IN_3+
and IN_3−, when SEL=0.TX3− 44 36
VDD 6, 17,22,
27, 34, 17,22,
27, 34,
3.3 V supply Supply voltage (3.3V±10 %).
AUX+ 26 33 differential input High-speed differential pair for AUX signals.
AUX− 25 32 differential input
OUT+ 12 14 differential input High-speed differential pair for PCIe RX0+ signal.
OUT− 13 15 differential input High-speed differential pair for PCIe RX0− signal.
GND[1] 1, 11,16,
20, 21,
28, 29,
35, 48,
49, 56 11,16,
20, 21,
28, 29,
35, 48,
49, 56
supply ground Ground.
SPARE 23 30 single-ended input Spare channel for general-purpose switch use.
Connected to pin X− when SEL=1.
Table 2. Pin description …continued
NXP Semiconductors CBTL06122
High-performance DP/PCIe Gen2 hex display multiplexer Functional descriptionRefer to Figure 4 “Functional diagram”.
The CBTL06122 uses 3.3 V power supply. All signal paths are implemented using
high-bandwidth pass-gate technology, are bidirectional and no clock or reset signal is
needed for the multiplexer to function.
The switch position is selected using the select signal (SEL), which can be latched using
the latch enable pin (LE_N). The detailed operation is described in Section 7.1.
7.1 MUX select (SEL) functionThe internal multiplexer switch positionis controlledby two logic inputs SEL and LE_Nas
described below.
The switch position select input signal SEL controls the MUX througha flow-through latch,
which is gated by the latch enable input signal LE_N (active LOW). The latch is open
when LE_Nis LOW;in this state the internal switch position will respondto the stateof the
SEL input signal. The latchis closed when LE_Nis HIGH, and the switch position will not
respond to input state changes on the SEL input.
Table 3. MUX select control high-impedance active; follows IN_x active; follows IN_x high-impedance
Table 4. MUX select latch control responds to changes on SEL latched
NXP Semiconductors CBTL06122
High-performance DP/PCIe Gen2 hex display multiplexer
7.2 Shutdown functionThe CBTL06122 provides a shutdown function to minimize power consumption when the
application is not active but power to the CBTL06122 is provided. Pin XSD (active LOW)
puts all channels in off mode (non-conducting) while reducing current consumption to
near-zero.
Limiting values[1] Human Body Model:ANSI/EOS/ESD-S5.1-1994, standardfor ESD sensitivity testing,Human Body Model-
Component level; Electrostatic Discharge Association, Rome, NY, USA.
[2] Charged Device Model: ANSI/EOS/ESD-S5.3-1-1999,standardforESD sensitivity testing, Charged Device
Model - Component level; Electrostatic Discharge Association, Rome, NY, USA.
Recommended operating conditions
Table 5. Shutdown function shutdown active
Table 6. Limiting valuesIn accordance with the Absolute Maximum Rating System (IEC 60134).
VDD supply voltage −0.3 +5 V
Tcase case temperature for operation within
specification
−40 +85 °C
Vesd electrostatic discharge
voltage
HBM [1]- 4000 V
CDM [2]- 1000 V
Table 7. Recommended operating conditionsVDD supply voltage 3.0 3.3 3.6 V input voltage - - 3.6 V
Tamb ambient temperature operating in free air −40 - +85 °C
