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CBTL02042ABQ
3.3 V, 2 differential channel, 2 : 1 multiplexer/demultiplexer switch for PCI Express Gen2
1. General descriptionCBTL02042A/B is a 2 differential channel, 2-to-1 multiplexer/demultiplexer switch for PCI
Express Generation 2 (Gen2), and other high-speed serial interface applications. The
CBTL02042A/B can switch two differential signals to one of two locations. Using a unique
design technique, NXP has minimized the impedance of the switch such that the
attenuation observed through the switch is negligible, and also minimized the
channel-to-channel skew as well as channel-to-channel crosstalk, as required by the
high-speed serial interface. CBTL02042A/B allows expansion of existing high speed ports
for extremely low power.
The device's pinouts are optimized to match different application layouts. CBTL02042A
has input and output pins on the opposite of the package, and is suitable for edge
connector(s) with different signal sources on the motherboard. CBTL02042B has outputs
on both sides of the package, and the device can be placed between two connectors to
multiplex differential signals from a controller. Please refer to Section 8 for layout
examples.
2. Features and benefits 2 bidirectional differential channel, 2: 1 multiplexer/demultiplexer High-speed signal switching for PCIe Gen2 5 Gbit/s High bandwidth: 7 GHz at −3dB Low insertion loss: −0.5 dB at 100 MHz −1.2 dB at 2.5 GHz Low intra-pair skew: 5 ps typical Low inter-pair skew: 35 ps maximum Low crosstalk: −30 dB at 2.5 GHz Low off-state isolation: −25 dB at 2.5 GHz Low return loss: −20 dB at 2.5 GHz VDD operating range: 3.3V±10% Shutdown pin (XSD) for power-saving mode Standby current less than 1 μA ESD tolerance: 8kV HBM1 kV CDM DHVQFN20 package
CBTL02042A; CBTL02042B
3.3 V, 2 differential channel, 2:1 multiplexer/demultiplexer
switch for PCI Express Gen2
Rev. 1 — 10 March 2011 Product data sheet
NXP Semiconductors CBTL02042A; CBTL02042B
3.3 V, 2 differential channel, 2:1 MUX/deMUX switch for PCIe Gen2
3. Applications Routing of high-speed differential signals with low signal attenuation PCIe Gen2 DisplayPort 1.2 USB 3.0 SATA 6 Gbit/s
4. Ordering information[1] Total height after printed-circuit board mounting = 1.0 mm maximum.
5. Functional diagram
Table 1. Ordering informationCBTL02042ABQ DHVQFN20 plastic dual in-line compatible thermal enhanced very thin quad flat
package; no leads; 20 terminals; body 2.5× 4.5× 0.85 mm[1] SOT764-1
CBTL02042BBQ DHVQFN20 plastic dual in-line compatible thermal enhanced very thin quad flat
package; no leads; 20 terminals; body 2.5× 4.5× 0.85 mm[1]
SOT764-1
NXP Semiconductors CBTL02042A; CBTL02042B
3.3 V, 2 differential channel, 2:1 MUX/deMUX switch for PCIe Gen2
6. Pinning information
6.1 Pinning
6.2 Pin description
Table 2. Pin descriptionA0_P 3 2 I/O channel 0, port A differential signal
input/outputA0_N 4 3 I/O
A1_P 7 6 I/O channel 1, port A differential signal
input/outputA1_N 8 7 I/O
B0_P 19 18 I/O channel 0, port B differential signal
input/outputB0_N 18 17 I/O
B1_P 17 14 I/O channel 1, port B differential signal
input/outputB1_N 16 13 I/O
C0_P 15 4 I/O channel 0, port C differential signal
input/outputC0_N 14 5 I/O
C1_P 13 8 I/O channel 1, port C differential signal
input/outputC1_N 12 9 I/O
SEL 9 12 CMOS
single-ended
input
operation mode select
SEL= LOW: A↔B
SEL= HIGH: A↔C
NXP Semiconductors CBTL02042A; CBTL02042B
3.3 V, 2 differential channel, 2:1 MUX/deMUX switch for PCIe Gen2[1] DHVQFN20 package die supply ground is connected to both GND pins and exposed center pad. GND pins
and the exposed center pad must be connected to supply ground for proper device operation. For
enhanced thermal, electrical, and board level performance, the exposed pad needs to be soldered to the
board using a corresponding thermal pad on the board and for proper heat conduction through the board,
thermal vias need to be incorporated in the printed-circuit board in the thermal pad region.
7. Functional descriptionRefer to Figure 1 “Functional diagram of CBTL02042A; CBTL02042B”.
7.1 Function selection and shutdown functionThe CBTL02042A/B provides a shutdown function to minimize power consumption when
the application is not active, but power to the CBTL02042A/B is provided. The XSD pin
(active HIGH) places all channels in high-impedance state (non-conducting) while
reducing current consumption to near-zero. When XSD pin is LOW, the device operates
normally.
XSD 2 19 CMOS
single-ended
input
Shutdown pin; should be driven
LOW or connected to VSS for
normal operation. When HIGH, all
paths are switched off
(non-conducting high-impedance
state), and supply current
consumption is minimized.
VDD 1, 6, 10 11, 16, 20 power positive supply voltage,
3.3V(±10%)
GND[1] 5, 11, 20,
center pad
1, 10, 15,
center pad
power supply ground
Table 2. Pin description …continued
Table 3. Function selectionX = Don’t care.
HIGH X An, Bn and Cn pins are high-Z
LOW LOW An to Bn and vice versa
LOW HIGH An to Cn and vice versa
NXP Semiconductors CBTL02042A; CBTL02042B
3.3 V, 2 differential channel, 2:1 MUX/deMUX switch for PCIe Gen2
8. Application design-in informationNXP Semiconductors CBTL02042A; CBTL02042B
3.3 V, 2 differential channel, 2:1 MUX/deMUX switch for PCIe Gen2
9. Limiting values[1] Human Body Model: ANSI/EOS/ESD-S5.1-1994, standard for ESD sensitivity testing, Human Body Model -
Component level; Electrostatic Discharge Association, Rome, NY, USA.
[2] Charged Device Model: ANSI/EOS/ESD-S5.3-1-1999, standard for ESD sensitivity testing, Charged Device
Model - Component level; Electrostatic Discharge Association, Rome, NY, USA.
10. Recommended operating conditions
11. Static characteristics[1] Typical values are at VDD=3.3 V, Tamb =25 °C, and maximum loading.
[2] Input leakage current is ±50 μA if differential pairs are pulled to HIGH and LOW.
Table 4. Limiting valuesIn accordance with the Absolute Maximum Rating System (IEC 60134).
VDD supply voltage −0.3 +4.6 V
Tcase case temperature −40 +85 °C
VESD electrostatic discharge voltage HBM [1]- 8000 V
CDM [2]- 1000 V
Table 5. Recommended operating conditionsVDD supply voltage 3.0 3.3 3.6 V input voltage - - VDD V
Tamb ambient temperature operating in free air −40 - +85 °C
Table 6. Static characteristicsVDD = 3.3V±10 %; Tamb= −40 °C to +85 °C; unless otherwise specified.
IDD supply current VDD= max.; VI =GNDor VDD;
XSD= LOW
-1.35 2.5 mA
Istb standby current VDD= max.; VI =GNDor VDD;
XSD= HIGH 1 μA
IIH HIGH-level input current VDD= max.; VI =VDD -- ±5[2] μA
IIL LOW-level input current VDD= max.; VI =GND - - ±5[2] μA
VIH HIGH-level input voltage SEL, XSD pins 0.65VDD -- V
VIL LOW-level input voltage SEL, XSD pins - - 0.35VDD V input voltage differential pins - - 2.4 V
SEL, XSD pins - - VDD V
VIC common-mode input
voltage 2.0 V
VID differential input voltage peak-to-peak - - 1.6 V
NXP Semiconductors CBTL02042A; CBTL02042B
3.3 V, 2 differential channel, 2:1 MUX/deMUX switch for PCIe Gen2
12. Dynamic characteristics[1] Typical values are at VDD=3.3 V; Tamb =25 °C, and maximum loading.
Table 7. Dynamic characteristicsVDD =3.3V±10 %; Tamb= −40 °C to +85 °C; unless otherwise specified.
DDIL differential insertion loss channel is OFF
f=100MHz - −50 - dB
f=2.5GHz - −25 - dB
channel is ON
f=100MHz - −0.5 - dB
f=2.5GHz - −1.2 - dB
DDNEXT differential near-end crosstalk adjacent channels are ON
f=100MHz - −50 - dB
f=2.5GHz - −30 - dB
B−3dB −3 dB bandwidth - 7.0 - GHz
DDRL differential return loss f= 100 MHz - −25 - dB
f=2.5GHz - −20 - dB
Ron ON-state resistance VDD= 3.3 V; VI =2V; II =19mA - 6 - Ω
tPD propagation delay from Port A to Port B, or PortA
to Port C, or vice versa
-80 - ps
Switching characteristicststartup start-up time supply voltage valid or XSD
going LOW to channel specified
operating characteristics
--10 ms
tPZH OFF-state to HIGH propagation delay - - 300 ns
tPZL OFF-state to LOW propagation delay - - 70 ns
tPHZ HIGH to OFF-state propagation delay - - 50 ns
tPLZ LOW to OFF-state propagation delay - - 50 ns
tsk(dif) differential skew time intra-pair - 5 - ps
tsk skew time inter-pair - - 35 ps
NXP Semiconductors CBTL02042A; CBTL02042B
3.3 V, 2 differential channel, 2:1 MUX/deMUX switch for PCIe Gen2
