CBT3257ABQ ,Quad 1-of-2 multiplexer/demultiplexerPin configuration SOT109-1 (SO16) and Fig 3.
CBT3257AD ,Quad 1-of-2 multiplexer/demultiplexerLogic diagramCBT3257A All information provided in this document is subject to legal disclaimers. N ..
CBT3257ADB ,Quad 1-of-2 multiplexer/demultiplexerFeatures and benefits 5 switch connection between two ports TTL-compatible input levels Minimal ..
CBT3257ADS ,Quad 1-of-2 multiplexer/demultiplexerPin configuration SOT338-1 (SSOP16) and SOT519-1 (SSOP16) SOT403-1 (TSSOP16) CBT3257Aterminal 1inde ..
CBT3257APW ,Quad 1-of-2 multiplexer/demultiplexerFeatures and benefits 5 switch connection between two ports TTL-compatible input levels Minimal ..
CBT3257DB ,Quad 1-of-2 multiplexer/demultiplexer
CDCV857ADGG ,2.5V SSTL-II Phase Lock Loop Clock Driver for Double Data-Rate Synchronous DRAM Applicationsblock diagramY0Y0Y1PWRDWNPowerdownY1AVDD and TestY2LogicY2Y3Y3Y4Y4Y5Y5CLKY6CLKY6PLLFBINY7FBINY7Y8Y8 ..
CDCV857ADGGR ,2.5V SSTL-II Phase Lock Loop Clock Driver for Double Data-Rate Synchronous DRAM Applicationsmaximum ratings over operating free-air temperature (unless otherwise noted)Supply voltage range, V ..
CDCV857B ,2.5 V Phase Lock Loop DDR Clock Drivermaximum ratings over operating free-air temperature (unless otherwise noted)Supply voltage range, V ..
CDCV857BDGG ,2.5 V Phase Lock Loop DDR Clock DriverCDCV857B, CDCV857BI2.5-V PHASE-LOCK LOOP CLOCK DRIVERSCAS689A − FEBRUARY 2003 − REVISED NOVEMBER 20 ..
CDCV857BDGGR ,2.5 V Phase Lock Loop DDR Clock Drivermaximum ratings over operating free-air temperature (unless otherwise noted)Supply voltage range, V ..
CDCV857BDGGRG4 ,2.5 V Phase Lock Loop DDR Clock Driver 48-TSSOP 0 to 70CDCV857B, CDCV857BI2.5-V PHASE-LOCK LOOP CLOCK DRIVERSCAS689A − FEBRUARY 2003 − REVISED NOVEMBER 20 ..
CBT3257ABQ-CBT3257AD-CBT3257ADB-CBT3257ADS-CBT3257APW
Quad 1-of-2 multiplexer/demultiplexer
1. General descriptionThe CBT3257A is a quad 1-of-2 high-speed TTL-compatible multiplexer/demultiplexer.
The low ON resistance of the switch allows inputs to be connected to outputs without
adding propagation delay or generating additional ground bounce noise.
Output enable (OE) and select-control (S) inputs select the appropriate nB1 and nB2
outputs for the nA input data.
The CBT3257A is characterized for operation from 40 Cto+85 C.
2. Features and benefits5 switch connection between two ports TTL-compatible input levels Minimal propagation delay through the switch Latch-up protection exceeds 100 mA per JEDEC standard JESD78 class II level A ESD protection: HBM JESD22-A114F exceeds 2000V MM JESD22-A115-A exceeds 200V CDM JESD22-C101E exceeds 1000V Multiple package options Specified from 40 Cto+85C
CBT3257A
Quad 1-of-2 multiplexer/demultiplexer
Rev. 5 — 4 April 2013 Product data sheet
NXP Semiconductors CBT3257A
Quad 1-of-2 multiplexer/demultiplexer
3. Ordering information[1] Also known as QSOP16.
4. Functional diagram
Table 1. Ordering informationCBT3257AD 40 Cto+85C SO16 plastic small outline package; 16 leads;
body width 3.9 mm
SOT109-1
CBT3257ADB 40 Cto+85C SSOP16 plastic shrink small outline package; 16 leads;
body width 5.3 mm
SOT338-1
CBT3257ADS 40 Cto+85C SSOP16[1] plastic shrink small outline package; 16 leads;
body width 3.9 mm; lead pitch 0.635 mm
SOT519-1
CBT3257APW 40 Cto+85C TSSOP16 plastic thin shrink small outline package; 16 leads;
body width 4.4 mm
SOT403-1
CBT3257ABQ 40 Cto+85C DHVQFN16 plastic dual in-line compatible thermal enhanced
very thin quad flat package; no leads; 16 terminals;
body 2.5 3.5 0.85 mm
SOT763-1
NXP Semiconductors CBT3257A
Quad 1-of-2 multiplexer/demultiplexer
5. Pinning information
5.1 PinningNXP Semiconductors CBT3257A
Quad 1-of-2 multiplexer/demultiplexer
5.2 Pin description
6. Functional description
7. Limiting values[1] The input and output negative voltage ratings may be exceeded if the input and output clamp current ratings are observed.
[2] For SO16 package: Ptot derates linearly with 8 mW/K above 70 C.
[3] For SSOP16 and TSSOP16 package: Ptot derates linearly with 5.5 mW/K above 70 C.
[4] For DHVQFN16 package: Ptot derates linearly with 4.5 mW/K above 70 C.
Table 2. Pin description 1 select control input
1B1, 2B1, 3B1, 4B1, 2, 5, 11, 14 B1 outputs/inputs
1B2, 2B2, 3B2, 4B2 3, 6, 10, 13 B2 outputs/inputs
1A, 2A, 3A, 4A 4, 7, 9, 12 A inputs/outputs
GND 8 ground (0V) 15 output enable (active LOW)
VCC 16 positive supply voltage
Table 3. Function selection= HIGH voltage level; L= LOW voltage level; X= Don’t care.
LLnA to nB1 H nA to nB2 X switch off
Table 4. Limiting valuesIn accordance with the Absolute Maximum Rating System (IEC 60134).
VCC supply voltage 0.5 +7.0 V input voltage [1] 0.5 +7.0 V
ISW switch current continuous current through each switch - 128 mA
IIK input clamping current VI <0V 50 mA
Tstg storage temperature 65 +150 C
Ptot total power dissipation Tamb = 40 C to +85 C
SO16 package [2] -500 mW
SSOP16 package [3] -500 mW
TSSOP16 package [3] -500 mW
DHVQFN16 package [4] -500 mW
NXP Semiconductors CBT3257A
Quad 1-of-2 multiplexer/demultiplexer
8. Recommended operating conditions
9. Static characteristics[1] All typical values are measured at VCC =5V; Tamb =25C.
[2] This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND.
[3] Measured by the voltage drop between the nA and the nBn terminals at the indicated current through the switch. The lowest voltage of
the two (nA or nBn) terminals determines the ON resistance.
Table 5. Operating conditionsAll unused control inputs of the device must be held at VCC or GND to ensure proper device operation.
VCC supply voltage 4.5 5.5 V
VIH HIGH-level input voltage 2.0 - V
VIL LOW-level input voltage - 0.8 V
Tamb ambient temperature operating in free-air 40 +85 C
Table 6. Static characteristicsTamb= 40 Cto+85 C.
VIK input clamping voltage VCC =4.5 V; II= 18 mA - - 1.2 V
Vpass pass voltage VI =VCC= 5.0 V; IO= 100A 3.6 3.9 4.2 V input leakage current VCC =5.5 V; VI= GND or 5.5V - - 1 A
ICC supply current VCC =5.5 V; IO =0mA; =VCCor GND 3 A
ICC additional supply current per input; VCC= 5.5 V; one input at
3.4 V, other inputs at VCC or GND
[2] -- 2.5 mA input capacitance control pins; VI=3 V or 0V -3.3 -pF
Cio(off) off-state input/output capacitance A port; VO=3 V or 0 V; OE =VCC -9.9 -pF
B port; VO=3 V or 0 V; OE =VCC -6.4 -pF
RON ON resistance VCC =4.5V [3] =0V; II =64mA - 5 7 =0V; II =30mA - 5 7 = 2.4 V; II =15mA - 10 15
NXP Semiconductors CBT3257A
Quad 1-of-2 multiplexer/demultiplexer
10. Dynamic characteristics[1] This parameter is warranted but not production tested. The propagation delay is based on the RC time constant of the typical ON
resistance of the switch and a load capacitance, when driven by an ideal voltage source (zero output impedance).
[2] tPLH and tPHL are the same as tpd.
tPZL and tPZH are the same as ten.
tPLZ and tPHZ are the same as tdis.
11. AC waveforms
Table 7. Dynamic characteristicsTamb= 40 Cto+85 C; VCC= 4.5 V to 5.5 V; for test circuit see Figure7.
tpd propagation delay nA to nBn or nBn to nA; see Figure5 [1][2] -0.25 ns
S to nA; see Figure5 [1][2] 1.4 5.0 ns
ten enable time OE to nA or nBn; see Figure6 [2] 1.5 5.1 ns
S to nBn; see Figure6 [2] 1.4 5.2 ns
tdis disable time OE to nA or nBn; see Figure6 [2] 2.2 5.5 ns
S to nBn; see Figure6 [2] 1.0 5.0 ns
NXP Semiconductors CBT3257A
Quad 1-of-2 multiplexer/demultiplexer
Table 8. Measurement points4.5 V to 5.5 V GND to 3.0 V 1.5 V 1.5 V VOL + 0.3 V VOH 0.3 V
NXP Semiconductors CBT3257A
Quad 1-of-2 multiplexer/demultiplexer
12. Test information
Table 9. Test data4.5 V to 5.5 V GND to 3.0 V 2.5 ns 50 pF 500 open 7.0 V open
NXP Semiconductors CBT3257A
Quad 1-of-2 multiplexer/demultiplexer
13. Package outline
