CAT28C257 ,Parallel EEPROM, 256KbMaximum Ratings are stress ratings only. Functional operation above theRecommended Operating Condit ..
CAT28C512LI12 , 512K-Bit CMOS PARALLEL EEPROM
CAT28C512LI-12 , 512K-Bit CMOS PARALLEL EEPROM
CAT28C512LI-15 , 512K-Bit CMOS PARALLEL EEPROM
CAT28C64B ,64 kb CMOS Parallel EEPROMBLOCK DIAGRAM8,192 x 8ROWADDR. BUFFERA –AEEPROM5 12DECODER& LATCHESARRAYINADVERTENT HIGH VOLTAGE32 ..
CAT28C64BG-12T , 64K-Bit CMOS PARALLEL EEPROM
CD74AC32M ,Quad 2-Input OR Gatesmaximum ratings over operating free-air temperature range (unless otherwise noted)Supply voltage ra ..
CD74AC32M ,Quad 2-Input OR Gatesmaximum ratings over operating free-air temperature range (unless otherwise noted)Supply voltage ra ..
CD74AC32M96 ,Quad 2-Input OR Gates/sc/package.FUNCTION TABLE(each gate)INPUTSOUTPUTYA BH X HX HHL L LPlease be aware that an importan ..
CD74AC32M96G4 ,Quad 2-Input OR Gates 14-SOIC -55 to 125logic diagram (positive logic)AYB†absolute
CD74AC373E ,Octal Transparent Latches with 3-State OutputsFeatures:I Exceeds 2-kV ESD Protection - MlL-S TD-883,Method 3015I SCR-Latchup-resistant CMOS proce ..
CD74AC373M ,Octal Transparent Latches with 3-State OutputsMAXIMUM RATINGS, Absolute-Maximum Values:DC SUPPLY-VOLTAGE (Vac) ..... -0.5 to 6 vDC INPUT DIODE CU ..
CAT28C257
Parallel EEPROM, 256Kb
CAT28C257
256 kb CMOS Parallel
EEPROM
DescriptionThe CA T28C257 is a fast, low power, 5 V−only CMOS Parallel
EEPROM organized as 32K x 8−bits. It requires a simple interface for
in−system programming. On−chip address and data latches,
self−timed write cycle with auto−clear and VCC power up/down write
protection eliminate additional timing and protection hardware. DATA
Polling and Toggle status bits signal the start and end of the self−timed
write cycle. Additionally, the CAT28C257 features hardware and
software write protection.
The CAT28C257 is manufactured using ON Semiconductor’s
advanced CMOS floating gate technology. It is designed to endure
100,000 program/erase cycles and has a data retention of 100 years.
The device is available in JEDEC approved 28−pin DIP or 32−pin
PLCC packages.
Features Fast Read Access Times: 120/150 ns Low Power CMOS Dissipation:
– Active: 25 mA Max.
– Standby: 150 �A Max. Simple Write Operation:
– On−chip Address and Data Latches
– Self−timed Write Cycle with Auto−clear Fast Write Cycle Time:
− 5 ms Max. CMOS and TTL Compatible I/O Automatic Page Write Operation:
− 1 to 128 Bytes in 5 ms
− Page Load Timer End of Write Detection:
− Toggle Bit
− DATA Polling Hardware and Software Write Protection 100,000 Program/Erase Cycles 100 Year Data Retention Commercial, Industrial and Automotive Temperature Ranges
