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BZA968A
Quadruple ESD transient voltage suppressor
NXP Semiconductors Product data sheet
Quadruple ESD transient voltage
suppressor BZA900A-series
FEATURES ESD rating >8 kV, according to IEC61000-4-2 SOT665 surface mount package Common anode configuration.
APPLICATIONS Computers and peripherals Audio and video equipment Communication systems
DESCRIPTIONMonolithic transient voltage suppressor diode in a five lead
SOT665 package for 4-bit wide ESD transient
suppression.
MARKING
LIMITING VALUESIn accordance with the Absolute Maximum Rating System (IEC 60134).
Notes DC working current limited by Ptot(max). Device mounted on standard printed-circuit board.
NXP Semiconductors Product data sheet
Quadruple ESD transient voltage
suppressor BZA900A-series
THERMAL CHARACTERISTICS
Note Solder point of common anode (pin 2).
ELECTRICAL CHARACTERISTICS Tj = 25 °C unless otherwise specified.
Table 1 Per type; BZ956A to BZA968A
Tj = 25 °C unless otherwise specified.
NXP Semiconductors Product data sheet
Quadruple ESD transient voltage
suppressor BZA900A-series
GRAPHICAL DATA
NXP Semiconductors Product data sheet
Quadruple ESD transient voltage
suppressor BZA900A-series
NXP Semiconductors Product data sheet
Quadruple ESD transient voltage
suppressor BZA900A-series
APPLICATION INFORMATION
Typical common anode applicationA quadruple transient suppressor in a SOT665 package makes it possible to protect four separate lines using only one
package. A simplified example is shown in Fig.7.
Device placement and printed-circuit board layoutCircuit board layout is of extreme importance in the suppression of transients. The clamping voltage of the BZA900A is
determined by the peak transient current and the rate of rise of that current (di/dt). Since parasitic inductances can further
add to the clamping voltage (V = L di/dt) the series conductor lengths on the printed-circuit board should be kept to a
minimum. This includes the lead length of the suppression element.
In addition to minimizing conductor length the following printed-circuit board layout guidelines are recommended: Place the suppression element close to the input terminals or connectors Keep parallel signal paths to a minimum Avoid running protection conductors in parallel with unprotected conductors Minimize all printed-circuit board loop areas including power and ground loops Minimize the length of the transient return path to ground Avoid using shared transient return paths to a common ground point.
