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C2611 , Collector-emitter Voltage: V(BR)CEO=400V, Collector Current: IC=0.2A
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BUK9880-55
TrenchMOS transistor Logic level FET
Philips Semiconductors Product specification
TrenchMOS transistor BUK9880-55
Logic level FET
GENERAL DESCRIPTION QUICK REFERENCE DATAN-channel enhancement mode logic
SYMBOL PARAMETER MAX. UNITlevel field-effect power transistorina
plastic envelope suitable for surface VDS Drain-source voltage 55 V
mounting. The device features very ID Drain current 7.5 A
low on-state resistance and has Ptot Total power dissipation 1.8 W
integral zener diodes giving ESD Tj Junction temperature 150 ˚C
protection.Itis intended for usein RDS(ON) Drain-source on-state 80 mΩ
automotive and general purpose resistance VGS = 5 V
switching applications.
PINNING - SOT223 PIN CONFIGURATION SYMBOL
PIN DESCRIPTION gate drain source drain (tab)
LIMITING VALUESLimiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL PARAMETER CONDITIONS MIN. MAX. UNITVDS Drain-source voltage - - 55 V
VDGR Drain-gate voltage RGS = 20 kΩ -55 V
±VGS Gate-source voltage - - 10 V Drain current (DC) Tsp = 25 ˚C - 7.5 A Drain current (DC) On PCB in Fig.2 - 3.5 A
Tamb = 25 ˚C Drain current (DC) On PCB in Fig.2 - 2.2 A
Tamb = 100 ˚C
IDM Drain current (pulse peak value) Tsp = 25 ˚C - 40 A
Ptot Total power dissipation Tsp = 25 ˚C - 8.3 W
Ptot Total power dissipation On PCB in Fig.2 - 1.8 W
Tamb = 25 ˚C
Tstg, Tj Storage & operating temperature - - 55 150 ˚C
ESD LIMITING VALUE
SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT Electrostatic discharge capacitor Human body model - 2 kV
voltage (100 pF, 1.5 kΩ)
Philips Semiconductors Product specification
TrenchMOS transistor BUK9880-55
Logic level FET
THERMAL RESISTANCES
SYMBOL PARAMETER CONDITIONS TYP. MAX. UNITRth j-sp From junction to solder point Mounted on any PCB 12 15 K/W
Rth j-amb From junction to ambient Mounted on PCB of Fig.18 - 70 K/W
STATIC CHARACTERISTICSTj= 25˚C unless otherwise specified
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNITV(BR)DSS Drain-source breakdown VGS = 0 V; ID = 0.25 mA 55 - - V
voltage Tj = -55˚C 50 - - V
VGS(TO) Gate threshold voltage VDS = VGS; ID = 1 mA 1.0 1.5 2.0 V
Tj = 150˚C 0.6 - - Vj = -55˚C - - 2.3 VDSS Zero gate voltage drain current VDS = 55 V; VGS = 0 V; - 0.05 10 μA
Tj = 150˚C - - 100 μA
IGSS Gate source leakage current VGS = ±5 V - 0.02 1 μA
Tj = 150˚C - - 5 μA
±V(BR)GSS Gate source breakdown voltage IG = ±1 mA 10 - - V DS(ON) Drain-source on-state VGS = 5 V; ID = 5 A - 65 80 mΩ
resistance Tj = 150˚C - - 148 mΩ
DYNAMIC CHARACTERISTICSmb = 25˚C unless otherwise specified
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNITgfs Forward transconductance VDS = 25 V; ID = 5 A; Tj = 25˚C 4 8 - S
Ciss Input capacitance VGS = 0 V; VDS = 25 V; f = 1 MHz - 500 650 pF
Coss Output capacitance - 110 135 pF
Crss Feedback capacitance - 60 85 pF
td on Turn-on delay time VDD = 30 V; ID = 7 A; - 10 15 ns Turn-on rise time VGS = 5 V; RG = 10 Ω; - 30 50 nsd off Turn-off delay time - 30 45 ns Turn-off fall time Tj = 25˚C - 30 40 ns
REVERSE DIODE LIMITING VALUES AND CHARACTERISTICSTj = -55 to 175˚C unless otherwise specified
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNITIDR Continuous reverse drain Tsp = 25˚C - - 7.5 A
current
IDRM Pulsed reverse drain current Tsp = 25˚C - - 40 A
VSD Diode forward voltage IF = 5 A; VGS = 0 V - 0.85 1.1 V
trr Reverse recovery time IF = 5 A; -dIF/dt = 100 A/μs; - 38 - ns
Qrr Reverse recovery charge VGS = -10 V; VR = 30 V - 0.2 - μC
Philips Semiconductors Product specification
TrenchMOS transistor BUK9880-55
Logic level FET
AVALANCHE LIMITING VALUE
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNITWDSS Drain-source non-repetitive ID = 2.5 A; VDD ≤ 25 V; - - 30 mJ
unclamped inductive turn-off VGS = 5 V; RGS = 50 Ω; Tsp = 25 ˚C
energy
Fig.1. Normalised power dissipation.
PD% = 100⋅PD/PD 25 ˚C = f(Tsp)
Fig.2. Normalised continuous drain current.
ID% = 100⋅ID/ID 25 ˚C = f(Tsp); conditions: VGS ≥ 5 V
Fig.3. Safe operating area. Tsp = 25 ˚C
ID & IDM = f(VDS); IDM single pulse; parameter tp
Fig.4. Transient thermal impedance.
Zth j-sp = f(t); parameter D = tp/T 20 40 60 80 100 120 140
Tmb / C
PD% Normalised Power Derating120
110
100
90
80
70
60
50
40
30
20
10 10 1000.1
VDS/V
RDS(ON) = VDS/ID
ID/A 20 40 60 80 100 120 140
Tmb / C
ID% Normalised Current Derating120
110
100
90
80
70
60
50
40
30
20
10
1.0E-06 0.0001 0.01 1 1000.01
100 Zth/ (K/W)
t/s
Philips Semiconductors Product specification
TrenchMOS transistor BUK9880-55
Logic level FETFig.5. Typical output characteristics, Tj = 25 ˚C.
ID = f(VDS); parameter VGS
Fig.6. Typical on-state resistance, Tj = 25 ˚C.
RDS(ON) = f(ID); parameter VGS
Fig.7. Typical transfer characteristics.
Fig.8. Typical transconductance, Tj = 25 ˚C.
gfs = f(ID); conditions: VDS = 25 V
Fig.9. Normalised drain-source on-state resistance.
a = RDS(ON)/RDS(ON)25 ˚C = f(Tj); ID = 5 A; VGS = 5 V
Fig.10. Gate threshold voltage. 246 8 100
ID/A
VDS/V 5.6
2.4 5 10 15 205
gfs/S
ID/A 1015202570
115 RDS(ON)/mOhm
ID/A
-100 -50 0 50 100 150 200
Tmb / degC
Rds(on) normalised to 25degCa
ID/A
VGS/V
-100 -50 0 50 100 150 2000
Tj / C
Philips Semiconductors Product specification
TrenchMOS transistor BUK9880-55
Logic level FETFig.11. Sub-threshold drain current.
ID = f(VGS); conditions: Tj = 25 ˚C; VDS = VGS
Fig.12. Typical capacitances, Ciss, Coss, Crss.
C = f(VDS); conditions: VGS = 0 V; f = 1 MHz
Fig.13. Typical turn-on gate-charge characteristics.
Fig.14. Typical reverse diode current.
IF = f(VSDS); conditions: VGS = 0 V; parameter Tj
Fig.15. Normalised avalanche energy rating.
WDSS% = f(Tsp); conditions: ID = 2.5 A
Fig.16. Avalanche energy test circuit. 0.5 1 1.5 2 2.5 31E-05
1E-05
1E-04
1E-03
1E-02
1E-01 Sub-Threshold Conduction 0.5 1 1.5 20
IF/A
VSDS/V
0.01 0.1 1 10 100
Thousands pF
VDS/V
Ciss
Coss
Crss 20 40 60 80 100 120 140
Tmb / C
120
110
100
90
80
70
60
50
40
30
20
10
WDSS% 2468 10 120
VDS/V
QG/nC
T.U.T.
VDD
VGS=0.5 ⋅LI⋅BV /(BV −V)
Philips Semiconductors Product specification
TrenchMOS transistor BUK9880-55
Logic level FETFig.17. Switching test circuit.
VDDVGS
