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BUK9616-55A
TrenchMOS(tm) transistor Logic level FET
Philips Semiconductors Product specification
TrenchMOS transistor BUK9516-55A
Logic level FET BUK9616-55A
GENERAL DESCRIPTION QUICK REFERENCE DATAN-channel enhancement mode logic
SYMBOL PARAMETER MAX. UNITlevel field-effect power transistorina
plastic envelope available in VDS Drain-source voltage 55 V
TO220AB and SOT404. Using ID Drain current (DC) 66 A
’trench’ technology which features Ptot Total power dissipation 138 W
very low on-state resistance.Itis Tj Junction temperature 175 ˚C
intended for usein automotive and RDS(ON) Drain-source on-state
general purpose switching resistance VGS = 5 V 16 mΩ
applications. VGS = 10 V 15 mΩ
PINNING
TO220AB & SOT404 PIN CONFIGURATION SYMBOL
PIN DESCRIPTION gate drain source
tab/mb drain
LIMITING VALUESLimiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL PARAMETER CONDITIONS MIN. MAX. UNITVDS Drain-source voltage - - 55 V
VDGR Drain-gate voltage RGS = 20 kΩ -55 V
±VGS Gate-source voltage - - 10 V
±VGSM Non-repetitive gate-source voltage tp≤50μS - 15 V Drain current (DC) Tmb = 25 ˚C - 66 A Drain current (DC) Tmb = 100 ˚C - 46 A
IDM Drain current (pulse peak value) Tmb = 25 ˚C - 263 A
Ptot Total power dissipation Tmb = 25 ˚C - 138 W
Tstg, Tj Storage & operating temperature - - 55 175 ˚C
THERMAL RESISTANCES
SYMBOL PARAMETER CONDITIONS TYP. MAX. UNITRth j-mb Thermal resistance junction to - - 1.1 K/W
mounting base
Rth j-a Thermal resistance junction to in free air 60 - K/W
ambient(TO220AB)
Rth j-a Thermal resistance junction to Minimum footprint, FR4 50 - K/W
ambient(SOT404) board
Philips Semiconductors Product specification
TrenchMOS transistor BUK9516-55A
Logic level FET BUK9616-55A
STATIC CHARACTERISTICSTj= 25˚C unless otherwise specified
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNITV(BR)DSS Drain-source breakdown VGS = 0 V; ID = 0.25 mA; 55 - - V
voltage Tj = -55˚C 50 - - V
VGS(TO) Gate threshold voltage VDS = VGS; ID = 1 mA 1 1.5 2.0 V
Tj = 175˚C 0.5 - - V
Tj = -55˚C - - 2.3 V
IDSS Zero gate voltage drain current VDS = 55 V; VGS = 0 V; - 0.05 10 μA
Tj = 175˚C - - 500 μA
IGSS Gate source leakage current VGS = ±10 V; VDS = 0 V - 2 100 nA
RDS(ON) Drain-source on-state VGS = 5 V; ID = 25 A - 12.5 16 mΩ
resistance Tj = 175˚C - - 32 mΩ
VGS = 10 V; ID = 25 A - 10 15 mΩ
VGS = 4.5 V; ID = 25 A - - 17 mΩ
DYNAMIC CHARACTERISTICSTmb = 25˚C unless otherwise specified
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNITiss Input capacitance VGS = 0 V; VDS = 25 V; f = 1 MHz - 2314 3085 pF
Coss Output capacitance - 347 416 pF
Crss Feedback capacitance - 243 333 pF
td on Turn-on delay time VDD = 30 V; Rload =1.2Ω; - 45 68 ns Turn-on rise time VGS = 5 V; RG = 10 Ω - 130 195 ns
td off Turn-off delay time - 400 560 ns Turn-off fall time - 130 182 ns Internal drain inductance Measured from drain lead 6 mm - 4.5 - nH
from package to centre of die Internal drain inductance Measured from contact screw on - 3.5 - nH
tab to centre of die(TO220AB) Internal drain inductance Measured from upper edge of drain - 2.5 - nH
tab to centre of die(SOT404) Internal source inductance Measured from source lead to - 7.5 - nH
source bond pad
REVERSE DIODE LIMITING VALUES AND CHARACTERISTICSTj = 25˚C unless otherwise specified
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNITIDR Continuous reverse drain - - 66 A
current
IDRM Pulsed reverse drain current - - 263 A
VSD Diode forward voltage IF = 25 A; VGS = 0 V - 0.85 1.2 VF = 66 A; VGS = 0 V - 1.1 - V
trr Reverse recovery time IF = 20 A; -dIF/dt = 100 A/μs; - 51 164 ns
Qrr Reverse recovery charge VGS = -10 V; VR = 30 V - 102 126 nC
Philips Semiconductors Product specification
TrenchMOS transistor BUK9516-55A
Logic level FET BUK9616-55A
AVALANCHE LIMITING VALUE
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNITWDSS Drain-source non-repetitive ID = 49 A; VDD ≤ 25 V; - - 120 mJ
unclamped inductive turn-off VGS = 5 V; RGS = 50 Ω; Tmb = 25 ˚C
energy
Fig.1. Normalised power dissipation.
PD% = 100⋅PD/PD 25 ˚C = f(Tmb)
Fig.2. Normalised continuous drain current.
ID% = 100⋅ID/ID 25 ˚C = f(Tmb); conditions: VGS ≥ 5 V
Fig.3. Safe operating area. Tmb = 25 ˚C
ID & IDM = f(VDS); IDM single pulse; parameter tp
Fig.4. Transient thermal impedance.
Zth j-mb = f(t); parameter D = tp/T 20 40 60 80 100 120 140 160 180
Tmb / C
PD% Normalised Power Derating120
110
100
90
80
70
60
50
40
30
20
10 1
1000 10 100 1000VDS / V
ID / A 20 40 60 80 100 120 140 160 180
Tmb / C
ID% Normalised Current Derating120
110
100
90
80
70
60
50
40
30
20
10
Zth / (K/W)
0.000001 0.0001 0.01 1 100 10000
VDS / V
Philips Semiconductors Product specification
TrenchMOS transistor BUK9516-55A
Logic level FET BUK9616-55A
Fig.5. Typical output characteristics, Tj = 25 ˚C.
ID = f(VDS); parameter VGS
Fig.6. Typical on-state resistance, Tj = 25 ˚C.
RDS(ON) = f(ID); parameter VGS
Fig.7. Typical on-state resistance, Tj = 25 ˚C.
Fig.8. Typical transfer characteristics.
ID = f(VGS) ; conditions: VDS = 25 V; parameter Tj
Fig.9. Typical transconductance, Tj = 25 ˚C.
gfs = f(ID); conditions: VDS = 25 V
Fig.10. Normalised drain-source on-state resistance.
02468 10VDS/V
012345VGS / V
ID/A 30 40 50 60 70 80 90 100
ID / A 20406080 100ID / A
gfs / S
23456789 10
VGS / V
RDS(ON) / mOhm
-100 -50 0 50 100 150 200
Tmb / degC
Rds(on) normlised to 25degC
Philips Semiconductors Product specification
TrenchMOS transistor BUK9516-55A
Logic level FET BUK9616-55A
Fig.11. Gate threshold voltage.
VGS(TO) = f(Tj); conditions: ID = 1 mA; VDS = VGS
Fig.12. Sub-threshold drain current.
ID = f(VGS); conditions: Tj = 25 ˚C; VDS = VGS
Fig.13. Typical capacitances, Ciss, Coss, Crss.
Fig.14. Typical turn-on gate-charge characteristics.
VGS = f(QG); conditions: ID = 50 A; parameter VDS
Fig.15. Typical reverse diode current.
IF = f(VSDS); conditions: VGS = 0 V; parameter Tj
Fig.16. Normalised avalanche energy rating.
-100 -50 0 50 100 150 2000
Tj / C 102030405060
QG / nC
VGS / V 23 451E-06
1E-05
1E-04
1E-03
1E-02
1E-01 Sub-Threshold Conduction
0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4
VSDS/V
IF / A 40 60 80 100 120 140 160 180
Tmb / C
120
110
100
90
80
70
60
50
40
30
20
10
WDSS%
Philips Semiconductors Product specification
TrenchMOS transistor BUK9516-55A
Logic level FET BUK9616-55A
Fig.17. Avalanche energy test circuit. Fig.18. Switching test circuit.
T.U.T.
VDD
VGS
VDDVGSDSS= 0.5⋅LID ⋅BVDSS /(BVDSS−VDD)
