BUK9575-100A-BUK9675-100A Fast Delivery |IC PHOENIX CO.,LIMITED

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BUK9575-100A-BUK9675-100A
TrenchMOS(TM) transistor Logic level FET
Philips Semiconductors Product specification
TrenchMOS transistor BUK9575-100A
Logic level FET BUK9675-100A
GENERAL DESCRIPTION QUICK REFERENCE DATA
N-channel enhancement mode logic SYMBOL PARAMETER MAX. UNIT
level field-effect power transistorina
plastic envelope available in VDS Drain-source voltage 100 V
TO220AB and SOT404. Using ID Drain current (DC) 23 A
’trench’ technology which features Ptot Total power dissipation 99 W
very low on-state resistance.Itis Tj Junction temperature 175 ˚C
intended for usein automotive and RDS(ON) Drain-source on-state
general purpose switching resistance VGS = 5 V 75 mΩ
applications. VGS = 10 V 55 mΩ
PINNING
TO220AB & SOT404 PIN CONFIGURATION SYMBOL
PIN DESCRIPTION gate drain source
tab/mb drain
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT
VDS Drain-source voltage - - 100 V
VDGR Drain-gate voltage RGS = 20 kΩ - 100 V
±VGS Gate-source voltage - - 15 V Drain current (DC) Tmb = 25 ˚C - 23 A Drain current (DC) Tmb = 100 ˚C - 16 A
IDM Drain current (pulse peak value) Tmb = 25 ˚C - 91 A
Ptot Total power dissipation Tmb = 25 ˚C - 98 W
Tstg, Tj Storage & operating temperature - - 55 175 ˚C
THERMAL RESISTANCES
SYMBOL PARAMETER CONDITIONS TYP. MAX. UNIT
Rth j-mb Thermal resistance junction to - - 1.5 K/W
mounting base
Rth j-a Thermal resistance junction to in free air 60 - K/W
ambient(TO220AB)
Rth j-a Thermal resistance junction to Minimum footprint, FR4 50 - K/W
ambient(SOT404) board
Philips Semiconductors Product specification
TrenchMOS transistor BUK9575-100A
Logic level FET BUK9675-100A
STATIC CHARACTERISTICS
Tj= 25˚C unless otherwise specified
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
V(BR)DSS Drain-source breakdown VGS = 0 V; ID = 0.25 mA; 100 - - V
voltage Tj = -55˚C 89 - - V
VGS(TO) Gate threshold voltage VDS = VGS; ID = 1 mA 1 1.5 2.0 V
Tj = 175˚C 0.5 - - V
Tj = -55˚C - - 2.3 V
IDSS Zero gate voltage drain current VDS = 100 V; VGS = 0 V; - 0.05 10 μA
Tj = 175˚C - - 500 μA
IGSS Gate source leakage current VGS = ±10 V; VDS = 0 V - 2 100 nA
RDS(ON) Drain-source on-state VGS = 5 V; ID = 10 A - 60 75 mΩ
resistance Tj = 175˚C - - 188 mΩ
VGS = 10 V; ID = 10 A - 55 72 mΩ
VGS = 4.5 V; ID = 10 A - 61 84 mΩ
DYNAMIC CHARACTERISTICS
Tmb = 25˚C unless otherwise specified
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNITiss Input capacitance VGS = 0 V; VDS = 25 V; f = 1 MHz - 1278 1704 pF
Coss Output capacitance - 129 155 pF
Crss Feedback capacitance - 88 120 pF
td on Turn-on delay time VDD = 30 V; Rload =1.2Ω; - 13 20 ns Turn-on rise time VGS = 5 V; RG = 10 Ω - 120 168 ns
td off Turn-off delay time - 58 87 ns Turn-off fall time - 57 86 ns Internal drain inductance Measured from drain lead 6 mm - 4.5 - nH
from package to centre of die Internal drain inductance Measured from contact screw on - 3.5 - nH
tab to centre of die(TO220AB) Internal drain inductance Measured from upper edge of drain - 2.5 - nH
tab to centre of die(SOT404) Internal source inductance Measured from source lead to - 7.5 - nH
source bond pad
REVERSE DIODE LIMITING VALUES AND CHARACTERISTICS
Tj = 25˚C unless otherwise specified
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
IDR Continuous reverse drain - - 23 A
current
IDRM Pulsed reverse drain current - - 92 A
VSD Diode forward voltage IF = 10 A; VGS = 0 V - 0.85 1.2 VF = 23 A; VGS = 0 V - 1.1 - V
trr Reverse recovery time IF = 23 A; -dIF/dt = 100 A/μs; - 63 - ns
Qrr Reverse recovery charge VGS = -10 V; VR = 30 V - 0.22 - μC
Philips Semiconductors Product specification
TrenchMOS transistor BUK9575-100A
Logic level FET BUK9675-100A
AVALANCHE LIMITING VALUE
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
WDSS1 Drain-source non-repetitive ID = 14.2 A; VDD ≤ 25 V; - - 100 mJ
unclamped inductive turn-off VGS = 5 V; RGS = 50 Ω; Tmb = 25 ˚C
energy
Fig.1. Normalised power dissipation.
PD% = 100⋅PD/PD 25 ˚C = f(Tmb)
Fig.2. Normalised continuous drain current.
ID% = 100⋅ID/I D 25 ˚C = f(Tmb ); conditions: VGS ≥ 5 V
Fig.3. Safe operating area. Tmb = 25 ˚C
ID & IDM = f(VDS); IDM single pulse; parameter tp
Fig.4. Transient thermal impedance. th j-mb = f(t); parameter D = tp/T 20 40 60 80 100 120 140 160 180
Tmb / C
PD% Normalised Power Derating120
110
100
90
80
70
60
50
40
30
20
10 10 100 10001
ID/A
VDS/V 20 40 60 80 100 120 140 160 180
Tmb / C
ID% Normalised Current Derating120
110
100
90
80
70
60
50
40
30
20
10
1E-07 1E-05 1E-03 1E-01 1E+01
t/s
Zth/(K/W)
Philips Semiconductors Product specification
TrenchMOS transistor BUK9575-100A
Logic level FET BUK9675-100A
Fig.5. Typical output characteristics, Tj = 25 ˚C.
ID = f(VDS); parameter VGS
Fig.6. Typical on-state resistance, Tj = 25 ˚C.
RDS(ON) = f(VGS); conditions: ID = 25 A;
Fig.7. Typical on-state resistance, Tj = 25 ˚C.
Fig.8. Typical on-state resistance, Tj = 25 ˚C.
RDS(ON) = f(VGS); conditions: ID = 25 A;
Fig.9. Typical transfer characteristics.
ID = f(VGS) ; conditions: VDS = 25 V; parameter Tj
Fig.10. Typical transconductance, Tj = 25 ˚C. 46 8 10
VDS/V
ID/A
3456789 10
VGS/V
RDS(ON) Ohm
120 15 20 25 30 35 40
ID/A
RDS(ON)/mOhm
0.0 1.0 2.0 3.0 4.0
VGS/V
ID/A
3456789 10
VGS/V
RDS(ON) Ohm 1020 30405060
ID/A
gfs/S
Philips Semiconductors Product specification
TrenchMOS transistor BUK9575-100A
Logic level FET BUK9675-100A
Fig.11. Normalised drain-source on-state resistance.
a = RDS(ON)/RDS(ON)25 ˚C = f(Tj); ID = 25 A; VGS = 5 V
Fig.12. Gate threshold voltage.
VGS(TO) = f(Tj); conditions: ID = 1 mA; VDS = VGS
Fig.13. Sub-threshold drain current.
Fig.14. Typical capacitances, Ciss, Coss, Crss.
C = f(VDS); conditions: VGS = 0 V; f = 1 MHz
Fig.15. Typical turn-on gate-charge characteristics.
VGS = f(QG); conditions: ID = 25 A; parameter VDS
Fig.16. Typical reverse diode current.
-100 -50 0 50 100 150 200
Tmb / degC Rds(on) normalised to 25degC
0.01 0.1 1 10 100
VDS/V
ita
nF
Ciss
Coss
Crss
-100 -50 0 50 100 150 2000
Tj / C
VGS(TO) / V 5 10 15 20 25
QG / nC
VGS / V 0.5 1 1.5 2 2.5 31E-05
1E-05
1E-04
1E-03
1E-02
1E-01 Sub-Threshold Conduction
0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4VSDS/V
IF/A
Philips Semiconductors Product specification
TrenchMOS transistor BUK9575-100A
Logic level FET BUK9675-100A
Fig.17. Normalised avalanche energy rating.
WDSS% = f(Tmb); conditions: ID = 75 A
Fig.18. Avalanche energy test circuit.
Fig.19. Maximum permissible repetitive avalanche
current(IAV) versus avalanche time(tAV) for unclamped
inductive loads.
Fig.20. Switching test circuit. 40 60 80 100 120 140 160 180
Tmb / C
120
110
100
90
80
70
60
50
40
30
20
10
WDSS%
0.001 0.01 0.1 1 10
Avalanche Time, tAV (ms)
IAV
0.001 0.01 0.1 1 10
Avalanche Time, tAV (ms)
IAV
0.001 0.01 0.1 1 10
Avalanche Time, tAV (ms)
IAV
T.U.T.
VDD
VGS
VDDVGSDSS= 0.5⋅LID ⋅BVDSS /(BVDSS−VDD)

Partno	Mfg	Dc	Qty	Available	Descript
BUK9575-100A \|BUK9575100A		N/a	114	avai	TrenchMOS(TM) transistor Logic level FET
BUK9675-100A \|BUK9675100A		N/a	435	avai	N-channel TrenchMOS logic level FET