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BUK9219-55A
TrenchMOS TM logic level FET
BUK9219-55A renchMOS™ logic level FET
Rev. 01 — 24 October 2000 Product specificationM3D300
DescriptionN-channel enhancement mode field-effect power transistorina plastic package using
TrenchMOS™1 technology, featuring very low on-state resistance.
Product availability:
BUK9219-55A in SOT428 (D-PAK).
Features TrenchMOS™ technology Q101 compliant 175 °C rated Logic level compatible.
Applications Automotive and general purpose power switching: 12 V and 24 V loads. Motors, lamps and solenoids.
Pinning information TrenchMOS is a trademark of Royal Philips Electronics.
Table 1: Pinning - SOT428 (D-PAK), simplified outline and symbol gate (g)
SOT428 (D-PAK) drain (d) source (s) drain (d)
MBK091Top view
MBB076
Philips Semiconductors BUK9219-55A
TrenchMOS™ logic level FET Quick reference data Limiting values[1] IDM is limited by chip, not package.
Table 2: Quick reference dataVDS drain-source voltage (DC) − 55 V drain current (DC) Tmb =25 °C; VGS =5V − 55 A
Ptot total power dissipation Tmb =25°C − 114 W junction temperature − 175 °C
RDSon drain-source on-state resistance VGS =5V; ID=25A 15 19 mΩ
VGS= 4.5 V; ID =25A − 20 mΩ
Table 3: Limiting valuesIn accordance with the Absolute Maximum Rating System (IEC 60134).
VDS drain-source voltage (DC) − 55 V
VDGR drain-gate voltage (DC) RGS =20kΩ− 55 V
VGS gate-source voltage (DC) −±10 V
VGSM non-repetitive gate-source voltage tp≤50μs −±15 V drain current (DC) Tmb =25 °C; VGS =5V; Figure2 and3 − 55 A
Tmb= 100 °C; VGS =5V; Figure2 − 38 A
IDM peak drain current Tmb =25 °C; pulsed; tp≤10 μs; Figure3 [1]− 219 A
Ptot total power dissipation Tmb =25 °C; Figure1 − 114 W
Tstg storage temperature −55 +175 °C operating junction temperature −55 +175 °C
Source-drain diodeIDR reverse drain current (DC) Tmb =25°C − 55 A
IDRM pulsed reverse drain current Tmb =25 °C; pulsed; tp≤10μs − 219 A
Avalanche ruggednessWDSS non-repetitive avalanche energy unclamped inductive load; ID =49A;
VDS≤55 V; VGS =5V; RGS =50Ω;
startingTj =25°C 120 mJ
Philips Semiconductors BUK9219-55A
TrenchMOS™ logic level FET
Philips Semiconductors BUK9219-55A
TrenchMOS™ logic level FET Thermal characteristics
7.1 Transient thermal impedance
Table 4: Thermal characteristicsRth(j-a) thermal resistance from junction to ambient minimum footprint, FR4 board 71.4 K/W
Rth(j-mb) thermal resistance from junction to mounting
base
Figure4 1.3 K/W
Philips Semiconductors BUK9219-55A
TrenchMOS™ logic level FET Characteristics
Table 5: Characteristics =25 °C unless otherwise specified
Static characteristicsV(BR)DSS drain-source breakdown voltage ID= 0.25 mA; VGS =0V =25 °C55 −− V= −55 °C50 −− V
VGS(th) gate-source threshold voltage ID=1 mA; VDS =VGS; Figure9 =25°C 1 1.5 2 V= 175°C 0.5 −− V= −55°C −− 2.3 V
IDSS drain-source leakage current VDS =55V; VGS =0V =25°C − 0.05 10 μA= 175°C −− 500 μA
IGSS gate-source leakage current VGS= ±10 V; VDS =0V − 2 100 nA
RDSon drain-source on-state resistance VGS =5V; ID =25A; Figure7 and8 =25°C − 15 19 mΩ= 175°C −− 38 mΩ
VGS= 4.5 V; ID =25A −− 20 mΩ
VGS=10 V; ID=25A 14 17.6 mΩ
Dynamic characteristicsCiss input capacitance VGS =0V; VDS=25 V; f=1 MHz; Figure12 − 2190 2920 pF
Coss output capacitance − 380 450 pF
Crss reverse transfer capacitance − 250 345 pF
td(on) turn-on delay time VDD =30V; RL= 1.2 Ω; VGS =5V;RG =10 Ω− 45 − ns rise time − 130 − ns
td(off) turn-off delay time − 400 − ns fall time − 130 − ns internal drain inductance measured from drain lead from package to
centre of die 2.5 − nH internal source inductance measured from source lead from package to
source bond pad 7.5 − nH
Philips Semiconductors BUK9219-55A
TrenchMOS™ logic level FET
Source-drain diodeVSD source-drain (diode forward) voltageIS=25 A; VGS =0V; Figure15 − 0.85 1.2 V
trr reverse recovery time IS=20 A; dIS/dt= −100 A/μs
VGS= −10V; VDS =30V 51 − ns recovered charge − 102 − nC
Table 5: Characteristics…continued =25 °C unless otherwise specified
Philips Semiconductors BUK9219-55A
TrenchMOS™ logic level FET
