BSP100 Fast Delivery |IC PHOENIX CO.,LIMITED

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BSP100
N-channel enhancement mode TrenchMOS(tm) transistor
Philips Semiconductors Product specification
N-channel enhancement mode BSP100
TrenchMOS transistor
FEATURES SYMBOL QUICK REFERENCE DATA
• ’Trench’ technology VDSS = 30 V
• Low on-state resistance
• Fast switching ID = 6 A
• High thermal cycling performance
• Low thermal resistance RDS(ON) ≤ 100 mΩ (VGS = 10 V)
RDS(ON) ≤ 200 mΩ (VGS = 4.5 V)
GENERAL DESCRIPTION PINNING SOT223
N-channel enhancement mode PIN DESCRIPTION
field-effect transistorina plastic
envelope using ’trench’ 1 gate
technology. drain
Applications:- Motor and relay drivers 3 source d.c.to d.c. converters Logic level translator 4 drain (tab)
The BSP100is suppliedin the
SOT223 surface mounting
package.
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT
VDSS Drain-source voltage Tj = 25 ˚C to 150˚C - 30 V
VDGR Drain-gate voltage Tj = 25 ˚C to 150˚C; RGS = 20 kΩ -30 V
VGS Gate-source voltage - ± 20 V Continuous drain current Tsp = 25 ˚C - 61 A
Tsp = 100 ˚C - 4.4 A
Tamb = 25 ˚C - 3.2 A
IDM Pulsed drain current Tsp = 25 ˚C - 24 A Total power dissipation Tsp = 25 ˚C - 8.3 W
Tj, Tstg Operating junction and - 65 150 ˚C
storage temperature
THERMAL RESISTANCES
SYMBOL PARAMETER CONDITIONS TYP. MAX. UNIT
Rth j-sp Thermal resistance junction to surface mounted, FR4 12 15 K/W
solder point board
Rth j-amb Thermal resistance junction to surface mounted, FR4 70 - K/W
ambient board
Philips Semiconductors Product specification
N-channel enhancement mode BSP100
TrenchMOS transistor
AVALANCHE ENERGY LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT
EAS Non-repetitive avalanche Unclamped inductive load, IAS = 6 A; - 23 mJ
energy tp = 0.2 ms; Tj prior to avalanche = 25˚C;
VDD ≤ 15 V; RGS = 50 Ω; VGS = 10 V
IAS Non-repetitive avalanche - 6 A
current
ELECTRICAL CHARACTERISTICS
Tj= 25˚C unless otherwise specified
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT (BR)DSS Drain-source breakdown VGS = 0 V; ID = 10 μA; 30 - - V
voltage Tj = -55˚C 27 - - V
VGS(TO) Gate threshold voltage VDS = VGS; ID = 1 mA 1 2 2.8 V
Tj = 150˚C 0.4 - - V
Tj = -55˚C - 3.2 V
RDS(ON) Drain-source on-state VGS = 10 V; ID = 2.2 A - 80 100 mΩ
resistance VGS = 4.5 V; ID = 1 A - 120 200 mΩGS = 10 V; ID = 2.2 A; Tj = 150˚C - - 170 mΩ
gfs Forward transconductance VDS = 20 V; ID = 2.2 A 2 4.5 - S
ID(ON) On-state drain current VGS = 10 V; VDS = 1 V; 3.5 - - A
VGS = 4.5 V; VDS = 5 V 2 - - A
IDSS Zero gate voltage drain VDS = 24 V; VGS = 0 V; - 10 100 nA
current VDS = 24 V; VGS = 0 V; Tj = 150˚C - 0.6 10 μAGSS Gate source leakage current VGS = ±20 V; VDS = 0 V - 10 100 nA
Qg(tot) Total gate charge ID = 2.3 A; VDD = 15 V; VGS = 10 V - 6 - nC
Qgs Gate-source charge - 0.7 - nC
Qgd Gate-drain (Miller) charge - 0.7 - nC
td on Turn-on delay time VDD = 20 V; RD = 18 Ω;- 6 - ns Turn-on rise time VGS = 10 V; RG = 6 Ω -8 - ns
td off Turn-off delay time Resistive load - 21 - ns Turn-off fall time - 15 - ns Internal drain inductance Measured tab to centre of die - 2.5 - nH Internal source inductance Measured from source lead to source - 5 - nH
bond pad
Ciss Input capacitance VGS = 0 V; VDS = 20 V; f = 1 MHz - 250 - pF
Coss Output capacitance - 88 - pF
Crss Feedback capacitance - 54 - pF
Philips Semiconductors Product specification
N-channel enhancement mode BSP100
TrenchMOS transistor
REVERSE DIODE LIMITING VALUES AND CHARACTERISTICS
Tj = 25˚C unless otherwise specified
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Continuous source current Tsp = 25 ˚C - - 6 A
(body diode)
ISM Pulsed source current (body - - 24 A
diode)
VSD Diode forward voltage IF = 1.25 A; VGS = 0 V - 0.82 1.2 V
trr Reverse recovery time IF = 1.25 A; -dIF/dt = 100 A/μs; - 69 - ns
Qrr Reverse recovery charge VGS = 0 V; VR = 25 V - 55 - nC
Fig.1. Normalised power dissipation.
PD% = 100⋅PD/PD 25 ˚C = f(Tsp)
Fig.2. Normalised continuous drain current.
ID% = 100⋅ID/ID 25 ˚C = f(Tsp); conditions: VGS ≥ 10 V
Fig.4. Transient thermal impedance.
Zth j-sp = f(t); parameter D = tp/T 20 40 60 80 100 120 140
PD% Normalised Power Derating120
110
100
90
80
70
60
50
40
30
20
10
Tsp / C
BSP100
Peak Pulsed Drain Current, IDM (A) 20 40 60 80 100 120 140
ID% Normalised Current Derating120
110
100
90
80
70
60
50
40
30
20
10
Tsp / C
BSP100
1E-06 1E-05 1E-04 1E-03 1E-02 1E-01 1E+00 1E+01
Pulse width, tp (s)
Peak Pulsed Drain Current, IDM (A)
Philips Semiconductors Product specification
N-channel enhancement mode BSP100
TrenchMOS transistor
Fig.5. Typical output characteristics, Tj = 25 ˚C.
ID = f(VDS); parameter VGS
Fig.6. Typical on-state resistance, Tj = 25 ˚C.
RDS(ON) = f(ID); parameter VGS
Fig.7. Typical transfer characteristics.
Fig.8. Typical transconductance, Tj = 25 ˚C.
gfs = f(ID) ; parameter Tj
Fig.9. Normalised drain-source on-state resistance.
a = RDS(ON)/RDS(ON)25 ˚C = f(Tj)
Fig.10. Gate threshold voltage. 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.82
Drain-Source Voltage, VDS (V)
Drain Current, ID (A) 2345 678 9 10
Drain current, ID (A)
Transconductance, gfs (S)
012 34567 89 10Drain Current, ID (A)
-50 0 50 100 1500
Tj / C 0.51 1.52 2.53 3.54 4.55 5.56
Gate-source voltage, VGS (V)
Drain current, ID (A)
-60 -40 -200 20 40 60 80 100 120 140
Tj / C
VGS(TO) / V
Philips Semiconductors Product specification
N-channel enhancement mode BSP100
TrenchMOS transistor
Fig.11. Sub-threshold drain current.
ID = f(VGS); conditions: Tj = 25 ˚C; VDS = VGS
Fig.12. Typical capacitances, Ciss, Coss, Crss.
C = f(VDS); conditions: VGS = 0 V; f = 1 MHz
Fig.14. Typical reverse diode current.
IF = f(VSDS); conditions: VGS = 0 V; parameter Tj
Fig.15. Maximum permissible non-repetitive
avalanche current (IAS) versus avalanche time (tp);
unclamped inductive load
0123451E-06
1E-05
1E-04
1E-03
1E-02
1E-01
Sub-Threshold Conduction 0.10.20.30.40.50.60.70.80.91 1.11.21.31.41.5
Drain-Source Voltage, VSDS (V)
Source-Drain Diode Current, IF (A)
0.1 1 10 100
Drain-Source Voltage, VDS (V)
Capacitances, Ciss, Coss, Crss (pF)
1E-06 1E-05 1E-04 1E-03 1E-02
Avalanche time, tp (s)3691214
012 34567 89 10
Gate charge, QG (nC)
Gate-source voltage, VGS (V)
Philips Semiconductors Product specification
N-channel enhancement mode BSP100
TrenchMOS transistor
PRINTED CIRCUIT BOARD
Dimensions in mm.
Fig.16. PCB for thermal resistance and power rating for SOT223.
PCB: FR4 epoxy glass (1.6 mm thick), copper laminate (35 μm thick).

Partno	Mfg	Dc	Qty	Available	Descript
BSP100	PHILIPS	N/a	27463	avai	N-channel enhancement mode TrenchMOS(tm) transistor