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BQ2204A-BQ2204APN-BQ2204ASN
SRAM Nonvolatile Controller IC for 4 SRAM Banks
Features Power monitoring and switching
for 3-volt battery-backup applica-
tions Write-protect control 2-input decoderfor controlofup 4banksof SRAM 3-volt primary cellinputs Less than 10ns chip-enable
propagation delay 5%or 10% supply operation
General Description

The CMOS bq2204A SRAM Non-
volatile Controller Unit providesall
necessary functions for convertingto four banksof standard CMOS
SRAM into nonvolatile read/write
memory. precision comparator monitorsthe5V
VCC inputforan out-of-tolerance condi-
tion. When out-of-toleranceis detected,
the four conditioned chip-enable outputs
are forced inactiveto write-protectupto
four banksof SRAM.
Duringa power failure,the external
SRAMs are switched from the VCC
supplyto oneof two3V backup sup-
plies.Ona subsequent power-up, the
SRAMs are write-protected untila
power-valid conditionexists.
During power-valid operation,a
two-input decoder transparentlyse-
lects oneof upto four banksof
SRAM.
Dec.1992B
bq2204A SRAM Nonvolatile Controller Unit
Pin Names

VOUT Supply output
BC1–BC2 3 volt primary backup cell inputs
THS Threshold select input chip-enable active low input
CECON1– Conditioned chip-enable outputs
CECON4
A–B Decoder inputs No connect
VCC +5 volt supply input
VSS Groundto four banksof CMOS static RAM canbe battery-
backed usingthe VOUT and conditioned chip-enable out-
put pins from the bq2204A. As VCC slews down during power failure, the conditioned chip-enable outputs
CECON1 through CECON4 are forced inactive independ-
entof thechip-enable input CE.
This activity unconditionally write-protects the external
SRAMas VCC falls belowan out-of-tolerance threshold
VPFD.VPFDis selectedby the threshold select input pin,
THS.If THSis tiedto VSS,the power-fail detection occurs 4.62V typicalfor5% supply operation. THSis tiedto VCC, power-fail detection occursat
4.37V typical for 10% supply operation. The THS pin
mustbe tiedto VSSor VCCfor proper operation.a memory accessisin processto anyofthe four external
banksof SRAM during power-fail detection, that memory
cycle continuesto completion before the memoryis write-
protected.If the memory cycleis not terminated within
time tWPT,all four chip-enable outputs are unconditionally
driven high,write-protectingthe controlled SRAMs.
Pin Connections
Functional Description
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