BQ2201SNTR ,SRAM Nonvolatile Controller IC for 1 SRAM BankFunctional DescriptionAn external CMOS static RAM can be battery-backed If THS is tied to V , power ..
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BQ2201-BQ2201PN-BQ2201SN-BQ2201SN-NTR-BQ2201SNTR
SRAM Nonvolatile Controller IC for 1 SRAM Bank
Features Power monitoring and switching
for 3-volt battery-backup applica-
tions Write-protect control 3-volt primary cellinputs Less than 10ns chip-enable
propagation delay5%or 10% supply operation
General DescriptionThe CMOS bq2201 SRAM Nonvolatile
Controller Unit providesall necessary
functionsfor convertinga standard
CMOS SRAM into nonvolatile
read/writememory. precision comparator monitors the VCC inputforan out-of-tolerance
condition. When outof toleranceis
detected,a conditioned chip-enable
outputis forced inactiveto write-
protectany standard CMOSSRAM.
Duringa power failure, the external
SRAMis switched from the VCC
supplyto oneof two3V backup sup-
plies.Ona subsequent power-up,the
SRAMis write-protected untila
power-valid condition exists.
The bq2201is footprint- and timing-
compatible with industry stan-
dards with the added benefitofa
chip-enable propagation delayof
less than 10ns.
SRAM Nonvolatile Controller Unit
bq2201Oct. 1998 D
Pin NamesVOUT Supply output
BC1—BC2 3-volt primary backup cell inputs
THS Threshold select input chip-enable active low input
CECON Conditioned chip-enable output
VCC +5-volt supply input
VSS Ground No Connect
Functional Description
Pin Connections external CMOS static RAM canbe battery-backed
using the VOUT and the conditioned chip-enable output
pin fromthe bq2201.As VCC slews down duringa power
failure, the conditioned chip-enable output CECONis
forced inactive independentofthe chip-enable input CE.
This activity unconditionally write-protects external
SRAMas VCC fallstoan out-of-tolerance threshold VPFD.
VPFDis selectedby thethreshold select input pin, THS. THSis tiedto VSS, power-fail detection occursat 4.62V
typicalfor 5% supply operation.If THSis tiedto VCC,
power-fail detection occursat 4.37V typicalfor 10% sup-
ply operation. The THSpin mustbe tiedto VSSor VCCfor
properoperation.a memory accessisin process during power-fail detec-
tion, that memory cycle continuesto completion beforethe
memoryis write-protected.If the memory cycleis not ter-
minated within time tWPT, the CECON outputis uncondi-
tionally drivenhigh, write-protectingthe memory.
