AM3715CUS ,Sitara Processor 423-FCBGA 0 to 90Features123456Pseudo-SRAM• AM3715/03 Sitara ARM Microprocessors:– Flexible Asynchronous Protocol– C ..
AM401 , INDUSTRIAL VOLTAGE AMPLIFIER IC
AM402 , CURRENT CONVERTER IC
AM40N04-20D , N-Channel 40-V (D-S) MOSFET
AM40N04-20D , N-Channel 40-V (D-S) MOSFET
AM40P02-20D , P-Channel 20-V (D-S) MOSFET
AND520HW , Ultra Bright LED Lamps
AO3160 , 600V,0.04A N-Channel MOSFET
AO3162 , 600V,0.034A N-Channel MOSFET
AO3400L , N-Channel Enhancement Mode Field Effect Transistor
AO3400L , N-Channel Enhancement Mode Field Effect Transistor
AO3400L , N-Channel Enhancement Mode Field Effect Transistor
AM3715CUS
Sitara ARM Microprocessor (MPU)
AM3715, AM3703
www.ti.com SPRS616F–JUNE 2010–REVISED AUGUST 2011
AM3715, AM3703
Sitara ARM Microprocessors
Checkfor Samples: AM3715, AM3703 AM3715, AM3703 Sitara ARM Microprocessors
1.1 Features
Pseudo-SRAM•
AM3715/03 Sitara ARM Microprocessors: Flexible Asynchronous Protocol–
Compatible with OMAP™3 Architecture Control for Interfaceto Custom Logic–
Sitara™ ARM®
Microprocessor (MPU) (FPGA, CPLD, ASICs, etc.)Subsystem –
Nonmultiplexed Address/Data Mode•
Upto 1-GHz Sitara™ ARM®
Cortex™-A8 (Limited 2K-Byte Address Space)Core 1.8-V I/O and 3.0-V (MMC1 only),Also supports 300, 600, and 800-MHz
0.9-Vto 1.2-V Adaptive Processor Coreoperation
Voltage•
NEON™ SIMD Coprocessor 0.9-Vto 1.1-V Adaptive Core Logic Voltage–
POWERVR SGX™ Graphics Accelerator Note: These are default Operating(AM3715 only) Performance Point (OPP) voltages and could•
Tile Based Architecture Delivering upto be optimizedto lower values using20 MPoly/sec SmartReflex AVS.•
Universal Scalable Shader Engine: –
Commercial, Industrial, and ExtendedMulti-threaded Engine Incorporating Pixel Temperature Gradesand Vertex Shader Functionality –
Serial Communication•
Industry Standard API Support: •
5 Multichannel Buffered Serial PortsOpenGLES 1.1 and 2.0, OpenVG1.0 (McBSPs)•
Fine Grained Task Switching, Load –
512 Byte Transmit/Receive BufferBalancing, and Power Management (McBSP1/3/4/5)•
Programmable High Quality Image –
5K-Byte Transmit/Receive BufferAnti-Aliasing (McBSP2)–
External Memory Interfaces: –
SIDETONE Core Support (McBSP2 and•
SDRAM Controller (SDRC) 3 Only) For Filter, Gain, and Mix–
16, 32-bit Memory Controller With Operations1G-Byte Total Address Space –
Direct Interfaceto I2S and PCM Device Low-Power SDRAM andT Buses (SMS) and –
128 Channel Transmit/Receive Mode •
Four Master/Slave Multichannel Serial Memory Controller (McSPI) Ports USB OTG Subsystem (12-/8-Pin ULPI Interface) •
High-Speed/Full-Speed/Low-Speed With Multiport USB Subsystem128M-Byte per Chip –
12-/8-Pin ULPI Interface Serial Interface Flash, •
One HDQ/1-Wire Hamming •
Four UARTs Data and notice concerning availability, standard and usein critical applicationsof Texas and disclaimers thereto appearsatthe endof this data sheet.
