AM1808BZWTD4 ,Sitara Processor 361-NFBGA -40 to 90Features1• 375- and 456-MHz ARM926EJ-S™ RISC MPU • Programmable Real-Time Unit Subsystem(PRUSS)• AR ..
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AM186ED-40KC , ADVANCED MICROCONTROLLER from the Am186ED/EDLV family made from original AMD wafers
AM188EM-20KC , EMBEDDED STORAGE PRODUCT used in everyday office applications 16-Bit Microcontroller
AM188EM-20KC , EMBEDDED STORAGE PRODUCT used in everyday office applications 16-Bit Microcontroller
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AN12941A ,For Video·Audio
AN12942B ,For Information稢ommunication
AN12943A ,For Video·Audio
AN12943A ,For Video·Audio
AN12948A , Audio Power IC for Note PC
AN12974A ,For Video·AudioElectrical Characteristics ………….………………………………………………………. 10 Technical Data ………………………………………………………………… ..
AM1808BZCEA3-AM1808BZWTD4
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AM1808SPRS653E –FEBRUARY 2010–REVISED MARCH 2014
AM1808 ARM® Microprocessor AM1808 ARM Microprocessor
1.1 Features 375- and 456-MHz ARM926EJ-S™ RISC MPU • Programmable Real-Time Unit Subsystem
(PRUSS)• ARM926EJ-S Core Two Independent Programmable Real-Time Unit– 32-Bit and 16-Bit( Thumb®) Instructions
(PRU) Cores– Single-Cycle MAC • 32-Bit Load-Store RISC Architecture– ARM Jazelle® Technology • 4KBof Instruction RAM per Core– Embedded ICE-RT™for Real-Time Debug 512 Bytesof Data RAM per Core• ARM9™ Memory Architecture PRUSS canbe Disabled via Softwareto– 16KBof Instruction Cache Save Power– 16KBof Data Cache • Register30of Each PRUis Exported from– 8KBof RAM (Vector Table) the Subsystemin Additionto the Normal R31– 64KBof ROM Outputof the PRU Cores.• Enhanced Direct Memory Access Controller3 – Standard Power-Management Mechanism(EDMA3): • Clock Gating–2 Channel Controllers • Entire Subsystem Undera Single PSC Clock–3 Transfer Controllers Gating Domain– 64 Independent DMA Channels – Dedicated Interrupt Controller– 16 Quick DMA Channels – Dedicated Switched Central Resource– Programmable Transfer Burst Size • USB 1.1 OHCI (Host) with Integrated PHY (USB1)• 128KBof On-Chip Memory • USB 2.0 OTG Port with Integrated PHY (USB0)• 1.8-Vor 3.3-V LVCMOS I/Os (Except for USB and – USB 2.0 High- and Full-Speed ClientDDR2 Interfaces) – USB 2.0 High-, Full-, and Low-Speed Host• Two External Memory Interfaces: – End Point0 (Control)– EMIFA – End Points 1,2,3,4 (Control, Bulk, Interruptor• NOR (8-or 16-Bit-Wide Data) ISOC) RX and TX• NAND (8-or 16-Bit-Wide Data) • One Multichannel Audio Serial Port (McASP):• 16-Bit SDRAM with 128-MB Address Space – Transmit and Receive Clocks– DDR2/Mobile DDR Memory Controller with one – Two Clock Zones and16 Serial Data Pinsof the following: – Supports TDM, I2S, and Similar Formats• 16-Bit DDR2 SDRAM with 256-MB Address – DIT-CapableSpace – FIFO Buffersfor Transmit and Receive• 16-Bit mDDR SDRAM with 256-MB Address • Two Multichannel Buffered Serial Ports (McBSPs):Space – Transmit and Receive Clocks 16550-Type UART Modules: Supports TDM, I2S, and Similar Formats Signals – AC97 Audio Codec Interface – Telecom Interfaces (ST-Bus, H100) 128-Channel TDM Buffersfor Transmit (SPIs) Each with • Mbps MAC IEEE 802.3 Compliant Digital (SD)
