ADV7314KST ,Multiformat 216 MHz Video Encoder with Six NSV™ 14-Bit DACsSPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . 6 DNR Threshold . . . . . . . . . . . ..
ADV7320KSTZ ,12-bit 216MHz Video Encoder with NSV and Macrovision® Copy ProtectionGENERAL DESCRIPTION S-video (Y/C) The ADV®7320/ADV7321 are high speed, digital-to-analog EuroScart ..
ADV7321KSTZ ,12-bit 216MHz Video Encoder with NSVAPPLICATIONS Other high definition formats using async timing mode EVD players (enhanced versatile ..
ADV7322KSTZ ,Multiformat 11-Bit HDTV Video EncoderGENERAL DESCRIPTION S-video (Y/C) EuroScart RGB The ADV®7322 is a high speed, digital-to-analog enc ..
ADV7330KST ,Multiformat 11-Bit Triple DAC Video EncoderCHARACTERISTICS . . . . . . . . . . . . . . . . . . 11 Border Area . . . . . . . . . . . . . . . . ..
ADV7342BSTZ , Multiformat Video Encoder Six, 11-Bit, 297 MHz DACs
AM27S03APC , 64-Bit Inverting-Output Bipolar RAM
AM27S03PC , 64-Bit Inverting-Output Bipolar RAM
AM27S07APC , 64-Bit Inverting-Output Bipolar RAM
AM27S07DC , 64-Bit Inverting-Output Bipolar RAM
AM27S181A , 8,192-BIT (1024 X 8) BIPOLAR PROM
AM27S23APC , 2048-BIT (256X8) BIPOLAR PROM
ADV7314KST
Multiformat 216 MHz Video Encoder with Six NSV™ 14-Bit DACs
REV.0
Multiformat 216 MHz
Video Encoder with Six NSV™ 14-Bit DACs
FEATURES
High Definition Input Formats
8-/10-,16-/20-, 24-/30-Bit (4:2:2, 4:4:4) Parallel YCrCb
Compliant with:
SMPTE 293M (525p)
BTA T-1004 EDTV2 525p
ITU-R BT.1358 (625p/525p)
ITU-R BT.1362 (625p/525p)
SMPTE 274M (1080i) at 30 Hz and 25 Hz
SMPTE 296M (720p)
RGB in 3 � 10-Bit 4:4:4 Input Format
HDTV RGB Supported:
RGB and RGBHV
Other High Definition Formats Using Async
Timing Mode
High Definition Output Formats
YPrPb Progressive Scan (EIA-770.1, EIA-770.2)
YPrPb HDTV (EIA 770.3)
RGB, RGBHV
CGMS-A (720p/1080i)
Macrovision Rev 1.1 (525p/625p)
CGMS-A (525p)
Standard Definition Input Formats
CCIR-656 4:2:2 8-/10-/16-/20-Bit Parallel Input
Standard Definition Output Formats
Composite NTSC M/N
Composite PAL M/N/B/D/G/H/I, PAL-60
SMPTE 170M NTSC Compatible Composite Video
ITU-R BT.470 PAL Compatible Composite Video
S-Video (Y/C)
EuroScart RGB
Component YPrPb (Betacam, MII, SMPTE/EBU N10)
Macrovision Rev 7.1.L1
CGMS/WSS
Closed Captioning
GENERAL FEATURES
Simultaneous SD and HD Inputs and Outputs
Oversampling up to 216 MHz
Programmable DAC Gain Control
Sync Outputs in All Modes
SIMPLIFIED FUNCTIONAL BLOCK DIAGRAM
GENERAL DESCRIPTIONThe ADV®7314 is a high speed, digital-to-analog encoder on a
single monolithic chip. It includes six high speed NSV video
D/A converters with TTL compatible inputs.
The ADV7314 has separate 8-/10-/16-/20-bit input ports that
accept data in high definition and/or standard definition video
format. For all standards, external horizontal, vertical and
blanking signals, or EAV/SAV timing codes control the inser-
tion of appropriate synchronization signals into the digital data
stream and therefore the output signal.
On-Board Voltage Reference
Six 14-Bit NSV Precision Video DACs
2-Wire Serial I2C® Interface
Dual Input/Output Supply 2.5 V/3.3 V Operation
Analog and Digital Supply 2.5 V
On-Board PLL
64-Lead LQFP Package
Lead (Pb) Free Product
APPLICATIONS
High End DVD
High End PS DVD Recorders/Players
SD/Prog Scan/HDTV Display Devices
SD/HDTV Set Top Boxes
Professional Video SystemsPurchase of licensed I2C components of Analog Devices or one of its
sublicensed Associated Companies conveys a license for the purchaser under
the Philips I2C Patent Rights to use these components in an I2C system,
provided that the system conforms to the I2C Standard Specification as
defined by Philips.
ADV7314
DETAILED FEATURES
High Definition Programmable Features (720p/1080i)
2� Oversampling (148.5 MHz)
Internal Test Pattern Generator
(Color Hatch, Black Bar, Flat Field/Frame)
Fully Programmable YCrCb to RGB Matrix
Gamma Correction
Programmable Adaptive Filter Control
Programmable Sharpness Filter Control
CGMS-A (720p/1080i)
Programmable Features (525p/625p)
8� Oversampling (216 MHz Output)
Internal Test Pattern Generator
(Color Hatch, Black Bar, Flat Frame)
Individual Y and PrPb Output Delay
Gamma Correction
Programmable Adaptive Filter Control
Fully Programmable YCrCb to RGB Matrix
Undershoot Limiter
Macrovision Rev 1.1 (525p/625p)
CGMS-A (525p)
Standard Definition Programmable Features
16� Oversampling (216 MHz)
Internal Test Pattern Generator (Color Bars, Black Bar)
Controlled Edge Rates for Sync, Active Video
Individual Y and PrPb Output Delay
Gamma Correction
Digital Noise Reduction (DNR)
Multiple Chroma and Luma Filters
Luma-SSAF™ Filter with Programmable
Gain/Attenuation
PrPb SSAF
Separate Pedestal Control on Component and
Composite/S-Video Outputs
VCR FF/RW Sync Mode
Macrovision Rev 7.1.L1
CGMS/WSS
Closed Captioning
Standards Directly SupportedOther standards are supported in Async Timing mode.
*SMPTE 274M-1998: System no.6
DETAILED FUNCTIONAL BLOCK DIAGRAM
TABLE OF CONTENTSPROGRAMMABLE DAC GAIN CONTROL . . . . . . . . . .48
Gamma Correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
HD Sharpness Filter Control and Adaptive Filter
Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
HD Sharpness Filter and Adaptive Filter Application
Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
SD DIGITAL NOISE REDUCTION . . . . . . . . . . . . . . . .53
Coring Gain Border . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
Coring Gain Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
DNR Threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
Border Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
Block Size Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
DNR Input Select Control . . . . . . . . . . . . . . . . . . . . . . . .54
DNR Mode Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
Block Offset Control . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
SD ACTIVE VIDEO EDGE . . . . . . . . . . . . . . . . . . . . . . . .55
SAV/EAV Step Edge Control . . . . . . . . . . . . . . . . . . . . . .55
BOARD DESIGN AND LAYOUT CONSIDERATIONS .56
DAC Termination and Layout Considerations . . . . . . . .56
Video Output Buffer and Optional Output Filter . . . . . . .56
PC BOARD LAYOUT CONSIDERATIONS . . . . . . . . . .58
Supply Decoupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58
Digital Signal Interconnect . . . . . . . . . . . . . . . . . . . . . . .58
Analog Signal Interconnect . . . . . . . . . . . . . . . . . . . . . . .58
APPENDIX 1—COPY GENERATION MANAGEMENT
SYSTEM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
PS CGMS Data Registers 2–0 . . . . . . . . . . . . . . . . . . . . .60
SD CGMS Data Registers 2–0 . . . . . . . . . . . . . . . . . . . . .60
Function of CGMS Bits . . . . . . . . . . . . . . . . . . . . . . . . . .60
CGMS Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
APPENDIX 2—SD WIDE SCREEN SIGNALING . . . . . .62
APPENDIX 3—SD CLOSED CAPTIONING . . . . . . . . . .63
APPENDIX 4—TEST PATTERNS . . . . . . . . . . . . . . . . . .64
APPENDIX 5—SD TIMING MODES . . . . . . . . . . . . . . .66
Mode 0 (CCIR-656)—Slave Option . . . . . . . . . . . . . . . .66
Mode 0 (CCIR-656)—Master Option . . . . . . . . . . . . . . .67
Mode 1—Slave Option . . . . . . . . . . . . . . . . . . . . . . . . . . .68
Mode 1—Master Option . . . . . . . . . . . . . . . . . . . . . . . . .69
Mode 2—Slave Option . . . . . . . . . . . . . . . . . . . . . . . . . . .70
Mode 2—Master Option . . . . . . . . . . . . . . . . . . . . . . . . .71
Mode 3—Master/Slave Option . . . . . . . . . . . . . . . . . . . . .72
APPENDIX 6—HD TIMING . . . . . . . . . . . . . . . . . . . . . .73
APPENDIX 7—VIDEO OUTPUT LEVELS . . . . . . . . . . .74
HD YPrPb Output Levels . . . . . . . . . . . . . . . . . . . . . . . .74
RGB Output Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75
YPrPb Output Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . .76
APPENDIX 8—VIDEO STANDARDS . . . . . . . . . . . . . . .80
OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . .82
FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
GENERAL FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
APPLICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
SIMPLIFIED FUNCTIONAL BLOCK DIAGRAM . . . . . .1
GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . .1
DETAILED FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . .2
DETAILED FUNCTIONAL BLOCK DIAGRAM . . . . . . .2
SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
DYNAMIC SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . .5
TIMING SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . .6
ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . .14
ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
PIN CONFIGURATION . . . . . . . . . . . . . . . . . . . . . . . . . .15
PIN FUNCTION DESCRIPTIONS . . . . . . . . . . . . . . . . .15
TERMINOLOGY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
MPU PORT DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . .17
REGISTER ACCESS . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Register Programming . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Subaddress Register (SR7–SR0) . . . . . . . . . . . . . . . . . . .18
INPUT CONFIGURATION . . . . . . . . . . . . . . . . . . . . . . .31
Standard Definition Only . . . . . . . . . . . . . . . . . . . . . . . . .31
Progressive Scan Only or HDTV Only . . . . . . . . . . . . . . .31
Simultaneous Standard Definition
and Progressive Scan or HDTV . . . . . . . . . . . . . . . . . .32
Progressive Scan At 27 Mhz (Dual Edge)
or 54 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
OUTPUT CONFIGURATION . . . . . . . . . . . . . . . . . . . . .34
TIMING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
HD Async Timing Mode . . . . . . . . . . . . . . . . . . . . . . . . .35
HD Timing Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
SD Real-Time Control, Subcarrier Reset,
and Timing Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
Reset Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
SD VCR FF/RW Sync . . . . . . . . . . . . . . . . . . . . . . . . . . .38
Vertical Blanking Interval . . . . . . . . . . . . . . . . . . . . . . . . .39
SD Subcarrier Frequency Registers . . . . . . . . . . . . . . . . .39
Square Pixel Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
FILTER SECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
HD Sinc Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
SD Internal Filter Response . . . . . . . . . . . . . . . . . . . . . . .41
Typical Performance Characteristics . . . . . . . . . . . . . . . . . .42
COLOR CONTROLS AND RGB MATRIX . . . . . . . . . . .46
HD/PS Y Level, Cr Level, Cb Level . . . . . . . . . . . . . . . .46
HD RGB Matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
Programming the RGB Matrix . . . . . . . . . . . . . . . . . . . . .46
SD Luma and Color Control . . . . . . . . . . . . . . . . . . . . . .46
SD Hue Adjust Value . . . . . . . . . . . . . . . . . . . . . . . . . . . .47
SD Brightness Control . . . . . . . . . . . . . . . . . . . . . . . . . . .47
SD Brightness Detect . . . . . . . . . . . . . . . . . . . . . . . . . . . .47
Double Buffering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47
ADV7314–SPECIFICATIONS
(VAA = 2.375 V–2.625 V, VDD = 2.375 V–2.625 V; VDD_IO = 2.375 V–3.6 V,
VREF = 1.235 V, RSET = 3040 �, RLOAD = 150 �. All specifications TMIN to TMAX
(0�C to 70�C), unless otherwise noted.)NOTESOversampling disabled. Static DAC performance will be improved with increased oversampling ratios.DNL measures the deviation of the actual DAC output voltage step from the ideal. For +ve DNL, the actual step value lies above the ideal step value; for –ve DNL,
the actual step value lies below the ideal step value.Value in brackets for VDD_IO = 2.375 V–2.75 V.External current required to overdrive internal VREF.IDD, the circuit current, is the continuous current required to drive the digital core.Guaranteed maximum by characterization.IAA is the total current required to supply all DACs including the VREF circuitry and the PLL circuitry.All DACs on.
Specifications subject to change without notice.
ADV7314
DYNAMIC SPECIFICATIONS
(VAA = 2.375 V–2.625 V, VDD = 2.375 V–2.625 V; VDD_IO = 2.375 V–3.6 V, VREF = 1.235 V, RSET =
3040 �, RLOAD = 150 �. All specifications TMIN to TMAX (0�C to 70�C), unless otherwise noted.)Specifications subject to change without notice.
