ADV7304AKST ,14-bit 108MHz Video Encoder with NSV™ and Macrovision® Copy ProtectionFeatures (525 p/625 p) Luma-SSAF™ Filter with Programmable Gain/4 Oversampling (108 MHz Output) At ..
ADV7305AKST ,14-bit 108MHz Video Encoder with NSV™SPECIFICATIONS(V = V = 2.375 V–2.625 V, V = 2.375 V–3.600 V, V = 1.235 V, R = 1520 , R = 150 , T ..
ADV7310KST ,12-bit 216MHz Video Encoder with NSV™ and Macrovision® Copy ProtectionCHARACTERISTICS . . . . . . . . . . . . . . . . . . 14 Block Size Control . . . . . . . . . . . . . ..
ADV7311KST ,12-bit 216MHz Video Encoder with NSV™GENERAL DESCRIPTION®Programmable DAC Gain ControlThe ADV 7310/ADV7311 is a high speed, digital-to-a ..
ADV7312KST ,Multiformat 11-Bit HDTV Video EncoderCHARACTERISTICS . . . . . . . . . . . . . . . . . . 14 Block Size Control . . . . . . . . . . . . . ..
ADV7314KST ,Multiformat 216 MHz Video Encoder with Six NSV™ 14-Bit DACsSPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . 6 DNR Threshold . . . . . . . . . . . ..
AM27S03APC , 64-Bit Inverting-Output Bipolar RAM
AM27S03PC , 64-Bit Inverting-Output Bipolar RAM
AM27S07APC , 64-Bit Inverting-Output Bipolar RAM
AM27S07DC , 64-Bit Inverting-Output Bipolar RAM
AM27S181A , 8,192-BIT (1024 X 8) BIPOLAR PROM
AM27S23APC , 2048-BIT (256X8) BIPOLAR PROM
ADV7304AKST-ADV7305AKST
14-bit 108MHz Video Encoder with NSV™ and Macrovision® Copy Protection
REV.A
Multiformat SD, Progressive Scan/HDTV
Video Encoder with Six NSV™ 14-Bit DACsNSV (Noise Shaped Video) is a trademark of Analog Devices, Inc.
*ADV7304A Only
FEATURES
High Definition Input Formats
YCrCb Compliant to SMPTE293M (525 p),
ITU-R.BT1358 (625 p), SMPTE274M (1080 i),
SMPTE296M (720 p), and Any Other High Definition
Standard Using Async Timing Mode
RGB in 3 � 10-Bit 4:4:4 Format
BTA T-1004 EDTV2 525 p Parallel
High Definition Output Formats (525 p/625 p/720 p/1080 i)
YPrPb Progressive Scan (EIA-770.1, EIA-770.2)
YPrPb HDTV (EIA 770.3)
RGB + H/V (HDTV 5-Wire Format)
CGMS-A (720 p/1080 i)
Macrovision Rev 1.0 (525 p/625 p)*
CGMS-A (525 p)
Standard Definition Input Formats
CCIR-656 4:2:2 8-/10-Bit Parallel Input
CCIR-601 4:2:2 16-/20-Bit Parallel Input
Standard Definition Output Formats
Composite NTSC M, N;
PAL M, N, B, D, G, H, I, PAL-60
SMPTE170M NTSC Compatible Composite Video
ITU-R.BT470 PAL Compatible Composite Video
S-Video (Y/C)
EuroScart RGB
Component YUV (Betacam, MII, SMPTE/EBU N10)
Macrovision Rev 7.1*
CGMS/WSS
Closed Captioning
GENERAL FEATURES
Simultaneous SD and HD Inputs and Outputs
Oversampling (108 MHz/148.5 MHz)
On-Board Voltage Reference
6 NSV Precision Video 14-Bit �-� DACs
2-Wire Serial MPU Interface
Dual I/O Supply 2.5 V/3.3 V Operation
Analog and Digital Supply 2.5 V
On-Board PLL
64-LQFP Package
Lead-Free Product
APPLICATIONS
High End DVD Players
SD/Program Scan/HDTV Display Devices
SD/Program Scan/HDTV Set-Top Boxes
SD/HDTV Studio Equipment
Professional Video Equipment
SIMPLIFIED FUNCTIONAL BLOCK DIAGRAM
GENERAL DESCRIPTIONThe ADV7304A/ADV7305A is a high speed, digital-to-analog
encoder on a single monolithic chip. It includes six high speed
video D/A converters with TTL compatible inputs.
The ADV7304A/ADV7305A has three separate 10-bit wide input
ports that accept data in high definition and/or standard defini-
tion video format. For all standards, external horizontal, vertical,
and blanking signals, or EAV/SAV timing codes, control the
insertion of appropriate synchronization signals into the digital
data stream and therefore the output signals.
ADV7304A/ADV7305AFigure 1.Functional Block Diagram
DETAILED FEATURES
High Definition Programmable Features (720 p/1080 i)
2� Oversampling (148.5 MHz)
Internal Test Pattern Generator (Color Hatch, Black
Bar, Flat Field/Frame)
Fully Programmable YCrCb to RGB Matrix
Gamma Correction
Programmable Adaptive Filter Control
Programmable Sharpness Filter Control
CGMS-A (720 p/1080 i)
High Definition Programmable Features (525 p/625 p)
4� Oversampling (108 MHz Output)
Internal Test Pattern Generator (Color Hatch, Black
Bar, Flat Frame)
Individual Y and PrPb Output Delay
Gamma Correction
Programmable Adaptive Filter Control
Fully Programmable YCrCb to RGB Matrix
Undershoot Limiter
TERMS USED IN THIS DATA SHEETStandard Definition Video, conforming to
ITU-R.BT601/ITU-R.BT656.High Definition Video, i.e., Progressive Scan or HDTV.Progressive Scan Video, conforming to SMPTE293M
or ITU-R.BT1358.
Macrovision Rev 1.0 (525 p/625 p)*
CGMS-A (525 p)
Standard Definition Programmable Features
8� Oversampling (108 MHz)
Internal Test Pattern Generator (Color Bars, Black Bar)
Controlled Edge Rates for Sync, Active Video
Individual Y and UV Output Delay
Gamma Correction
Digital Noise Reduction
Multiple Chroma and Luma Filters
Luma-SSAF™ Filter with Programmable Gain/
Attenuation
UV SSAF
Separate Pedestal Control on Component and
Composite/S-Video Outputs
VCR FF/RW Sync Mode
Macrovision Rev 7.1*
CGMS/WSS
Closed CaptioningHDTVHigh Definition Television Video, conforming to
SMPTE274M or SMPTE296M.
YCrCbSD or HD Component Digital Video.
YPrPbHD Component Analog Video.
YUVSDComponent Analog Video.
ADV7304A/ADV7305A–SPECIFICATIONSPOWER REQUIREMENTS
NOTESNSV features enabled.DNL measures the deviation of the actual DAC o/p voltage step from the ideal. For +ve DNL, the actual step value lies above the ideal step value; for –ve DNL, the
actual step values lie below the ideal step value.Value in brackets for VDD_IO = 2.375 V to 2.750 V.IDD or the circuit current is the continuous current required to drive the digital core without the IPLL.IAA is the total current required to supply all DACs including the VREF and PLL circuitry.All DACs on.
Specifications subject to change without notice.
(VAA = VDD = 2.375V–2.625V, VDD_IO = 2.375V–3.600V, VREF = 1.235V, RSET = 1520 �, RLOAD = 150 �, TMIN to TMAX (0�C to 70�C), unless otherwise noted.)
ADV7304A/ADV7305A
DYNAMIC SPECIFICATIONSSpecifications subject to change without notice.
(VAA = VDD = 2.375V–2.625V, VDD_IO = 2.375V–3.600V, VREF = 1.235V, RSET = 1520 �,
RLOAD = 150�, TMIN to TMAX (0�C to 70�C), unless otherwise noted.)
ADV7304A/ADV7305A
TIMING SPECIFICATIONSANALOG OUTPUTS
NOTESGuaranteed by characterization.Output delay measured from the 50% point of the rising edge of CLOCK to the 50% point of DAC output full-scale transition.Data: C[9:0]; S[9:0]; Y[9:0]
Control: P_HSYNC; P_ VSYNC; P_BLANK; S_HSYNC; S_VSYNC; S_BLANK
Specifications subject to change without notice.
(VAA = VDD = 2.375V–2.625V, VDD_IO = 2.375V–3.600V, VREF = 1.235V, RSET = 1520 �,
RLOAD = 150�, TMIN to TMAX (0�C to 70�C), unless otherwise noted.)
