ADV7194KST ,Professional Extended-10⑩ Video Encoder with 54 MHz OversamplingFEATURES: FUNCTIONAL DESCRIPTION . . . . . . . . . 17BRIGHTNESS DETECT REGISTER . . . . . . . . . . ..
ADV7194KSTZ ,Professional Extended-10™ Video Encoder with 54 MHz OversamplingFEATURES: FUNCTIONAL DESCRIPTION . . . . . . . . . 17BRIGHTNESS DETECT REGISTER . . . . . . . . . . ..
ADV7196AKS ,Multiformat Progressive Scan/HDTV Encoder with Three 11-Bit DACs, 10-Bit Data Input, and MacrovisionGENERAL DESCRIPTIONAnticopy algorithm in 525p mode.The ADV7196A is a triple high-speed, digital-to- ..
ADV7197KS ,Multiformat HDTV Encoder with Three 11-Bit DACsGENERAL DESCRIPTIONcodes control the insertion of appropriate synchronization signalsThe ADV7197 is ..
ADV7300AKST ,Multiformat SD, Progressive Scan/HDTV Video Encoder with Six NSV⑩ 12-Bit DACsFEATURES SIMPLIFIED FUNCTIONAL BLOCK DIAGRAMHigh Definition Input FormatsYCrCb Compliant to SMPTE29 ..
ADV7301AKST ,Multiformat SD, Progressive Scan/HDTV Video Encoder with Six NSV⑩ 12-Bit DACsSPECIFICATIONS(V = V = 2.375 V–2.625 V, V = 2.375 V–3.600 V, V = 1.235 V, R = 760 , R = 150 , T t ..
AM27H010 , 1 Megabit (131,072 x 8-bit) High Speed CMOS EPROM
AM27H010-45DC , 1 Megabit (131,072 x 8-bit) High Speed CMOS EPROM
AM27H010-45DI , 1 Megabit (131,072 x 8-bit) High Speed CMOS EPROM
AM27S03APC , 64-Bit Inverting-Output Bipolar RAM
AM27S03PC , 64-Bit Inverting-Output Bipolar RAM
AM27S07APC , 64-Bit Inverting-Output Bipolar RAM
ADV7194KST
Professional Extended-10⑩ Video Encoder with 54 MHz Oversampling
REV.0
Professional Extended-10™
Video Encoder with 54MHz Oversampling
SIMPLIFIED BLOCK DIAGRAM*This device is protected by U.S. Patent Numbers 4631603, 4577216, and 4819098 and other intellectual property rights.
Extended-10 is a trademark of Analog Devices, Inc. This technology combines 10-bit conversion, 10-bit digital video data processing, and 10-bit external interfacing.
SSAF is a trademark of Analog Devices Inc.
ITU-R and CCIR are used interchangeably in this document (ITU-R has replaced CCIR recommendations).2C is a registered trademark of Philips Corporation.
FEATURES
10-Bit Extended CCIR-656 Input Data Port
Six High-Quality 10-Bit Video DACs
10-Bit Internal Digital Video Processing
Multistandard Video Input
Multistandard Video Output
4� Oversampling with Internal 54MHz PLL
Programmable Video Control Includes:
Digital Noise Reduction
Gamma Correction
Black Burst
LUMA Delay
CHROMA Delay
Multiple Luma and Chroma Filters
Luma SSAF™ (Super Sub-Alias Filter)
Average Brightness Detection
Field Counter
CGMS (Copy Generation Management System)
WSS (Wide Screen Signaling)
Closed Captioning Support
Teletext Insertion Port (PAL-WST)
2-Wire Serial MPU Interface (I2C Compatible and
Fast I2C)
Supply Voltage 5 V and 3.3 V Operation
80-Lead LQFP Package
GENERAL DESCRIPTIONThe ADV7194 is part of the new generation of video encoders
from Analog Devices. The device builds on the performance of
previous video encoders and provides new features like inter-
facing progressive scan devices, digital noise reduction, gamma
correction, 4× oversampling and 54MHz operation, average
brightness detection, black burst signal generation, chroma delay,
an additional Chroma Filter, etc.
The ADV7194 supports NTSC-M, NTSC-N (Japan), PAL N,
PAL-B/D/G/H/I and PAL-60 standards. Input standards sup-
ported include ITU-R.BT656 4:2:2 YCrCb in 8-, 10-, 16- or
20-bit format and 3× 10-bit YCrCb progressive scan format.
The ADV7194 can output composite video (CVBS), S-Video
(Y/C), Component YUV or RGB and analog progressive scan in
YPrPb format. The analog component output is also compatible
with Betacam, MII and SMPTE/EBU N10 levels, SMPTE 170M
NTSC and ITU-R.BT 470 PAL.
For more information about the ADV7194’s features refer to
Detailed Description of Features section.
APPLICATIONS
Professional DVD Playback Systems
PC Video/Multimedia Playback Systems
Progressive Scan Playback Systems
Professional Studio Equipment
ADV7194
CONTENTSFEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
APPLICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . .1
SIMPLIFIED BLOCK DIAGRAM . . . . . . . . . . . . . . . . . . . 1
SPECIFICATIONS
5 V Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
3.3 V Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
5 V Dynamic Specifications . . . . . . . . . . . . . . . . . . . . . . . . 5
3.3 V Dynamic Specifications . . . . . . . . . . . . . . . . . . . . . . . 5
5 V Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 6
3.3 V Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . 7
ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . 9
PIN CONFIGURATION . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
PACKAGE THERMAL PERFORMANCE . . . . . . . . . . . . . 9
PIN FUNCTION DESCRIPTIONS . . . . . . . . . . . . . . . . . 10
DETAILED DESCRIPTION OF FEATURES . . . . . . . . . 11
GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . .11
DATA PATH DESCRIPTION . . . . . . . . . . . . . . . . . . . . . 12
INTERNAL FILTER RESPONSE . . . . . . . . . . . . . . . . . . . 13
FEATURES: FUNCTIONAL DESCRIPTION . . . . . . . . . 17
BLACK BURST OUTPUT . . . . . . . . . . . . . . . . . . . . . . . . 17
BRIGHTNESS DETECT . . . . . . . . . . . . . . . . . . . . . . . . . . 17
CHROMA/LUMA DELAY . . . . . . . . . . . . . . . . . . . . . . . . 17
CLAMP OUTPUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
CSO, HSO AND VSO OUTPUTS . . . . . . . . . . . . . . . . . . . 17
COLOR BAR GENERATION . . . . . . . . . . . . . . . . . . . . . . 17
COLOR BURST SIGNAL CONTROL . . . . . . . . . . . . . . . 17
COLOR CONTROLS . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
CHROMINANCE CONTROL . . . . . . . . . . . . . . . . . . . . . 17
UNDERSHOOT LIMITER . . . . . . . . . . . . . . . . . . . . . . . . 18
DIGITAL NOISE REDUCTION . . . . . . . . . . . . . . . . . . . . 18
DOUBLE BUFFERING . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
GAMMA CORRECTION CONTROL . . . . . . . . . . . . . . . 18
NTSC PEDESTAL CONTROL . . . . . . . . . . . . . . . . . . . . . 18
POWER-ON RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
PROGRESSIVE SCAN INPUT . . . . . . . . . . . . . . . . . . . . . 18
REAL-TIME CONTROL, SUBCARRIER RESET, AND
TIMING RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
SCH PHASE MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
SLEEP MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
SQUARE PIXEL MODE . . . . . . . . . . . . . . . . . . . . . . . . . . 19
VERTICAL BLANKING DATA INSERTION
AND BLANK INPUT . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
YUV LEVELS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
20-/16-BIT INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4× OVERSAMPLING AND INTERNAL PLL . . . . . . . . . 20
VIDEO TIMING DESCRIPTION . . . . . . . . . . . . . . . . . . . 20
REGISTER ACCESSES . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
REGISTER PROGRAMMING . . . . . . . . . . . . . . . . . . . . . 29
MODE REGISTERS 0–9 . . . . . . . . . . . . . . . . . . . . . . . 30–35
TIMING REGISTERS 0–17 . . . . . . . . . . . . . . . . . . . . . . .36
SUBCARRIER FREQUENCY AND
PHASE REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
CLOSED CAPTIONING REGISTERS . . . . . . . . . . . . . . . 37
NTSC PEDESTAL/PAL TELETEXT CONTROL
REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
TELETEXT REQUEST CONTROL REGISTER . . . . . . 38
CGMS_WSS REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . 38
CONTRAST CONTROL REGISTERS . . . . . . . . . . . . . . . 39
COLOR CONTROL REGISTERS . . . . . . . . . . . . . . . . . . 39
HUE ADJUST CONTROL REGISTER (HCR) . . . . . . . . 40
HCR BIT DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . .40
BRIGHTNESS CONTROL REGISTER (BCR) . . . . . . . . 40
BCR BIT DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . .40
SHARPNESS RESPONSE REGISTER (PR) . . . . . . . . . . . 41
PR BIT DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . .41
DNR REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
DNR BIT DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . .41
GAMMA CORRECTION REGISTERS . . . . . . . . . . . . . . 43
BRIGHTNESS DETECT REGISTER . . . . . . . . . . . . . . . . 44
OUTPUT CLOCK REGISTER . . . . . . . . . . . . . . . . . . . . . 44
OCR BIT DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . .44
APPENDIX 1
Board Design and Layout Considerations . . . . . . . . . . . . 45
APPENDIX 2
Closed Captioning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
APPENDIX 3
Copy Generation Management System (CGMS) . . . . . . . 48
APPENDIX 4
Wide Screen Signaling . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
APPENDIX 5
Teletext Insertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
APPENDIX 6
Optional Output Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
APPENDIX 7
DAC Buffering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
APPENDIX 8
Recommended Register Values . . . . . . . . . . . . . . . . . . . . 53
Power-On Reset Register Values . . . . . . . . . . . . . . . . . . . 55
APPENDIX 9
NTSC Waveforms (With Pedestal) . . . . . . . . . . . . . . . . . 56
NTSC Waveforms (Without Pedestal) . . . . . . . . . . . . . . . 57
PAL Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
UV Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Output Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Video Measurement Plots . . . . . . . . . . . . . . . . . . . . . . . . 64
APPENDIX 10
Vector Plots . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
ADV7194
5 V SPECIFICATIONS1NOTESAll measurements are made in 4× Oversampling Mode unless otherwise specified.Temperature range TMIN to TMAX: 0°C to 70°C.Guaranteed by characterization.For all inputs but PAL_NTSC and ALSB.For PAL_NTSC and ALSB inputs.For all outputs but VSO/TIX/CLAMP.For VSO/TTX/CLAMP outputs.Measurement made in 2× Oversampling Mode.IDAC is the total current required to supply all DACs including the VREF circuitry.All six DACs on.ICCT or the circuit current, is the continuous current required to drive the digital core without IPLL.
Specifications subject to change without notice.
(VAA = 5 V, VREF = 1.235 V, RSET1,2 = 1200 � unless otherwise noted. All specifications TMIN to TMAX2 unless
otherwise noted.)SPECIFICATIONS
ADV7194–SPECIFICATIONS
3.3 V SPECIFICATIONS1POWER REQUIREMENTS
NOTESAll measurements are made in 4× Oversampling Mode unless otherwise specified and are guaranteed by characterization. For 2× Oversampling Mode, the power
requirements for the ADV7194 are typically 3.0V.Temperature range TMIN to TMAX: 0°C to 70°C.For all inputs but PAL_NTSC and ALSB.For PAL_NTSC and ALSB inputs.For all outputs but VSO/TTX/CLAMP.For VSO/TTX/CLAMP outputs.Measurement made in 2× Oversampling Mode.IDAC is the total current required to supply all DACs including the VREF circuitry.All six DACs on.ICCT or the circuit current, is the continuous current required to drive the digital core without IPLL.
Specifications subject to change without notice.
(VAA = 3.0 V, VREF = 1.235 V, RSET1,2 = 1200 � unless otherwise noted. All specifications TMIN to TMAX2
unless otherwise noted.)
ADV7194
5 V DYNAMIC SPECIFICATIONS1NOTESAll measurements are made in 4× Oversampling Mode unless otherwise specified.Temperature range TMIN to TMAX: 0°C to 70°C.Values in parentheses apply to 2× Oversampling Mode.
Specifications subject to change without notice.
3.3 V DYNAMIC SPECIFICATIONS1NOTESAll measurements are made in 4× Oversampling Mode unless otherwise specified.Temperature range TMIN to TMAX: 0°C to 70°C.Values in brackets apply to 2× Oversampling Mode.
Specifications subject to change without notice.
(VAA = 5 V � 250 mV, VREF = 1.235 V, RSET1,2 = 1200 � unless otherwise noted. All
specifications TMIN to TMAX2 unless otherwise noted.)
(VAA = 3.3 V � 150 mV, VREF = 1.235 V, RSET1,2 = 1200 � unless otherwise noted. All
specifications TMIN to TMAX2 unless otherwise noted.)
ADV7194
5 V TIMING CHARACTERISTICSNOTESTemperature range TMIN to TMAX: 0°C to 70°C.Guaranteed by characterization.Pixel Port consists of the following:
Data: P0–P9, Y0/P10–Y9/P19,
Control: HSYNC, VSYNC, BLANK
Clock: CLKIN Input.Teletext Port consists of:
Digital Output: TTXRQ,
Data: TTX.
Specifications subject to change without notice.
(VAA = 5 V � 250 mV, VREF = 1.235 V, RSET1,2 = 1200 � unless otherwise noted. All
specifications TMIN to TMAX1 unless otherwise noted.)
3.3 V TIMING CHARACTERISTICSNOTESTemperature range TMIN to TMAX: 0°C to 70°C.Guaranteed by characterization.Pixel Port consists of the following:
Data: P0–P9, Y0/P10–Y9/P19,
Control: HSYNC, VSYNC, BLANK
Clock: CLKIN Input.Teletext Port consists of:
Digital Output: TTXRQ,
Data: TTX.
Specifications subject to change without notice.
(VAA = 3.3 V � 150 mV, VREF = 1.235 V, RSET1,2 = 1200 � unless otherwise noted. All
specifications TMIN to TMAX1 unless otherwise noted.)2
ADV7194Figure 1.MPU Port Timing Diagram
Figure 2.Pixel and Control Data Timing Diagram
Figure 3.Teletext Timing Diagram
Figure 4.Progressive Scan Input Timing
ABSOLUTE MAXIMUM RATINGS1VAA to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
Voltage on Any Digital Input Pin . . . . GND – 0.5 V to VAA + 0.5 V
Storage Temperature (TS) . . . . . . . . . . . . . . –65°C to +150°C
Junction Temperature (TJ) . . . . . . . . . . . . . . . . . . . . . . 150°C
Body Temperature (Soldering, 10 secs) . . . . . . . . . . . . . 220°C
Analog Outputs to GND2 . . . . . . . . . . . . . . GND – 0.5 to VAA
NOTESStresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute maximum rating condi-
tions for extended periods may affect device reliability.Analog Output Short Circuit to any Power Supply or Common can be of an
indefinite duration.
PACKAGE THERMAL PERFORMANCEThe 80-lead package is used for this device. The junction-to-
ambient (θJA) thermal resistance in still air on a four-layer PCB
is 24.7°C.
To reduce power consumption when using this part the user
can run the part on a 3.3 V supply, turn off any unused DACs.
The user must at all times stay below the maximum junction
temperature of 110°C. The following equation shows how to
calculate this junction temperature:
Junction Temperature = (VAA × (IDAC + ICCT)) × θJA + 70°C (TAMB)
IDAC = 10 mA + (sum of the average currents consumed by
each powered-on DAC)
Average current consumed by each powered-on DAC =
(VREF × K )/RSET
VREF = 1.235 V
K = 4.2146
ORDERING GUIDE
CAUTIONESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection. Although
PIN CONFIGURATION
Y[0]/P10
VREF
COMP 1
DAC A
DAC B
VAA
AGND
DAC C
DAC D
AGND
VAA
DAC E
DAC F
COMP 2
RSET2
DGND
RESET
PAL_NTSC
RSET1
ALSB
SCRESET/RTC/TR
DGND
HSYNCVSYNC
BLANK
TTXREQ
DGND
AGND
SCL
SDA
CLKIN
CLKOUT
Cb[4]Cb[5]Cb[6]Cb[7]Cb[8]Cb[9]
DGNDV
Cb[3]DGNDVSO
/TTX
/CLAMP
CSO_HSOCb[2]Cb[1]Cb[0]Cr[9]Cr[8]Cr[7]Cr[6]Cr[5]V
Cr[4]Cr[3]Cr[2]Cr[1]Cr[0]
Y[1]/P11
Y[2]/P12
Y[3]/P13
Y[4]/P14
Y[5]/P15
Y[6]/P16
Y[7]/P17
Y[8]/P18
Y[9]/P19
ADV7194
PIN FUNCTION DESCRIPTIONS
DETAILED DESCRIPTION OF FEATURES
Clocking
Single 27MHz Clock Required to Run the Device
4� Oversampling with Internal 54 MHz PLL
Square Pixel Operation
Advanced Power Management
Programmable Video Control Features
Digital Noise Reduction
Black Burst Signal Generation
Pedestal level
Hue, Brightness, Contrast and Saturation
Clamping Output signal
VBI (Vertical Blanking Interval)
Subcarrier Frequency and Phase
LUMA Delay
CHROMA Delay
Gamma Correction
Luma and Chroma Filters
Luma SSAF (Super Subalias Filter)
Average Brightness Detection
Field Counter
Interlaced/Noninterlaced Operation
Complete On-Chip Video Timing Generator
Programmable Multimode Master/Slave Operation
CGMS (Copy Generation Management System)
WSS (Wide Screen Signaling)
Closed Captioning Support
Teletext Insertion Port (PAL-WST)
2-Wire Serial MPU Interface2C Compatible and Fast I2C)2C Registers Synchronized to VSYNC
Y0–Y9Cb0–Cb9Cr0–Cr9
DAC A
DAC B
DAC C
VREF
RSET2
COMP2
DAC D
DAC F
DAC E
ALSBSDASCLPAL_NTSCVSO/CLAMPCSO_HSO
HSYNC
VSYNC
BLANK
RESET
TTX
TTXRQ
P15
GENERAL DESCRIPTIONThe ADV7194 is an integrated Digital Video Encoder that con-
verts digital CCIR-601/656 4:2:2 10-bit (or 20-bit or 8-/16-bit)
component video data into a standard analog baseband television
signal compatible with worldwide standards. Additionally there
is the possibility to input video data in 3× 10-bit YCrCb progres-
sive scan format to facilitate interfacing devices such as progressive
scan systems.
There are six DACs available on the ADV7194, each of these
DACs is capable of providing 4.33mA of current. In addition to
the composite output signal there is the facility to output S-
Video (Y/C Video), RGB Video, and YUV Video. All YUV
formats (SMPTRE/EBU N10, MII or Betacam) are supported.
The on-board SSAF (Super Subalias Filter) with extended
luminance frequency response and sharp stopband attenuation
enables studio quality video playback on modern TVs, giving
optimal horizontal line resolution. An additional sharpness
control feature allows high-frequency enhancement on the lumi-
nance signal.
Figure 6.Block Diagram for DNR Mode and DNR Sharp-
ness Mode
ADV7194The output video frames are synchronized with the incoming
data timing reference codes. Optionally the encoder accepts
(and can generate) HSYNC, VSYNC and FIELD timing sig-
nals. These timing signals can be adjusted to change pulsewidth
and position while the part is in master mode.
HSO/CSO and VSO TTL outputs are also available and are
timed to the analog output video.
A separate teletext port enables the user to directly input teletext
data during the vertical blanking interval.
The ADV7194 also incorporates WSS and CGMS-A data control
generation.
The ADV7194 modes are set up over a 2-wire serial bidirectional
port (I2C-compatible) with two slave addresses and the device is
register-compatible with the ADV7172/ADV7173.
The ADV7194 is packaged in an 80-lead LQFP package.
DATA PATH DESCRIPTIONFor PAL B, D, G, H, I, N, and NTSC M, N modes, YCrCb
4:2:2 Data is input via the CCIR-656/601-compatible Pixel Port at
a 27 MHz Data Rate. The Pixel Data is demultiplexed to form
three data paths. Y typically has a range of 16 to 235, Cr and Cb
typically have a range of 128+/–112; however, it is possible to input
data from 1 to 254 on both Y, Cb, and Cr. The ADV7194 sup-
ports PAL (B, D, G, H, I, N) and NTSC M, N (with and without
Pedestal) and PAL60 standards.
Digital Noise Reduction can be applied to the Y signal. Pro-
grammable gamma correction can also be applied to the Y
signal if required.
The Y data can be manipulated for contrast control and a setup
level can be added for brightness control. The Cr, Cb data can
be scaled to achieve color saturation control. All settings become
effective at the start of the next field when double buffering is
enabled.
The appropriate sync, blank and burst levels are added to the
YCrCb data. Closed-Captioning and Teletext levels are also
added to Y and the resultant data is interpolated to 54 MHz
(4× Oversampling Mode). The interpolated data is filtered and
scaled by three digital FIR filters.
The U and V signals are modulated by the appropriate Subcarrier
Sine/Cosine waveforms and a phase offset may be added onto the
color subcarrier during active video to allow hue adjustment. The
resulting U and V signals are added together to make up the
Chrominance Signal. The Luma (Y) signal can be delayed by up
to six clock cycles (at 27 MHz) and the Chroma signal can be
delayed by up to eight clock cycles (at 27 MHz).
The Luma and Chroma signals are added together to make up
the Composite Video Signal. All timing signals are controlled.
The YCrCb data is also used to generate RGB data with appropri-
ate sync and blank levels. The YUV levels are scaled to output the
suitable SMPTE/EBU N10, MII, or Betacam levels.
Each DAC can be individually powered off if not required. A
complete description of DAC output configurations is given in
the Mode Register 2 section.
Digital noise reduction allows improved picture quality in
removing low-amplitude, high-frequency noise. The block dia-
gram below shows the DNR functionality in the two modes
available.
Programmable gamma correction is also available. The figure
below shows the response of different gamma values to a ramp
input signal.
GAMMA-CORRECTED AMPLITUDE50100150200250
LOCATIONFigure 7.Signal Input (Ramp) and Selectable Gamma
Output Curves
The device is driven by a 27 MHz clock. Data can be output atMHz or 54MHz (on-board PLL) when 4× oversampling is
enabled. Also, the filter requirements in 4× oversampling and 2×
oversampling differ, as can be seen in the figure below.
Figure 8.Output Filter Requirements in 2× and 4×
Oversampling Mode
Figure 9.PLL and 4x Oversampling Block Diagram
The ADV7194 also supports both PAL and NTSC square pixel
operation. In this case, the encoder requires a 24.5454MHz
clock for NTSC or 29.5MHz clock for PAL square pixel mode
Table I.Luminance Internal Filter Specifications (4� Oversampling)Low-Pass (NTSC)
Low-Pass (PAL)
Notch (NTSC)
Notch (PAL)
Extended (SSAF)
CIF
NOTESPassband Ripple is defined to be fluctuations from the 0 dB response in the passband, measured in (dB). The passband is defined to have 0–fc frequency limits for a
low-pass filter, 0–f1 and f2–infinity for a notch filter, where fc, f1, f2 are the –3 dB points.3 dB bandwidth refers to the –3 dB cutoff frequency.Stopband Cutoff refers to the frequency of the attenuation point referred to in Note 4.Stopband Attenuation refers to the attenuation point (dB) of the frequency referred to in Note 3.
Table II.Chrominance Internal Filter Specifications (4� Oversampling)1.3 MHz Low-Pass
0.65 MHz Low-Pass
1.0 MHz Low-Pass
2.0 MHz Low-Pass
3.0 MHz Low-Pass
CIF
NOTESPassband Ripple is defined to be fluctuations from the 0 dB response in the passband, measured in (dB). The passband is defined to have 0–fc frequency limits for a
low-pass filter, 0–f1 and f2–infinity for a notch filter, where fc, f1, f2 are the –3 dB points.3 dB bandwidth refers to the –3 dB cutoff frequency.Stopband Cutoff refers to the frequency of the attenuation point referred to in Note 4.Stopband Attenuation refers to the attenuation point (dB) of the frequency referred to in Note 3.
When used to interface progressive scan systems, the ADV7194
allows input to YCrCb signals in Progressive Scan format (3 × 10
bit) before these signals are routed to the interpolation filters
and the DACs.
INTERNAL FILTER RESPONSEThe Y Filter supports several different frequency responses
including two low-pass responses, two notch responses, an
Extended (SSAF) response with or without gain boost/attenuation,
a CIF response and a QCIF response. The UV Filter supports
several different frequency responses including five low-pass
responses, a CIF response and a QCIF response, as can be seen in
the following figures.
In Extended Mode there is the option of 12 responses in the
range from –4 dB to +4 dB. The desired response can be chosen
by the user by programming the correct value via the I2C. The
variation of frequency responses can be seen in the tables on
the following pages.
For a more detailed filter specification, refer to Analog Devices’
application note AN-562.
ADV7194
FREQUENCY – MHz
MAGNITUDE
dBFigure 10.NTSC Low-Pass Luma Filter
FREQUENCY – MHz
MAGNITUDE
dBFigure 11.PAL Low-Pass Luma Filter
MAGNITUDE
dB
FREQUENCY – MHzFigure 12.Extended Mode (SSAF) Luma Filter
MAGNITUDE
dB
FREQUENCY – MHzFigure 13.NTSC Notch Luma Filter
MAGNITUDE
dB
FREQUENCY – MHzFigure 14.PAL Notch Luma Filter
6735–1
MAGNITUDE
dB
FREQUENCY – MHzFigure 15.Extended SSAF and Programmable Gain,
Showing Range 0dB/4dB
6735–5MAGNITUDE
dB
FREQUENCY – MHzFigure 16.Extended SSAF and Programmable Attenua-
tion, Showing Range 0dB/–4dB
MAGNITUDE
dB
FREQUENCY – MHzFigure 17.Luma CIF Filter
MAGNITUDE
dB
FREQUENCY – MHzFigure 18.Chroma 0.65 MHz Low-Pass Filter
6735–12
MAGNITUDE
dB
FREQUENCY – MHz
–10Figure 19.Extended SSAF and Programmable Gain/
Attenuation, Showing Range +4dB/–12dB
MAGNITUDE
dB
FREQUENCY – MHzFigure 20.Luma QCIF Filter
MAGNITUDE
dB
FREQUENCY – MHzFigure 21.Chroma 1MHz Low-Pass Filter
ADV7194
MAGNITUDE
dB
FREQUENCY – MHzFigure 22.Chroma 1.3MHz Low-Pass Filter
MAGNITUDE
dB
FREQUENCY – MHzFigure 23.Chroma 3MHz Low-Pass Filter
MAGNITUDE
dB
FREQUENCY – MHzFigure 24.Chroma QCIF Filter
Figure 25.Chroma 2MHz Low-Pass Filter
MAGNITUDE
dB
FREQUENCY – MHzFigure 26.Chroma CIF Filter
FEATURES—FUNCTIONAL DESCRIPTION
BLACK BURST OUTPUTIt is possible to output a black burst signal from two DACs. This
signal output is very useful for professional video equipment
since it enables two video sources to be locked together. (Mode
Register 9.)
Figure 27.Possible Application for the Black Burst Output
Signal
BRIGHTNESS DETECTThis feature is used to monitor the average brightness of the
incoming Y video signal on a field by field basis. The informa-
tion is read from the I2C and based on this information the color
saturation, contrast and brightness controls can be adjusted
(for example to compensate for very dark pictures). (Bright-
ness Detect Register.)
CHROMA/LUMA DELAYThe luminance data can be delayed by maximum of six clock
cycles. Additionally the Chroma can be delayed by a maximum
of eight clock cycles (one clock cycle at 27 MHz). (Timing Reg-
ister 0 and Mode Register 9.)
Figure 28.Chroma Delay Figure 29.Luma Delay
CLAMP OUTPUTThe ADV7194 has a programmable clamp TTL output signal.
This clamp signal is programmable to the front and back porch.
The clamp signal can be varied by one to three clock cycles in
a positive and negative direction from the default position. (Mode
Register 5, Mode Register 7.)
CSO, HSO AND VSO OUTPUTSThe ADV7194 supports three output timing signals, CSO (com-
posite sync signal), HSO (Horizontal Sync Signal) and VSO
(Vertical Sync Signal). These output TTL signals are aligned
with the analog video outputs. See Figure 31 for an example
of these waveforms. (Mode Register 7.)
Figure 31.CSO, HSO, VSO Timing Diagram
COLOR BAR GENERATIONThe ADV7194 can be configured to generate 100/7.5/75/7.5
color bars for NTSC or 100/0/75/0 color bars for PAL. (Mode
Register 4.)
COLOR BURST SIGNAL CONTROLThe burst information can be switched on and off the composite
and chroma video output. (Mode Register 4.)
COLOR CONTROLSThe ADV7194 allows the user to control the brightness, contrast,
hue and saturation of the color. The control registers may be
double-buffered, meaning that any modification to the registers
will be done outside the active video region and, therefore, changes
made will not be visible during active video.
Contrast ControlContrast adjustment is achieved by scaling the Y input data by a
factor programmed by the user. This factor allows the data to be
scaled between 0% and 150%. (Contrast Control Register.)
Brightness ControlThe brightness is controlled by adding a programmable setup level
onto the scaled Y data. This brightness level may be added onto
the Y data. For NTSC with pedestal, the setup can vary from
0 IRE to 22.5 IRE. For NTSC without pedestal and PAL, the
setup can vary from –7.5 IRE to +15 IRE. (Brightness Control
Register.)
Color SaturationColor adjustment is achieved by scaling the Cr and Cb input
data by a factor programmed by the user. This factor allows the
data to be scaled between 0% and 200%. (U Scale Register and
V Scale Register.)
Hue Adjust ControlThe hue adjustment is achieved on the composite and chroma
outputs by adding a phase offset onto the color subcarrier in the
active video but leaving the color burst unmodified, i.e., only
the phase between the video and the colorburst is modified and
hence the hue is shifted. The ADV7194 provides a range of22° in increments of 0.17578125°. (Hue Adjust Register.)
CHROMINANCE CONTROL
ADV7194
UNDERSHOOT LIMITERA limiter is placed after the digital filters. This prevents any
synchronization problems for TVs. The level of undershoot is
programmable between –1.5 IRE, –6 IRE, –11 IRE when oper-
ating in 4× Oversampling Mode. In 2× Oversampling Mode the
limits are –7.5 IRE and 0 IRE. (Mode Register 9 and Timing
Register 0.)
DIGITAL NOISE REDUCTIONDNR is applied to the Y data only. A filter block selects the
high frequency, low-amplitude components of the incoming
signal (DNR Input Select). The absolute value of the filter output
is compared to a programmable threshold value (DNR Thresh-
old Control). There are two DNR modes available: DNR Mode
and DNR Sharpness Mode.
In DNR Mode, if the absolute value of the filter output is smaller
than the threshold, it is assumed to be noise. A programmable
amount (Coring Gain Control) of this noise signal will be sub-
tracted from the original signal.
In DNR Sharpness Mode, if the absolute value of the filter output
is less than the programmed threshold, it is assumed to be noise,
as before. Otherwise, if the level exceeds the threshold, now
being identified as a valid signal, a fraction of the signal (Coring
Gain Control) will be added to the original signal in order to boost
high frequency components and to sharpen the video image.
In MPEG systems it is common to process the video information
in blocks of 8 × 8 pixels for MPEG2 systems, or 16 × 16 pixels
for MPEG1 systems (Block Size Control). DNR can be applied
to the resulting block transition areas that are known to contain
noise. Generally the block transition area contains two pixels. It
is possible to define this area to contain four pixels (Border Area
Control).
It is also possible to compensate for variable block positioning or
differences in YCrCb pixel timing with the use of the Block Offset
Control. (Mode Register 8, DNR Registers 0–2.)
DOUBLE BUFFERINGDouble buffering can be enabled or disabled on the following
registers: Closed Captioning Registers, Brightness Control
Register, V-Scale Register, U-Scale Register, Contrast Control
Register, Hue Adjust Register, and the Gamma Curve Select
bit. These registers are updated once per field on the falling
edge of the VSYNC signal. Double Buffering improves the over-
all performance of the ADV7194, since modifications to register
settings will not be made during active video, but take effect on
the start of the active video. (Mode Register 8.)
GAMMA CORRECTION CONTROLGamma correction may be performed on the luma data. The
user has the choice to use either of two different gamma curves,
A or B. At any one time one of these curves is operational if
gamma correction is enabled. Gamma correction allows the
mapping of the luma data to a user-defined function. (Mode
Register 8, Gamma Correction Registers 0–13.)
NTSC PEDESTAL CONTROL
POWER-ON RESETAfter power-up, it is necessary to execute a RESET operation.
A reset occurs on the falling edge of a high-to-low transition on
the RESET pin. This initializes the pixel port such that the data
on the pixel inputs pins is ignored. See Appendix 8 for the regis-
ter settings after RESET is applied.
PROGRESSIVE SCAN INPUTIt is possible to input data to the ADV7194 in progressive scan
format. For this purpose the input pins Y0/P10–Y9/P19, Cr0–Cr9,
Cb0–Cb9 accept 10-bit Y data, 10-bit Cb data and 10-bit Cr
data. The data is clocked into the part at 27 MHz. The data
is then filtered and sinc corrected in an 2× Interpolation filter
and then output to three video DACs at 54 MHz (to interface to
a progressive scan monitor).
FREQUENCY – MHz
AMPLITUDE
dB152025
–70Figure 32. Plot of the Interpolation Filter for the Y Data
Figure 33.Plot of the Interpolation Filter for the CrCb Data
It is assumed that there is no color space conversion or any other
such operation to be performed on the incoming data. Thus if
these DAC outputs are to drive a TV, all relevant timing and
synchronization data should be contained in the incoming digital
Y data.
The block diagram below shows a possible configuration for
progressive scan mode using the ADV7194.
Figure 34.Block Diagram Using the ADV7194 in Progres-
sive Scan Mode
The progressive scan decoder deinterlaces the data from the
MPEG2 decoder. This now means that there are 525 video lines
per field in NTSC mode and 625 video lines per field in PAL
mode. The duration of the video line is now 32 µs.
It is important to note that the data from the MPEG2 decoder is
in 4:2:2 format. The data output from the progressive scan decoder
is in 4:4:4 format. Thus it is assumed that some form of interpola-
tion on the color component data is performed in the progressive
scan decoder IC. (Mode Register 8.)
REAL-TIME CONTROL, SUBCARRIER RESET AND
TIMING RESETTogether with the SCRESET/RTC/TR pin and of Mode
Register 4 (Genlock Control), the ADV7194 can be used in
(a) Timing Reset Mode, (b) Subcarrier Phase Reset Mode or
(c) RTC Mode.
(a)A TIMING RESET is achieved in holding this pin high. In
this state the horizontal and vertical counters will remain
reset. On releasing this pin (set to low), the internal counters
will commence counting again. The minimum time the pin
has to be held high is 37 ns (1 clock cycle at 27 MHz),
otherwise the reset signal might not be recognized.
(b)The SUBCARRIER PHASE will reset to that of Field 0 at
the start of the following field when a low to high transition
occurs on this input pin.
(c)In RTC MODE, the ADV7194 can be used to lock to an
external video source.
The real-time control mode allows the ADV7194 to automati-
cally alter the subcarrier frequency to compensate for line
length variations. When the part is connected to a device that
outputs a digital datastream in the RTC format (such as an
ADV7185 video decoder, see Figure 37), the part will auto-
matically change to the compensated subcarrier frequency
on a line-by-line basis. This digital datastream is 67 bits wide
and the subcarrier is contained in Bits 0 to 21. Each bit is
two clock cycles long. 00Hex should be written into all four
Subcarrier Frequency registers when using this mode. (Mode
Register 4.)
SCH PHASE MODEThe SCH phase is configured in default mode to reset every
to achieve due to clock frequency variations. This effect is reduced
by the use of a 32-bit DDS, which generates this SCH.
Resetting the SCH phase every four or eight fields avoids the
accumulation of SCH phase error, and results in very minor
SCH phase jumps at the start of the four or eight field sequence.
Resetting the SCH phase should not be done if the video source
does not have stable timing or the ADV7194 is configured in RTC
mode. Under these conditions (unstable video) the Subcarrier
Phase Reset should be enabled but no reset applied. In this
configuration the SCH Phase will never be reset; this means
that the output video will now track the unstable input video. The
Subcarrier Phase Reset when applied will reset the SCH phase
to Field 0 at the start of the next field (e.g., Subcarrier Phase
Reset applied in Field 5 (PAL) on the start of the next field SCH
phase will be reset to Field 0). (Mode Register 4.)
SLEEP MODEIf, after RESET, the SCRESET/RTC/TR and NTSC_PAL pins
are both set high, the ADV7194 will power-up in Sleep Mode to
facilitate low-power consumption before all registers have been
initialized.
If Power-up in Sleep Mode is disabled, Sleep Mode control
passes to the Sleep Mode control in Mode Register 2 (i.e., con-
trol via I2C). (Mode Register 2 and Mode Register 6.)
SQUARE PIXEL MODEThe ADV7194 can be used to operate in square pixel mode. For
NTSC operation an input clock of 24.5454 MHz is required.
Alternatively, for PAL operation, an input clock of 29.5 MHz
is required. The internal timing logic adjusts accordingly for
square pixel mode operation. Square pixel mode is not available
in 4× Oversampling mode. (Mode Register 2.)
VERTICAL BLANKING DATA INSERTION AND BLANK
INPUTIt is possible to allow encoding of incoming YCbCr data on
those lines of VBI that do not have line sync or pre-/post-equal-
ization pulses. This mode of operation is called Partial Blanking. It
allows the insertion of any VBI data (Opened VBI) into the
encoded output waveform, this data is present in digitized
incoming YCbCr data stream (e.g., WSS data, CGMS, VPS
etc.). Alternatively the entire VBI may be blanked (no VBI data
inserted) on these lines. VBI is available in all timing modes.
Complete VBI is comprised of the following lines:
525/60 systems, Lines 525 to 21 for field one and Lines 262 to
Line 284 for field two.
625/50 systems, Lines 624 to Line 22 and Lines 311 to 335.
The Opened VBI consists of:
525/60 systems, Lines 10 to 21 for field one and second half of
Line 273 to Line 284 for field two.
625/50 systems, Lines 7 to 22 and Lines 319 to 335.
(Mode Register 3.)
It is possible to allow control over the BLANK signal using
Timing Register 0. When the BLANK input is enabled (TR03 =
0 and input pin tied low), the BLANK input can be used to
ADV7194ADV7194 automatically blanks all normally blank lines as per
CCIR-624. (Timing Register 0.)
YUV LEVELSThis functionality allows the ADV7194 to output SMPTE levels
or Betacam levels on the Y output when configured in PAL or
NTSC mode.
SyncVideoBetacam286 mV714 mV
SMPTE300 mV700 mV
MII300 mV700 mV
As the data path is branched at the output of the filters the luma
signal relating to the CVBS or S-Video Y/C output is unaltered.
It is only the Y output of the YCrCb outputs that is scaled.
This control allows color component levels to have a peak-peak
amplitude of 700 mV, 1000 mV or the default values of 934 mV
in NTSC and 700 mV in PAL. (Mode Register 5.)
20-/16-BIT INTERFACEIt is possible to input data in 20-bit or 16-bit format. In this
case, the interface only operates if the data is accompanied by
separate HSYNC/VSYNC/BLANK signals. Twenty-bit or 16-
bit mode is not available in Slave Mode 0 since EAV/SAV timing
codes are used. (Mode Register 8.)
4� OVERSAMPLING AND INTERNAL PLLIt is possible to operate all six DACs at 27 MHz (2× Oversam-
pling) or 54 MHz (4× Oversampling).
The ADV7194 is supplied with a 27 MHz clock synced with the
incoming data. Two options are available: to run the device
throughout at 27 MHz or to enable the PLL. In the latter case,
even if the incoming data runs at 27 MHz, 4× Oversampling
and the internal PLL will output the data at 54 MHz.
NOTE
In 4× Oversampling Mode the requirements for the optional
output filters are different than from those in 2× Oversampling.
(Mode Register 1, Mode Register 6.)
Figure 35a.PLL and 4× Oversampling Block Diagram
Figure 35b.Output Filter Requirements in 4× Oversam-
pling Mode
VIDEO TIMING DESCRIPTIONThe ADV7194 is intended to interface to off-the-shelf MPEG1
and MPEG2 Decoders. As a consequence, the ADV7194 accepts
4:2:2 YCrCb Pixel Data via a CCIR-656 Pixel Port and has
several Video Timing Modes of operation that allow it to be
configured as either System Master Video Timing Generator or
a Slave to the System Video Timing Generator. The ADV7194
generates all of the required horizontal and vertical timing periods
and levels for the analog video outputs.
The ADV7194 calculates the width and placement of analog sync
pulses, blanking levels, and color burst envelopes. Color bursts
are disabled on appropriate lines and serration and equalization
pulses are inserted where required.
In addition, the ADV7194 supports a PAL or NTSC square pixel
operation. The part requires an input pixel clock of 24.5454 MHz
for NTSC square pixel operation and an input pixel clock of
29.5 MHz for PAL square pixel operation. The internal hori-
zontal line counters place the various video waveform sections in
the correct location for the new clock frequencies.
The ADV7194 has four distinct Master and four distinct Slave
timing configurations. Timing Control is established with the
bidirectional HSYNC, BLANK and VSYNC pins. Timing Regis-
ter 1 can also be used to vary the timing pulsewidths and where
they occur in relation to each other. (Mode Register 2, Timing
Register 0, 1.)
RESET SEQUENCEWhen RESET becomes active the ADV7194 reverts to the
default output configuration (see Appendix for register settings).
The ADV7194 internal timing is under the control of the logic
level on the NTSC_PAL pin.
When RESET is released Y, Cr, Cb values corresponding to a
black screen are input to the ADV7194. Output timing signals
are still suppressed at this stage. DACs A, B, C are switched off
and DACs D, E, F are switched on.
When the user requires valid data, Pixel Data Valid Control is
enabled (MR26 = 1) to allow the valid pixel data to pass through
the encoder. Digital output timing signals become active and
the encoder timing is now under the control of the Timing Regis-
ters. If at this stage, the user wishes to select a different video
standard to that on the NTSC_PAL pin, Standard I2C Con-
trol should be enabled (MR25 = 1) and the video standard
required is selected by programming Mode Register 0 (Out-
put Video Standard Selection). Figure 36 illustrates the RESET
sequence timing.
Figure 36.RESET Sequence Timing Diagram
Figure 37.RTC Timing and Connections
ADV7194
Mode 0 (CCIR–656):Slave Option(Timing Register 0 TR0 = X X X X X 0 0 0)
The ADV7194 is controlled by the SAV (Start Active Video) and EAV (End Active Video) Time Codes in the Pixel Data. All timing
information is transmitted using a 4-byte synchronization pattern. A synchronization pattern is sent immediately before and after
each line during active picture and retrace. Mode 0 is illustrated in Figure 38. The HSYNC, VSYNC and BLANK (if not used) pins
should be tied high during this mode. Blank output is available.
Figure 38.Timing Mode 0, Slave Mode
Mode 0 (CCIR–656):Master Option(Timing Register 0 TR0 = X X X X X 0 0 1)
The ADV7194 generates H, V, and F signals required for the SAV (Start Active Video) and EAV (End Active Video) Time Codes in
the CCIR656 standard. The H bit is output on the HSYNC pin, the V bit is output on the BLANK pin and the F bit is output on
the VSYNC pin. Mode 0 is illustrated in Figure 39 (NTSC) and Figure 40 (PAL). The H, V, and F transitions relative to the video
waveform are illustrated in Figure 41.
Figure 39.Timing Mode 0, NTSC Master Mode
Figure 40.Timing Mode 0, PAL Master Mode
Figure 41.Timing Mode 0 Data Transitions, Master Mode
ADV7194
Mode 1:Slave Option HSYNC, BLANK, FIELD(Timing Register 0 TR0 = X X X X X 0 1 0)
In this mode the ADV7194 accepts Horizontal SYNC and Odd/Even FIELD signals. A transition of the FIELD input when HSYNC is
low indicates a new frame, i.e., Vertical Retrace. The BLANK signal is optional. When the BLANK input is disabled the ADV7194
automatically blanks all normally blank lines as per CCIR-624. Mode 1 is illustrated in Figure 42 (NTSC) and Figure 43 (PAL).
Figure 42.Timing Mode 1, NTSC
Figure 43.Timing Mode 1, PAL
Mode 1:Master Option HSYNC, BLANK, FIELD(Timing Register 0 TR0 = X X X X X 0 1 1)
In this mode the ADV7194 can generate Horizontal SYNC and Odd/Even FIELD signals. A transition of the FIELD input when
HSYNC is low indicates a new frame, i.e., Vertical Retrace. The BLANK signal is optional. When the BLANK input is disabled the
ADV7194 automatically blanks all normally blank lines as per CCIR-624. Pixel data is latched on the rising clock edge follow-
ing the timing signal transitions. Mode 1 is illustrated in Figure 42 (NTSC) and Figure 43 (PAL). Figure 44 illustrates the HSYNC,
BLANK and FIELD for an odd-or-even field transition relative to the pixel data.
Figure 44.Timing Mode 1 Odd/Even Field Transitions Master/Slave
Mode 2:Slave Option HSYNC, VSYNC, BLANK(Timing Register 0 TR0 = X X X X X 1 0 0)
In this mode the ADV7194 accepts Horizontal and Vertical SYNC signals. A coincident low transition of both HSYNC and VSYNC
inputs indicates the start of an Odd Field. A VSYNC low transition when HSYNC is high indicates the start of an Even Field. The
BLANK signal is optional. When the BLANK input is disabled, the ADV7194 automatically blanks all normally blank lines as per
CCIR-624. Mode 2 is illustrated in Figure 45 (NTSC) and Figure 46 (PAL).
Figure 45.Timing Mode 2, NTSC
ADV7194Figure 46.Timing Mode 2, PAL
Mode 2:Master Option HSYNC, VSYNC, BLANK(Timing Register 0 TR0 = X X X X X 1 0 1)
In this mode the ADV7194 can generate Horizontal and Vertical SYNC signals. A coincident low transition of both HSYNC and
VSYNC inputs indicates the start of an Odd Field. A VSYNC low transition when HSYNC is high indicates the start of an Even
Field. The BLANK signal is optional. When the BLANK input is disabled, the ADV7194 automatically blanks all normally blank lines as
per CCIR-624. Mode 2 is illustrated in Figure 45 (NTSC) and Figure 46 (PAL). Figure 47 illustrates the HSYNC, BLANK and
VSYNC for an even-to-odd field transition relative to the pixel data. Figure 48 illustrates the HSYNC, BLANK and VSYNC for
an odd-to-even field transition relative to the pixel data.
Figure 47.Timing Mode 2, Even-to-Odd Field Transition Master/Slave
Mode 3:Master/Slave Option HSYNC, BLANK, FIELD
(Timing Register 0 TR0 = X X X X X 1 1 0 or X X X X X 1 1 1)In this mode the ADV7194 accepts or generates Horizontal SYNC and Odd/Even FIELD signals. A transition of the FIELD input
when HSYNC is high indicates a new frame, i.e., Vertical Retrace. The BLANK signal is optional. When the BLANK input is dis-
abled the ADV7194 automatically blanks all normally blank lines as per CCIR-624. Mode 3 is illustrated in Figure 49 (NTSC) and
Figure 50 (PAL).
Figure 49.Timing Mode 3, NTSC
Figure 50.Timing Mode 3, PAL
ADV7194
MPU PORT DESCRIPTIONThe ADV7194 supports a 2-wire serial (I2C-compatible) micro-
processor bus driving multiple peripherals. Two inputs Serial
Data (SDA) and Serial Clock (SCL) carry information between
any device connected to the bus. Each slave device is recognized
by a unique address. The ADV7194 has four possible slave ad-
dresses for both read and write operations. These are unique
addresses for each device and are illustrated in Figure 51 and
Figure 53. The LSB sets either a read or write operation. Logic
Level 1 corresponds to a read operation while Logic Level 0
corresponds to a write operation. A1 is set by setting the ALSB
pin of the ADV7194 to Logic Level 0 or Logic Level 1. When
ALSB is set to 0, there is greater input bandwidth on the I2C
lines, which allows high speed data transfers on this bus. When
ALSB is set to 1, there is reduced input bandwidth on the I2C
lines, which means that pulses of less than 50 ns will not pass
into the I2C internal controller. This mode is recommended for
noisy systems.
Figure 51.Slave Address
To control the various devices on the bus the following protocol
must be followed. First the master initiates a data transfer by
establishing a start condition, defined by a high to low transition on
SDA while SCL remains high. This indicates that an address/data
stream will follow. All peripherals respond to the start condition
and shift the next eight bits (7-bit address + R/W bit). The bits are
transferred from MSB down to LSB. The peripheral that recog-
nizes the transmitted address responds by pulling the data line
low during the ninth clock pulse. This is known as an acknowledge
bit. All other devices withdraw from the bus at this point and
maintain an idle condition. The idle condition is where the device
monitors the SDA and SCL lines waiting for the start condi-
tion and the correct transmitted address. The R/W bit determines
the direction of the data.
A Logic 0 on the LSB of the first byte means that the master
will write information to the peripheral. A Logic 1 on the LSB
of the first byte means that the master will read information
from the peripheral.
Figure 53.Write and Read Sequences
The ADV7194 acts as a standard slave device on the bus. The data
on the SDA pin is 8 bits long supporting the 7-bit addresses plus
the R/W bit. It interprets the first byte as the device address and
the second byte as the starting subaddress. The subaddresses
autoincrement allowing data to be written to or read from the
starting subaddress. A data transfer is always terminated by a
stop condition. The user can also access any unique subaddress
register on a one by one basis without having to update all the
registers. There is one exception. The Subcarrier Frequency
Registers should be updated in sequence, starting with Sub-
carrier Frequency Register 0. The autoincrement function should
be then used to increment and access Subcarrier Frequency
Registers 1, 2, and 3. The Subcarrier Frequency Registers
should not be accessed independently.
Stop and start conditions can be detected at any stage during
the data transfer. If these conditions are asserted out of sequence
with normal read and write operations, then these cause an
immediate jump to the idle condition. During a given SCL high
period the user should only issue one start condition, one stop
condition or a single stop condition followed by a single start
condition. If an invalid subaddress is issued by the user, the
ADV7194 will not issue an acknowledge and will return to the
idle condition. If in autoincrement mode, the user exceeds the
highest subaddress then the following action will be taken:In Read Mode, the highest subaddress register contents
will continue to be output until the master device issues
a no-acknowledge. This indicates the end of a read. A
no-acknowledge condition is where the SDA line is not
pulled low on the ninth pulse.In Write Mode, the data for the invalid byte will be not be
loaded into any subaddress register, a no-acknowledge will
be issued by the ADV7194 and the part will return to the
idle condition.
Figure 52.Bus Data Transfer
Figure 52 illustrates an example of data transfer for a read
sequence and the start and stop conditions.
Figure 53 shows bus write and read sequences.
REGISTER ACCESSESThe MPU can write to or read from all of the registers of the
ADV7194 except the Subaddress Registers which are write only
registers. The Subaddress Register determines which register the
next read or write operation accesses. All communications with
the part through the bus start with an access to the Subaddress
Register. Then a read/write operation is performed from/to the
target address which then increments to the next address until
a stop command on the bus is performed.
REGISTER PROGRAMMINGThe following section describes each register. All registers can
be read from as well as written to.
Subaddress Register (SR7–SR0)The Communications Register is an 8-bit write-only register. After
the part has been accessed over the bus and a read/write operation
is selected, the subaddress is set up. The Subaddress Register
determines to/from which register the operation takes place.
Figure 54 shows the various operations under the control of the
Subaddress Register 0 should always be written to SR7.
Register Select (SR6–SR0)These bits are set up to point to the required starting address.
ADV7194
MODE REGISTER 0
MR0 (MR07–MR00)
(Address (SR4–SR0) = 00H)Figure 55 shows the various operations under the control of
Mode Register 0.
MR0 BIT DESCRIPTION
Output Video Standard Selection (MR00–MR01)These bits are used to setup the encoder mode. The ADV7194
can be set up to output NTSC, PAL (B, D, G, H, I), or PAL N
standard video.
Luminance Filter Select (MR02–MR04)These bits specify which luma filter is to be selected. The filter
selection is made independent of whether PAL or NTSC is
selected.
Chrominance Filter Select (MR05–MR07)These bits select the chrominance filter. A low-pass filter can be
selected with a choice of cutoff frequencies (0.65 MHz, 1.0 MHz,
1.3 MHz, 2 MHz, or 3 MHz) along with a choice of CIF or
QCIF filters.
MODE REGISTER 1
MR1 (MR17–MR10)
(Address (SR4–SR0) = 01H)Figure 56 shows the various operations under the control of
Mode Register 1.
MR1 BIT DESCRIPTION
DAC Control (MR10–MR15)Bits MR15–MR10 can be used to power down the DACs. This are
used to reduce the power consumption of the ADV7194 or if any
of the DACs are not required in the application.
4� Oversampling Control (MR16)To enable 4× Oversampling this bit has to be set to 1. When
enabled, the data is output at a frequency of 54 MHz.
Note that PLL Enable Control has to be enabled (MR61 = 0) in
4× Oversampling mode.
Reserved (MR17)A Logical 0 must be written to this bit.
Figure 55.Mode Register 0, MR0
Figure 56.Mode Register 1, MR1
MODE REGISTER 2
MR2 (MR27–MR20)
(Address (SR4–SR0) = 02H)Mode Register 2 is an 8-bit-wide register.
Figure 57 shows the various operations under the control of Mode
Register 2.
MR2 BIT DESCRIPTION
RGB/YUV Control (MR20)This bit enables the output from the DACs to be set to YUV or
RGB output video standard.
DAC Output Control (MR21)This bit controls the output from DACs A, B, and C. When this
bit is set to 1, Composite, Luma and Chroma Signals are output
from DACs A, B and C (respectively). When this bit is set to 0,
RGB or YUV may be output from these DACs.
SCART Enable Control (MR22)This bit is used to switch the DAC outputs from SCART to a
EUROSCART configuration. A complete table of all DAC out-
put configurations is shown below.
Pedestal Control (MR23)This bit specifies whether a pedestal is to be generated on the
NTSC composite video signal. This bit is invalid when the device
is configured in PAL mode.
Square Pixel Control (MR24)This bit is used to setup square pixel mode. This is available in
Slave Mode only. For NTSC, a 24.54 MHz clock must be sup-
plied. For PAL, a 29.5 MHz clock must be supplied. Square
pixel operation is not available in 4× Oversampling mode.
Standard I2C Control (MR25)This bit controls the video standard used by the ADV7194.
When this bit is set to 1 the video standard is as programmed in
Mode Register 0 (Output Video Standard Selection). When it is
set to 0, the ADV7194 is forced into the standard selected by
the NTSC_PAL pin. When NTSC_PAL is low the standard is
NTSC, when the NTSC_PAL pin is high, the standard is PAL.
Pixel Data Valid Control (MR26)After resetting the device this bit has the value 0 and the pixel
data input to the encoder is blanked such that a black screen is
output from the DACs. The ADV7194 will be set to Master
Mode timing. When this bit is set to 1 by the user (via the I2C),
pixel data passes to the pins and the encoder reverts to the tim-
ing mode defined by Timing Mode Register 0.
Sleep Mode Control (MR27)When this bit is set (1), Sleep Mode is enabled. With this mode
enabled the ADV7194 current consumption is reduced to typically
less than 0.1 mA. The I2C registers can be written to and read
from when the ADV7194 is in Sleep Mode.
When the device is in Sleep Mode and 0 is written to MR27, the
ADV7194 will come out of Sleep Mode and resume normal
operation. Also, if a RESET is applied during Sleep Mode the
ADV7194 will come out of Sleep Mode and resume normal
operation.
For this to operate, Power up in Sleep Mode control has to be
enabled (MR60 is set to a Logic 1), otherwise Sleep Mode is
controlled by the PAL_NTSC and SCRESET/RTC/TR pins.
Figure 57.Mode Register 2, MR2
Table V.DAC Output ConfigurationNOTE
ADV7194
MODE REGISTER 3
MR3 (MR37–MR30)
(Address (SR4–SR0) = 03H)Mode Register 3 is an 8-bit-wide register. Figure 58 shows
the various operations under the control of Mode Register 3.
MR3 BIT DESCRIPTION
Revision Code (MR30–MR31)This bit is read only and indicates the revision of the device.
VBI_Open (MR32)This bit determines whether or not data in the Vertical Blanking
Interval (VBI) is output to the analog outputs or blanked. Note
that this condition is also valid in Timing Slave Mode 0. For
further information see Vertical Blanking section.
Teletext Enable (MR33)This bit must be set to 1 to enable teletext data insertion on
the TTX pin. Note: TTX functionality is shared with VSO and
CLAMP on Pin 62. CLAMP/VSO Select (MR77) and TTX
Input/CLAMP/VSO Output (MR76) have to be set accordingly.
Teletext Bit Request Mode Control (MR34)This bit enables switching of the teletext request signal from a
continuous high signal (MR34 = 0) to a bitwise request signal
(MR34 = 1).
Closed Captioning Field Control (MR35–MR36)These bits control the fields that closed captioning data is dis-
played on, closed captioning information can be displayed on
an odd field, even field or both fields.
Reserved (MR37)A Logic 0 must be written to this bit.
MODE REGISTER 4
MR4 (MR47–MR40)
(Address (SR4–SR0) = 04H)Mode Register 4 is an 8-bit-wide register. Figure 59 shows
the various operations under the control of Mode Register 4.
MR4 BIT DESCRIPTION
VSYNC_3H Control (MR40)When this bit is enabled (1) in Slave Mode, it is possible to
drive the VSYNC input low for 2.5 lines in PAL mode and
three lines in NTSC mode. When this bit is enabled in Master
Mode the ADV7194 outputs an active low VSYNC signal for
three lines in NTSC mode and 2.5 lines in PAL mode.
Genlock Control (MR41–MR42)These bits control the Genlock feature and timing reset of the
ADV7194 Setting MR41 and MR42 to Logic 0 disables the
SCRESET/RTC/TR pin and allows the ADV7194 to operate in
normal mode.By setting MR41 to zero and MR42 to one, a timing reset is
applied, resetting the horizontal and vertical counters. This
has the effect of resetting the Field Count to Field 0.
If the SCRESET/RTC/TR pin is held high, the counters
will remain reset. Once the pin is released the counters will
commence counting again. For correct counter reset, the
SCRESET/RTC/TR pin has to remain high for at least
37 ns (one clock cycle at 27 MHz).If MR41 is set to one and MR42 is set to zero, the SCRESET/
RTC/TR pin is configured as a subcarrier reset input and
the subcarrier phase will reset to Field 0 whenever a low-to-
high transition is detected on the SCRESET/RTC/TR pin
(SCH phase resets at the start of the next field).If MR41 is set to one and MR42 is set to one, the SCRESET/
RTC/TR pin is configured as a real time control input and
the ADV7194 can be used to lock to an external video source
working in RTC mode. See page TBD.
Active Video Line Duration Control (MR43)This bit switches between two active video line durations. A zero
selects CCIR Rec. 601 (720 pixels PAL/NTSC) and a one
selects ITU-R BT. 470 standard for active video duration (710
pixels NTSC, 702 pixels PAL).
Chrominance Control (MR44)This bit enables the color information to be switched on and off
the chroma, color component, composite video outputs.
Burst Control (MR45)This bit enables the color burst to be switched on and off the
chroma and composite video outputs.
Color Bar Control (MR46)This bit can be used to generate and output an internal color
bar test pattern. The color bar configuration is 100/7.5/75/7.5
for NTSC and 100/0/75/0 for PAL. It is important to note that
when color bars are enabled the ADV7194 is configured in a
Master Timing mode. The output pins VSYNC, HSYNC and
BLANK are three-state during color bar mode.
Interlaced Mode Control (MR47)This bit is used to setup the output to interlaced or noninterlaced
mode.
MODE REGISTER 5
MR5 (MR57–MR50)
(Address (SR4–SR0) = 05H)Mode Register 5 is an 8-bit-wide register. Figure 60 shows
the various operations under the control of Mode Register 5.
MR5 BIT DESCRIPTION
Y-Level Control (MR50)This bit controls the component Y output level on the ADV7194.
If this bit is set (0), the encoder outputs Betacam levels when
configured in PAL or NTSC mode. If this bit is set (1), the
encoder outputs SMPTE levels when configured in PAL or
NTSC mode.
UV-Level Control (MR51–MR52)These bits control the component U and V output levels on
the ADV7194. It is possible to have UV levels with a peak-to-
peak amplitude of either 700 mV (MR52 + MR51 = 01 ) or
1000 mV (MR52 + MR51 = 10) in NTSC and PAL. It is also
possible to have default values of 934 mV for NTSC and 700 mV
for PAL (MR52 + MR51 = 00).
RGB Sync (MR53)This bit is used to set up the RGB outputs with the sync infor-
mation encoded on all RGB outputs.
Clamp Delay (MR54–MR55)These bits control the delay or advance of the CLAMP signal in
the front or back porch of the ADV7194. It is possible to delay or
advance the pulse by zero, one, two, or three clock cycles.
Note: TTX functionality is shared with VSO and CLAMP on Pin
62. CLAMP/VSO Select (MR77) and TTX Input/CLAMP/VSO
Output (MR76) have to be set accordingly.
Clamp Delay Direction (MR56)This bit controls a positive or negative delay in the CLAMP sig-
nal. If this bit is set (1), the delay is negative. If it is set (0), the
delay is positive.
Clamp Position (MR57)This bit controls the position of the CLAMP signal. If this bit is
set (1), the CLAMP signal is located in the back porch position.
If this bit is set (0), the CLAMP signal is located in the front
porch position.
Figure 60.Mode Register 5, MR5
Figure 59.Mode Register 4, MR4
ADV7194
MODE REGISTER 6
MR6 (MR67–MR60)
(ADDRESS (SR4–SR0) = 06H)Mode Register 6 is an 8-bit-wide register. Figure 61 shows the
various operations under the control of Mode Register 6.
MR6 BIT DESCRIPTION
Power-Up Sleep Mode Control (MR60)After RESET is applied this control is enabled (MR60 = 0) if
both SCRESET/RTC/TR and NTSC_PAL pins are tied high.
The ADV7194 will then power up in Sleep Mode to facilitate
low power consumption before the I2C is initialized. When
this control is disabled (MR60 = 1, via the I2C) Sleep Mode con-
trol passes to Sleep Mode Control, MR27.
PPL Enable Control (MR61)The PLL control should be enabled (MR61 = 0 ) when 4×
Oversampling is enabled (MR16 = 1). It is also used to reset the
PLL when this bit is toggled.
Reserved (MR62, MR63, MR64)A Logic 0 must be written to these bits.
Field Counter (MR65, MR66, MR67)These three bits are read-only bits. The field count can be read
back over the I2C interface. In NTSC mode the field count goes
from 0–3, in PAL Mode from 0–7.
MODE REGISTER 7
MR7 (MR77–MR70)
(Address (SR4–SR0) = 07H)Mode Register 7 is an 8-bit-wide register. Figure 62 shows the
various operations under the control of Mode Register 7.
MR7 BIT DESCRIPTION
Color Control Enable (MR70)This bit is used to enable control of contrast and saturation of
color. If this bit is set (1) color controls are enabled (Contrast
Control, U-Scale, V-Scale Registers). If this bit is set (0), the color
control features are disabled.
Luma Saturation Control (MR71)When this bit is set (1), the luma signal will be clipped if it reaches
a limit that corresponds to an input luma value of 255 (after
scaling by the Contrast Control Register). This prevents the
chrominance component of the composite video signal being
clipped if the amplitude of the luma is too high. When this bit is
set (0), this control is disabled.
Hue Adjust Control (MR72)This bit is used to enable hue adjustment on the composite and
chroma output signals of the ADV7194. When this bit is set (1),
the hue of the color is adjusted by the phase offset described in
the Hue Adjust Control Register. When this bit is set (0), hue
adjustment is disabled.
Brightness Enable Control (MR73)This bit is used to enable brightness control on the ADV7194.
The actual brightness level is programmed in the Brightness
Control Register. This value or set-up level is added to the scaled
Y data. When this bit is set (1), brightness control is enabled.
When this bit is set (0), brightness control is disabled.
Sharpness Filter Enable (MR74)This bit is used to enable the sharpness control of the luminance
signal on the ADV7194 (Luma Filter Select has to be set to
Extended, MR04–MR02 = 100). The various responses of the
filter are determined by the Sharpness Control Register. When
this bit is set 1, the luma response is altered by the amount
described in the Sharpness Control Register. When this bit is
set 0, the sharpness control is disabled. See Internal Filter
Response section.
CSO_HSO Output Control (MR75)This bit is used to determine whether HSO or CSO TTL output
signal is output at the CSO_HSO pin. If this bit is set 1, then
the CSO TTL signal is output. If this bit is set 0, the HSO TTL
signal is output.
TTX Input/ CLAMP–VSO Output Control (MR76)This bit controls whether Pin 62 is configured as an output or as
an input pin. A 1 selects Pin 62 to be an output for CLAMP or
VSO functionality. A 0 selects this pin as a TTX input pin.
CLAMP/VSO Select Control (MR77)This bit is used to select the functionality of Pin 62. Setting this
bit to 1 selects CLAMP as the output signal. A 0 selects VSO
as the output signal. Since this pin is also shared with the TTX
functionality, TTX Input/ CLAMP–VSO Output has to be set
accordingly (MR76).
Figure 61.Mode Register 6, MR6
MODE REGISTER 8
MR8 (MR87–MR80)
(Address (SR4–SR0) = 08H)Mode Register 8 is an 8-bit-wide register. Figure 63 shows the
various operations under the control of Mode Register 8.
MR8 BIT DESCRIPTION
Progressive Scan Control (MR80)This control enables the progressive scan inputs, Y0–Y9, Cr0–Cr9,
Cb0–Cb9. To enable this control MR80 has to be set to 1. It
is assumed that the incoming Y data contains all necessary sync
information.
Note: Simultaneous progressive scan input and 16-bit pixel input
is not possible.
10-Bit Pixel Port (MR84)This bit selects 8-bit or 10-bit input format. In 8-bit mode, the
LSB of the pixel data is input on Pin 3, in 10-bit mode, on Pin 1.
Double Buffer Control (MR82)Double Buffering can be enabled or disabled on the Contrast
Control Register, U Scale Register, V Scale Register, Hue Adjust
Control, Closed Captioning Register, Brightness Control Regis-
ter, Gamma Curve Select Bit. Double Buffering is not available in
Mastering Timing mode.
20-, 16-Bit Pixel Port (MR83)This bit controls whether the ADV7194 is operated in 16-bit
mode (10-Bit Pixel Port disabled, MR 84 = 0, MR83 = 1) or
20-bit mode (10-Bit Pixel Port enabled, MR84 =1, MR83 = 1).
10-Bit Pixel Port (MR84)This bit selects 8-bit or 10-bit format. In 8-bit mode, the LSB of
the pixel data is input on Pin 3, in 10-bit mode on Pin 1.
DNR Enable Control (MR85)To enable the DNR process this bit has to be set to 1. If this bit
is set to 0, the DNR processing is bypassed. For further infor-
mation on DNR controls see the DNR Bit Description section.
Gamma Enable Control (MR86)To enable the programmable gamma correction this bit has
to be set to enabled (MR86 = 1). For further information on
Gamma Correction controls see the Gamma Correction Regis-
ters section.
Gamma Curve Select Control (MR87)This bit selects which of the two programmable gamma curves is
to be used. When setting MR87 to 0, the gamma correction curve
MODE REGISTER 9
MR9 (MR97–MR90)
(Address (SR4–SR0) = 09H)Mode Register 9 is an 8-bit-wide register. Figure 65 shows the
various operations under the control of Mode Register 9.
MR9 BIT DESCRIPTION
Undershoot Limiter (MR90–MR91)This control ensures that no luma video data will go below a
programmable level. This prevents any synchronization problems
due to luma signals going below the blanking level. Available
limit levels are –1.5 IRE, –6 IRE, –11 IRE. Note that this facil-
ity is only available in 4× Oversampling mode (MR16 = 1). When
the device is operated in 2× Oversampling mode (MR16 = 0),
or RGB output without RGB sync is selected, the minimum
luma level is set in Timing Register 0, TR06 (Min Luma Control).
Black Burst Y-DAC (MR92)It is possible to output a Black Burst signal from the DAC which is
selected to be the Luma DAC (MR22, MR21, MR20). When
this control is set to enabled, MR92 is set to 1. This signal can be
useful for locking two video sources together using professional
video equipment. See also the Black Burst Output section.
Black Burst Luma-DAC (MR93)It is possible to output a Black Burst signal from the DAC which
is selected to be the Y-DAC (MR22, MR21, MR20). When this
control is set to enabled, MR93 set to 1. This signal can be
useful for locking two video sources together using professional
video equipment. See also the Black Burst Output section.
Figure 64.Black Burst Signals for PAL and NTSC Standards
Chroma Delay Control (MR95–MR97)The Chroma signal can be delayed by up to eight clock cycles
Figure 63.Mode Register 8, MR8
