ADV7191KST ,Video Encoder with Six 10-Bit DACs and Video Encoder with Six DAC OutputsFEATURES: FUNCTIONAL DESCRIPTION . . . . . . . . . 17APPENDIX 2BRIGHTNESS DETECT . . . . . . . . . ..
ADV7192KST ,Video Encoder with Six 10-Bit DACs, 54 MHz Oversampling and Progressive Scan InputsFEATURES: FUNCTIONAL DESCRIPTION . . . . . . . . . 17BRIGHTNESS DETECT REGISTER . . . . . . . . . . ..
ADV7192KSTZ ,Video Encoder with Six 10-bit DACs, 54 MHz Oversampling and ProgressiveFEATURES: FUNCTIONAL DESCRIPTION . . . . . . . . . 17DNR BIT DESCRIPTIONS . . . . . . . . . . . . . ..
ADV7194KST ,Professional Extended-10⑩ Video Encoder with 54 MHz OversamplingFEATURES: FUNCTIONAL DESCRIPTION . . . . . . . . . 17BRIGHTNESS DETECT REGISTER . . . . . . . . . . ..
ADV7194KSTZ ,Professional Extended-10™ Video Encoder with 54 MHz OversamplingFEATURES: FUNCTIONAL DESCRIPTION . . . . . . . . . 17BRIGHTNESS DETECT REGISTER . . . . . . . . . . ..
ADV7196AKS ,Multiformat Progressive Scan/HDTV Encoder with Three 11-Bit DACs, 10-Bit Data Input, and MacrovisionGENERAL DESCRIPTIONAnticopy algorithm in 525p mode.The ADV7196A is a triple high-speed, digital-to- ..
AM27C64-90DC , 64 Kilobit (8 K x 8-Bit) CMOS EPROM
AM27C64-90DE , 64 Kilobit (8 K x 8-Bit) CMOS EPROM
AM27C64-90DI , 64 Kilobit (8 K x 8-Bit) CMOS EPROM
AM27H010 , 1 Megabit (131,072 x 8-bit) High Speed CMOS EPROM
AM27H010-45DC , 1 Megabit (131,072 x 8-bit) High Speed CMOS EPROM
AM27H010-45DI , 1 Megabit (131,072 x 8-bit) High Speed CMOS EPROM
ADV7190KST-ADV7191KST
Video Encoder with Six 10-Bit DACs and Video Encoder with Six DAC Outputs
REV.0
Video Encoder with Six 10-Bit DACs and
Video Encoder with Six DAC Outputs
FEATURES
Six High-Quality 10-Bit Video DACs
Multistandard Video Input
Multistandard Video Output
4� Oversampling with Internal 54 MHz PLL
Programmable Video Control Includes:
Digital Noise Reduction
Gamma Correction
LUMA Delay
CHROMA Delay
Multiple Luma and Chroma Filters
Luma SSAF™ (Super Subalias Filter)
Average Brightness Detection
Field Counter
Macrovision Rev 7.1
CGMS (Copy Generation Management System)
WSS (Wide Screen Signaling)
Closed Captioning Support
Teletext Insertion Port (PAL-WST)
2-Wire Serial MPU Interface
Supply Voltage 5 V and 3.3 V Operation
64-Lead LQFP Package
SIMPLIFIED FUNCTIONAL BLOCK DIAGRAM*This device is protected by U.S. Patent Numbers 4631603, 4577216, and 4819098, and other intellectual property rights.
**Throughout the document YUV refers to digital or analog component video.
The Macrovision anticopy process is licensed for noncommercial home use only, which is its sole intended use in the device. Please contact sales office for latest available Macrovision version.
ITU-R and CCIR are used interchangeably in this document (ITU-R has replaced CCIR recommendations).
SSAF is a trademark of Analog Devices Inc.
I2C is a registered trademark of Philips Corporation.
GENERAL DESCRIPTIONThe ADV7190/ADV7191 is part of the new generation of video
encoders from Analog Devices. The device builds on the perfor-
mance of previous video encoders and provides new features such
as, Digital Noise Reduction, Gamma Correction, 4× Oversam-
pling and 54 MHz operation, Average Brightness Detection,
Chroma Delay, an additional Chroma Filter, etc.
The ADV7190/ADV7191 supports NTSC-M, NTSC-N (Japan),
PAL N, PAL M, PAL-B/D/G/H/I and PAL-60 standards. Input
standards supported include ITU-R.BT656/601 4:2:2 YCrCb
in 8- or 16-bit format.
The ADV7190/ADV7191 can output Composite Video (CVBS),
S-Video (Y/C), Component YUV** or RGB. The analog
component output is also compatible with Betacam, MII
and SMPTE/EBU N10 levels, SMPTE 170M NTSC and
ITU-R.BT 470 PAL.
For more information about the ADV7190/ADV7191’s fea-
tures refer to Detailed Description.
APPLICATIONS
DVD Playback Systems,
PC Video/Multimedia Playback Systems
ADV7190/ADV7191
CONTENTSFEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
APPLICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
SIMPLIFIED FUNCTIONAL BLOCK DIAGRAM . . . . . .1
SPECIFICATIONS
Static Performance 5 V . . . . . . . . . . . . . . . . . . . . . . . . . . .3
Static Performance 3.3 V . . . . . . . . . . . . . . . . . . . . . . . . . .4
Dynamic Specification 5 V . . . . . . . . . . . . . . . . . . . . . . . . .5
Dynamic Specification 3.3 V . . . . . . . . . . . . . . . . . . . . . . .5
Timing Characteristics 5 V . . . . . . . . . . . . . . . . . . . . . . . .6
Timing Characteristics 3.3 V . . . . . . . . . . . . . . . . . . . . . . .. 7
ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . .9
PACKAGE THERMAL PERFORMANCE . . . . . . . . . . . . .9
PIN CONFIGURATION . . . . . . . . . . . . . . . . . . . . . . . . . . .9
ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
PIN FUNCTION DESCRIPTIONS . . . . . . . . . . . . . . . . .10
DETAILED DESCRIPTION OF FEATURES . . . . . . . . .11
GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . .11
DETAILED FUNCTIONAL BLOCK DIAGRAM . . . . . .11
DATA PATH DESCRIPTION . . . . . . . . . . . . . . . . . . . . .12
INTERNAL FILTER RESPONSE.. . . . . . . . . . . . . . . . . . .13
FEATURES: FUNCTIONAL DESCRIPTION . . . . . . . . .17
BRIGHTNESS DETECT . . . . . . . . . . . . . . . . . . . . . . . . . . 17
CHROMA/LUMA DELAY . . . . . . . . . . . . . . . . . . . . . . . . 17
CLAMP OUTPUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
CSO, HSO AND VSO OUTPUTS . . . . . . . . . . . . . . . . . . . 17
COLOR BAR GENERATION . . . . . . . . . . . . . . . . . . . . . . 17
COLOR BURST SIGNAL CONTROL . . . . . . . . . . . . . . . 17
COLOR CONTROLS . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
CHROMINANCE CONTROL . . . . . . . . . . . . . . . . . . . . . 17
UNDERSHOOT LIMITER . . . . . . . . . . . . . . . . . . . . . . . . 17
DIGITAL NOISE REDUCTION . . . . . . . . . . . . . . . . . . . . 17
DOUBLE BUFFERING . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
GAMMA CORRECTION CONTROL . . . . . . . . . . . . . . . 18
NTSC PEDESTAL CONTROL . . . . . . . . . . . . . . . . . . . . . 18
POWER-ON RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
REAL-TIME CONTROL, SUBCARRIER RESET,
AND TIMING RESET . . . . . . . . . . . . . . . . . . . . . . . . . . 18
SCH PHASE MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
SLEEP MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
SQUARE PIXEL MODE . . . . . . . . . . . . . . . . . . . . . . . . . . 18
VERTICAL BLANKING DATA INSERTION AND
BLANK INPUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
YUV LEVELS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
16-BIT INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4× OVERSAMPLING AND INTERNAL PLL . . . . . . . . . 19
VIDEO TIMING DESCRIPTION . . . . . . . . . . . . . . . . . . . 19
RESET SEQUENCE . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
MPU PORT DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . 27
REGISTER ACCESSES . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
REGISTER PROGRAMMING . . . . . . . . . . . . . . . . . . . . . 28
MODE REGISTER 0–9 . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
TIMING REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
SUBCARRIER FREQUENCY AND
PHASE REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
CLOSED CAPTIONING REGISTERS . . . . . . . . . . . . . . . 36
NTSC PEDESTAL REGISTERS . . . . . . . . . . . . . . . . . . . . 37
TELETEXT CONTROL REGISTER . . . . . . . . . . . . . . . . 37
CGMS_WSS REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . 37
CONTRAST, U SCALE AND V SCALE REGISTERS . . 38
HUE ADJUST, BRIGHTNESS CONTROL,
SHARPNESS CONTROL REGISTERS . . . . . . . . . . . . 39
GAMMA CORRECTION REGISTERS . . . . . . . . . . . . . . 42
BRIGHTNESS DETECT REGISTER . . . . . . . . . . . . . . . . 43
OUTPUT CLOCK REGISTER . . . . . . . . . . . . . . . . . . . . . 43
APPENDIX 1
Board Design and Layout Considerations . . . . . . . . . . . . 44
APPENDIX 2
Closed Captioning. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
APPENDIX 3
CGMS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
APPENDIX 4
WSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
APPENDIX 5
Teletext Insertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
APPENDIX 6
Optional Output Filter. . . . . . . . . . . . . . . . . . . . . . . . . . . 50
APPENDIX 7
DAC Buffering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
APPENDIX 8
Recommended Register Values . . . . . . . . . . . . . . . . . . . . 52
APPENDIX 9
NTSC Waveforms (With Pedestal) . . . . . . . . . . . . . . . . . 56
NTSC Waveforms (Without Pedestal) . . . . . . . . . . . . . . . 57
PAL Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
UV Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Output Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Video Measurement Plots . . . . . . . . . . . . . . . . . . . . . . . .64
APPENDIX 10
Vector Plots . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . 69
ADV7190/ADV7191
5 V SPECIFICATIONS1DIGITAL OUTPUTS
VOLTAGE REFERENCE
POWER REQUIREMENTS
NOTES
1All measurements are made in 4× Oversampling Mode unless otherwise specified.
2Temperature range TMIN to TMAX: 0°C to 70°C.
3Guaranteed by characterization.
4Measurement made in 2× oversampling mode.
5IDAC is the total current required to supply all DACs including the VREF circuitry.
6All six DACs ON.
7ICCT, or the circuit current, is the continuous current required to drive the digital core without IPLL.
Specifications subject to change without notice.
(VAA = 5 V, VREF = 1.235 V, RSET1,2 = 1200 � unless otherwise noted. All specifications TMIN to TMAX2
unless otherwise noted.)
SPECIFICATIONS
ADV7190/ADV7191–SPECIFICATIONS
3.3 V SPECIFICATIONS1POWER REQUIREMENTS
NOTES
1All measurements are made in 4× Oversampling Mode unless otherwise specified and are guaranteed by characterization. In 2× Oversampling Mode, the power re-
quirement for the ADV7190/ADV7191 are typically 3.0 V.
2Temperature range TMIN to TMAX: 0°C to 70°C.
3Measurement made in 2× oversampling mode.
4IDAC is the total current required to supply all DACs including the VREF circuitry.
5All six DACs ON.
6ICCT, or the circuit current, is the continuous current required to drive the digital core without IPLL.
Specifications subject to change without notice.
(VAA = 3.3 V, VREF = 1.235 V, RSET1,2 = 1200 � unless otherwise noted. All specifications TMIN to TMAX2
unless otherwise noted.)
ADV7190/ADV7191
5 V DYNAMIC–SPECIFICATIONS1Hue Accuracy
Color Saturation Accuracy
Chroma Nonlinear Gain
NOTESAll measurements are made in 4× Oversampling Mode unless otherwise specified.Temperature range TMIN to TMAX: 0°C to 70°C.Values in parentheses apply to 2× Oversampling Mode.
Specifications subject to change without notice.
3.3 V DYNAMIC–SPECIFICATIONS1Hue Accuracy
Color Saturation Accuracy
Chroma Nonlinear Gain
NOTESAll measurements are made in 4× Oversampling Mode unless otherwise specified.Temperature range TMIN to TMAX: 0°C to 70°C.Values in parentheses apply to 2× Oversample Mode.
Specifications subject to change without notice.
(VAA = 5 V � 250 mV, VREF = 1.235 V, RSET1,2 = 1200 � unless otherwise noted. All
specifications TMIN to TMAX2 unless otherwise noted.)
(VAA = 3.3 V � 150 mV, VREF = 1.235 V, RSET1,2 = 1200 � unless otherwise noted. All
specifications TMIN to TMAX2 unless otherwise noted.)
ADV7190/ADV7191
5 V TIMING CHARACTERISTICSTELETEXT PORT
PLL
NOTESTemperature range TMIN to TMAX: 0°C to 70°C.Guaranteed by characterization.Pixel Port consists of:
Data: P15–P0 Pixel Inputs,
Control: HSYNC, VSYNC, BLANK,
Clock: CLKIN Input.Teletext Port consists of:
Digital Output: TTXRQ,
Data: TTX.
Specifications subject to change without notice.
(VAA = 5 V � 250 mV, VREF = 1.235 V, RSET1,2 = 1200 � unless otherwise noted. All specifications
TMIN to TMAX1 unless otherwise noted.)
3.3 V TIMING CHARACTERISTICSNOTESTemperature range TMIN to TMAX: 0°C to 70°C.Guaranteed by characterization.Pixel Port consists of:
Data: P15–P0 Pixel Inputs,
Control: HSYNC, VSYNC, BLANK,
Clock: CLKIN Input.Teletext Port consists of:
Digital Output: TTXRQ,
Data: TTX.
Specifications subject to change without notice.
(VAA = 3.3 V � 150 mV, VREF = 1.235 V, RSET1,2 = 1200 � unless otherwise noted. All
specifications TMIN to TMAX1 unless otherwise noted2.)
ADV7190/ADV7191Figure 1.MPU Port Timing Diagram
Figure 2.Pixel and Control Data Timing Diagram
Figure 3.Teletext Timing Diagram
ABSOLUTE MAXIMUM RATINGS1VAA to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 V
Voltage on Any Digital Input Pin . . . . GND – 0.5 V to VAA + 0.5 V
Storage Temperature (TS) . . . . . . . . . . . . . .–65°C to +150°C
Junction Temperature (TJ) . . . . . . . . . . . . . . . . . . . . . 150°C
Body Temperature (Soldering, 10 secs) . . . . . . . . . . . . 220°C
Analog Outputs to GND2 . . . . . . . . . . . .GND – 0.5 to VAA
NOTESStresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute maximum rating condi-
tions for extended periods may affect device reliability.Analog Output Short Circuit to any Power Supply or Common can be of an
indefinite duration.
PACKAGE THERMAL PERFORMANCEThe 64-lead package is used for this device. The junction-to-
ambient (θJA) thermal resistance in still air on a four-layer PCB
is 38°C/W.
To reduce power consumption when using this part the user
can run the part on a 3.3 V supply, turn off any unused DACs.
The user must at all times stay below the maximum junction
temperature of 110°C. The following equation shows how to
calculate this junction temperature:
Junction Temperature = (VAA × (IDAC + ICCT)) × θJA + 70°C TAMB
IDAC = 10 mA + (sum of the average currents consumed by
each powered-on DAC)
Average current consumed by each powered-on DAC =
(VREF × K )/RSET
VREF = 1.235 V
K = 4.2146
ORDERING GUIDE
CAUTIONESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection. Although
PIN CONFIGURATION
NC = NO CONNECT
AGNDNCNCNCNCNCTTXAGNDVPAL
NTSC
VSO
/CLAMP
CSO_HSORESET
P10
P11
P12
P13
P14
P15
RSET1
VREF
COMP 1
DAC A
DAC B
VAA
AGND
DAC C
DAC D
AGND
VAA
DAC E
DAC F
COMP 2
RSET2
AGND
AGND
HSYNCVSYNCBLANK
ALSB
TTXREQ
AGND
AGND
SCL
SDA
SCRESET/RTC/TR
CLKIN
CLKOUT
ADV7190/ADV7191
PIN FUNCTION DESCRIPTIONS
DAC A
DAC B
DAC C
VREF
RSET2
COMP2
DAC D
DAC F
DAC E
RSET1
ALSBSDASCLPAL_NTSCVSO/CLAMPCSO_HSO
HSYNC
VSYNC
BLANK
RESET
TTX
TTXRQ
P15
CLKIN
DETAILED DESCRIPTION OF FEATURES
Clocking:
Single 27 MHz Clock Required to Run the Device
4� Oversampling with Internal 54 MHz PLL
Square Pixel Operation
Advanced Power Management
Programmable Video Control Features:
Digital Noise Reduction
Pedestal level
Hue, Brightness, Contrast and Saturation
Clamping Output Signal
VBI (Vertical Blanking Interval)
Subcarrier Frequency and Phase
LUMA Delay
CHROMA Delay
Gamma Correction
Luma and Chroma Filters
Luma SSAF (Super Subalias Filter)
Average Brightness Detection
Field Counter
Interlaced/Noninterlaced Operation
Complete On-Chip Video Timing Generator
Programmable Multimode Master/Slave Operation
CGMS (Copy Generation Management System)
WSS (Wide Screen Signaling)
Macrovision 7.1 Rev
Closed Captioning Support
Teletext Insertion Port (PAL-WST)
2-Wire Serial MPU Interface2C Registers Synchronized to VSYNC
GENERAL DESCRIPTIONThe ADV7190/ADV7191 is an integrated Digital Video Encoder
that converts digital CCIR-601/656 4:2:2 8-bit or 16-bit com-
ponent video data into a standard analog baseband television
signal compatible with worldwide standards.
Six DACs are available on the ADV7190/ADV7191, each of which
is capable of providing 4.33mA of current. In addition to the
composite output signal there is the facility to output S-Video
(Y/C Video), RGB Video and YUV Video. All YUV formats
(Betacam, MII and (SMPTE/EBU N10) are supported.
Digital Noise Reduction allows improved picture quality in remov-
ing low amplitude, high frequency noise. The block diagram below
shows the DNR functionality in the two modes available.
Figure 5.Block Diagram for DNR Mode and DNR Sharpness
Mode
ADV7190/ADV7191Programmable gamma correction is also available. Figure 6 shows
the response of different gamma values to a ramp signal.
GAMMA
CORRECTED AMPLITUDE50100150200250
LOCATIONFigure 6.Signal Input (Ramp) and Selectable Gamma
Output Curves
The on-board SSAF (Super Subalias Filter) with extended
luminance frequency response and sharp stopband attenuation
enables studio quality video playback on modern TVs, giving
optimal horizontal line resolution. An additional sharpness
control feature allows high-frequency enhancement on the lumi-
nance signal.
The device is driven by a 27MHz clock. Data can be output atMHz or 54MHz (on-board PLL) when 4� oversampling is
enabled. Also, the output filter requirements in 4� oversampling
and 2� oversampling differ, as can be seen in Figure 7.
Figure 7.Output Filter Requirements in 4×Oversampling
Mode
Figure 8.PLL and 4× Oversampling Block Diagram
The ADV7190/ADV7191 also supports both PAL and NTSC
An advanced power management circuit enables optimal control
of power consumption in normal operating modes or sleep modes.
The Output Video Frames are synchronized with the incoming
data Timing Reference Codes. Optionally, the Encoder accepts
(and can generate) HSYNC, VSYNC, and FIELD timing signals.
These timing signals can be adjusted to change pulsewidth and
position while the part is in master mode.
HSO/CSO and VSO TTL outputs are also available and are timed
to the analog output video.
A separate teletext port enables the user to directly input teletext
data during the vertical blanking interval.
The ADV7190/ADV7191 also incorporates WSS and CGMS-A
data control generation and Macrovision Rev 7.1.
The ADV7190/ADV7191 modes are set up over a 2-wire
serial bidirectional port (I2C-compatible) with two slave
addresses, and the device is register-compatible with the
ADV7172/ADV7173.
The ADV7190ADV7191 is packaged in a 64-lead LQFP
package.
DATA PATH DESCRIPTIONFor PAL B, D, G, H, I, M, N, and NTSC M, N modes, YCrCb
4:2:2 Data is input via the CCIR-656/601-compatible Pixel
Port at a 27 MHz data rate. The pixel data is demultiplexed to
form three data paths. Y typically has a range of 16 to 235, Cr
and Cb typically have a range of 128+/–112; however, it is
possible to input data from 1 to 254 on both Y, Cb, and Cr.
The ADV7190/ADV7191 supports PAL (B, D, G, H, I, N, M)
and NTSC M, N (with and without Pedestal) and PAL60 stan-
dards. Digital Noise Reduction can be applied to the Y signal.
Programmable gamma correction can also be applied to the Y
signal if required.
The Y data can be manipulated for contrast control and a set-up
level can be added for brightness control. The Cr, Cb data can
be scaled to achieve color saturation control. All settings become
effective at the start of the next field when double buffering is
enabled.
The appropriate sync, blank, and burst levels are added to the
YCrCb data. Macrovision antitaping, (ADV7190 only) Closed-
Captioning, and Teletext levels are also added to Y and the
resultant data is interpolated to 54 MHz when 4× Oversampling
is enabled. The interpolated data is filtered and scaled by three
digital FIR filters.
The U and V signals are modulated by the appropriate Subcarrier
Sine/Cosine waveforms and a phase offset may be added onto
the color subcarrier during active video to allow hue adjustment.
The resulting U and V signals are added together to make up
the Chrominance Signal. The Luma (Y) signal can be delayed
by up to six clock cycles (at 27 MHz) and the Chroma signal
can be delayed by up to eight clock cycles (at 27 MHz). The
Luma and Chroma Signals are added together to make up the
Composite Video Signal. All timing signals are controlled.
The YCrCb data is also used to generate RGB data with appropri-
ate sync and blank levels. The YUV levels are scaled to output
Table I.Luminance Internal Filter Specifications (4� Oversampling)Low-Pass (NTSC)
Low-Pass (PAL)
Notch (NTSC)
Notch (PAL)
Extended (SSAF)
CIF
NOTESPassband ripple is defined to be fluctuations from the 0 dB response in the passband, measured in (dB). The passband is defined to have 0-fc frequency limits for a
low-pass filter, 0–f1 and f2–infinity for a notch filter, where fc, f1, f2 are the –3 dB points.3 dB bandwidth refers to the –3 dB cutoff frequency.Stopband cutoff refers to the frequency at the attenuation point referred to under Note 4.Stopband Attenuation refers to the attenuation point (dB) at the frequency referred to under Note 3.
Table II.Chrominance Internal Filter Specifications (4� Oversampling)1.3 MHz Low-Pass
0.65 MHz Low-Pass
1.0 MHz Low-Pass
2.0 MHz Low-Pass
3.0 MHz Low-Pass
CIF
NOTESPassband ripple is defined to be fluctuations from the 0 dB response in the passband, measured in (dB). The passband is defined to have 0-fc frequency limits for a
low-pass filter, 0–f1 and f2–infinity for a notch filter, where fc, f1, f2 are the –3 dB points.3 dB bandwidth refers to the –3 dB cutoff frequency.Stopband cutoff refers to the frequency at the attenuation point referred to under Note 4.Stopband Attenuation refers to the attenuation point (dB) at the frequency referred to under Note 3.
Each DAC can be individually powered off if not required. A
complete description of DAC output configurations is given in
the MR2 Bit Description section.
Video output levels are illustrated in Appendix 9.
INTERNAL FILTER RESPONSEThe Y Filter supports several different frequency responses
including two low-pass responses, two notch responses, an
Extended (SSAF) response with or without gain boost/attenuation,
a CIF response and a QCIF response. The UV Filter supports
several different frequency responses including five low-pass
responses, a CIF response and a QCIF response, as can be seen on
the following pages.
In Extended Mode there is the option of twelve responses in
the range from –4 dB to +4 dB. The desired response can be
chosen by the user by programming the correct value via the2C. The variation of frequency responses can be seen on the
following pages. For more detailed plots refer to AN-562
Analog Devices’ Application note.
ADV7190/ADV7191
FREQUENCY – MHz
MAGNITUDE
dBFigure 9.NTSC Low-Pass Luma Filter
FREQUENCY – MHz
MAGNITUDE
dBFigure 10.PAL Low-Pass Luma Filter
MAGNITUDE
dB
FREQUENCY – MHzFigure 11.Extended Mode (SSAF) Luma Filter
MAGNITUDE
dB
FREQUENCY – MHzFigure 12.NTSC Notch Luma Filter
MAGNITUDE
dB
FREQUENCY – MHzFigure 13.PAL Notch Luma Filter
6735–1
MAGNITUDE
dB
FREQUENCY – MHzFigure 14.Extended SSAF and Programmable Gain,
Showing Range 0 dB/+4 dB Range
6735–5MAGNITUDE
dB
FREQUENCY – MHzFigure 15.Extended SSAF and Programmable
Attenuation, Showing Range 0 dB/–4 dB
6735–12
MAGNITUDE
dB
FREQUENCY – MHz
–10Figure 16.Extended SSAF and Programmable
Attenuation, Showing Range +4 dB/–12 dB
MAGNITUDE
dB
FREQUENCY – MHzFigure 17.Luma CIF Filter
MAGNITUDE
dB
FREQUENCY – MHzFigure 18.QCIF Filter
MAGNITUDE
dB
FREQUENCY – MHzFigure 19.Chroma 0.65 MHz Low-Pass Filter
MAGNITUDE
dB
FREQUENCY – MHzFigure 20.Chroma 1.0 MHz Low-Pass Filter
ADV7190/ADV7191
MAGNITUDE
dB
FREQUENCY – MHzFigure 21.Chroma 1.3 MHz Low-Pass Filter
Figure 22.Chroma 2 MHz Low-Pass Filter
MAGNITUDE
dB
FREQUENCY – MHzFigure 23.Chroma 3 MHz Low-Pass Filter
MAGNITUDE
dB
FREQUENCY – MHzFigure 24.Chroma CIF Filter
MAGNITUDE
dB
FREQUENCY – MHzFigure 25.Chroma QCIF Filter
FEATURES: FUNCTIONAL DESCRIPTION
BRIGHTNESS DETECTThis feature is used to monitor the average brightness of the
incoming Y signal on a field-by-field basis. The information is
read from the I2C and based, on this information, the color
saturation, contrast and brightness controls can be adjusted (for
example to compensate for very dark pictures). (Brightness Detect
Register.)
CHROMA/LUMA DELAYThe luminance data can be delayed by maximum of six clock
cycles. Additionally the Chroma can be delayed by a maximum
of eight clock cycles (one clock cycle at 27 MHz). (Timing
Register 0 and Mode Register 9.)
Figure 26.Chroma Delay Figure 27.Luma Delay
CLAMP OUTPUTThe ADV7190/ADV7191 has a programmable clamp TTL
output signal. This clamp signal is programmable to the front
and back porch. The clamp signal can be varied by one to
three clock cycles in a positive and negative direction from the
default position. (Mode Register 5, Mode Register 7.)
Figure 28.Clamp Output Timing
CSO, HSO AND VSO OUTPUTSThe ADV7190/ADV7191 supports three output timing sig-
nals, CSO (Composite Sync Signal), HSO (Horizontal Sync
Signal) and VSO (Vertical Sync Signal). These output TTL sig-
nals are aligned with the analog video outputs. See Figure 29 for
an example of these waveforms. (Mode Register 7.)
Figure 29.CSO, HSO, VSO Timing Diagram
COLOR BAR GENERATIONThe ADV7190/ADV7191 can be configured to generate 100/
7.5/75/7.5 color bars for NTSC or 100/0/75/0 color bars for
PAL. (Mode Register 4.)
COLOR BURST SIGNAL CONTROLThe burst information can be switched on and off the composite
and chroma video output. (Mode Register 4.)
COLOR CONTROLSThe ADV7190/ADV7191 allows the user to control the brightness,
contrast, hue, and saturation of the color. The control regis-
ters may be double-buffered, meaning that any modification to
the registers will be done outside the active video region and,
therefore, changes made will not be visible during active video.
Contrast ControlContrast adjustment is achieved by scaling the Y input data by a
factor programmed by the user. This factor allows the data to be
scaled between 0% and 150%. (Contrast Control Register.)
Brightness ControlThe brightness is controlled by adding a programmable setup level
onto the scaled Y data.
For NTSC with pedestal, the setup can vary from 0 IRE to
22.5 IRE. For NTSC without pedestal and PAL, the setup can
vary from –7.5 IRE to +15 IRE. (Brightness Control Register.)
Color SaturationColor adjustment is achieved by scaling the Cr and Cb input
data by a factor programmed by the user. This factor allows the
data to be scaled between 0% and 200%. (U Scale Register and
V Scale Register.)
Hue Adjust ControlThe hue adjustment is achieved on the composite and chroma
outputs by adding a phase offset onto the color subcarrier in the
active video but leaving the color burst unmodified, i.e., only
the phase between the video and the colorburst is modified and
hence the hue is shifted. The ADV7190/ADV7191 provides a
range of ±22° in increments of 0.17578125°. (Hue Adjust
Register.)
CHROMINANCE CONTROLThe color information can be switched on and off the com-
posite, chroma and color component video outputs. (Mode
Register 4.)
UNDERSHOOT LIMITERA limiter is placed after the digital filters. This prevents any
synchronization problems for TVs. The level of undershoot is
programmable between –1.5 IRE, –6 IRE, –11 IRE when operat-
ing in 4× Oversampling. In 2× Oversampling mode the limits are
–7.5 IRE and 0 IRE. (Mode Register 9 and Timing Register 0.)
DIGITAL NOISE REDUCTIONDNR is applied to the Y data only. A filter block selects the
high frequency, low amplitude components of the incoming
signal (DNR Input Select). The absolute value of the filter output
is compared to a programmable threshold value (DNR Thresh-
old Control).
ADV7190/ADV7191In DNR Mode, if the absolute value of the filter output is smaller
than the threshold, it is assumed to be noise. A programmable
amount (Coring Gain Control) of this noise signal will be sub-
tracted from the original signal.
In DNR Sharpness Mode, if the absolute value of the filter output
is less than the programmed threshold, it is assumed to be noise,
as before. Otherwise, if the level exceeds the threshold, now
being identified as a valid signal, a fraction of the signal (Coring
Gain Control) will be added to the original signal in order to boost
high frequency components and to sharpen the video image.
In MPEG systems it is common to process the video information
in blocks of 8 × 8 pixels for MPEG2 systems, or 16 × 16 pixels for
MPEG1 systems (Block Size Control). DNR can be applied to
the resulting block transition areas that are known to contain
noise. Generally the block transition area contains two pixels.
It is possible to define this area to contain four pixels (Border
Area Control).
It is also possible to compensate for variable block positioning or
differences in YCrCb pixel timing with the use of the (Block Offset
Control). See Figure 82 for further information (Mode Register
8, DNR Registers 0–2.)
DOUBLE BUFFERINGDouble buffering can be enabled or disabled on the following
registers: Closed Captioning Registers, Brightness Control,
V Scale, U Scale, Contrast Control, Hue Adjust, the Gamma
Curve Select bit, and Macrovision Registers. These registers are
updated once per field on the falling edge of the VSYNC signal.
Double buffering improves the overall performance of the
ADV7190/ADV7191, since modifications to register settings
will not be made during active video, but take effect on the
start of the active video. (Mode Register 8.)
GAMMA CORRECTION CONTROLGamma correction may be performed on the luma data. The
user has the choice to use either of two different gamma curves,
A or B. At any one time one of these curves is operational if
gamma correction is enabled. Gamma correction allows the
mapping of the luma data to a user-defined function. (See Gamma
Correction Registers 0–13 section.) (Mode Register 8, Gamma
Correction Registers 0–13.)
NTSC PEDESTAL CONTROLIn NTSC mode it is possible to have the pedestal signal gener-
ated on the output video signal. (Mode Register 2.)
POWER-ON RESETAfter power-up, it is necessary to execute a RESET operation. A
reset occurs on the falling edge of a high-to-low transition on the
RESET pin. This initializes the pixel port such that the data on
the pixel inputs pins is ignored. See Appendix 8 for the register
settings after RESET is applied.
REAL-TIME CONTROL, SUBCARRIER RESET, AND
TIMING RESETTogether with the SCRESET/RTC/TR pin and of Mode
Register 4 (Genlock Control), the ADV7190/ADV7191 can
be used in (a) Timing Reset Mode, (b) Subcarrier Phase
(a)A TIMING RESET is achieved in holding this pin high. In
this state the horizontal and vertical counters will remain reset.
On releasing this pin (set to low), the internal counters will
commence counting again. The minimum time the pin has
to be held high is 37 ns (1 clock cycle at 27 MHz), otherwise
the reset signal might not be recognized.
(b)The SUBCARRIER PHASE will reset to that of Field 0 at
the start of the following field when a low-to-high transition
occurs on this input pin.
(c)In RTC MODE, the ADV7190/ADV7191 can be used to
lock to an external video source.
The real-time control mode allows the ADV7190/ADV7191
to automatically alter the subcarrier frequency to compen-
sate for line length variations. When the part is connected to
a device that outputs a digital datastream in the RTC format
such as an ADV7185 video decoder (see Figure 32), the part
will automatically change to the compensated subcarrier
frequency on a line-by-line basis. This digital datastream is
67 bits wide and the subcarrier is contained in Bits 0 to 21.
Each bit is two clock cycles long. 00Hex should be written
into all four Subcarrier Frequency registers when using this
mode. (Mode Register 4.)
SCH PHASE MODEThe SCH phase is configured in default mode to reset every
four (NTSC) or eight (PAL) fields to avoid an accumulation of
SCH phase error over time. In an ideal system, zero SCH phase
error would be maintained forever, but in reality, this is impos-
sible to achieve due to clock frequency variations. This effect is
reduced by the use of a 32-bit DDS, which generates this SCH.
Resetting the SCH phase every four or eight fields avoids the
accumulation of SCH phase error, and results in very minor SCH
phase jumps at the start of the four or eight field sequence.
Automatically resetting the SCH phase should not be done if
the video source does not have stable timing or the ADV7190/
ADV7191 is configured in RTC mode. Under these conditions
(unstable video) the Subcarrier Phase Reset should be en-
abled but no reset applied. In this configuration the SCH
Phase will never be reset; this means that the output video will
now track the unstable input video.
The Subcarrier Phase Reset, when applied, will reset the SCH
phase to Field 0 at the start of the next field (e.g., Subcarrier
Phase Reset applied in Field 5 (PAL) on the start of the next
field SCH phase will be reset to Field 0). (Mode Register 4.)
SLEEP MODEIf, after RESET, the SCRESET/RTC/TR and NTSC_PAL pins
are both set high, the ADV7190/ADV7191 will power-up in
Sleep Mode to facilitate low power consumption before all
registers have been initialized. If Power-Up in Sleep Mode is
disabled, Sleep Mode control passes to the Sleep Mode control
in Mode Register 2 (i.e., control via I2C). (Mode Register 2
and Mode Register 6.)
SQUARE PIXEL MODEThe ADV7190/ADV7191 can be used to operate in square pixel
VERTICAL BLANKING DATA INSERTION AND BLANK
INPUTIt is possible to allow encoding of incoming YCbCr data on
those lines of VBI that do not have line sync or pre-/post-
equalization pulses (see Figures 34 to 45). This mode of operation
is called Partial Blanking. It allows the insertion of any VBI
data (Opened VBI) into the encoded output waveform. This data
is present in digitized incoming YCbCr data stream (e.g., WSS
data, CGMS, VPS etc.). Alternatively, the entire VBI may be
blanked (no VBI data inserted) on these lines. VBI is available
in all timing modes.
The complete VBI is comprised of the following lines:
525/60 systems, Lines 525 to 21 for field one and Lines 262 to
284 for field two.
625/50 systems, Line 624 to Line 22 and Lines 311 to 335.
The Opened VBI consists of:
525/60 systems, Lines 10 to 21 for field one and second half of
Lines 273 to 284 for field two.
625/50 systems, Lines 7 to 22 and Lines 319 to 335. (Mode
Register 3.)
It is possible to allow control over the BLANK signal using
Timing Register 0. When the BLANK input is enabled (TR03 =
0 and input pin tied low), the BLANK input can be used to
input externally generated blank signals in Slave Mode 1, 2, or 3.
When the BLANK input is disabled (TR03 = 1 and input pin
tied low or tied high), the BLANK input is not used and the
ADV7190/ADV7191 automatically blanks all normally blank
lines as per CCIR-624. (Timing Register 0.)
YUV LEVELSThis functionality allows the ADV7190/ADV7191 to output
SMPTE levels or Betacam levels on the Y output when config-
ured in PAL or NTSC mode.
SyncVideoBetacam286 mV714 mV
SMPTE300 mV700 mV
MII300 mV700 mV
As the data path is branched at the output of the filters the luma
signal relating to the CVBS or S-Video Y/C output is unaltered.
It is only the Y output of the YCrCb outputs that is scaled.
This control allows color component levels to have a peak-peak
amplitude of 700 mV, 1000 mV or the default values of 934 mV
in NTSC and 700 mV in PAL. (Mode Register 5.)
16-BIT INTERFACEIt is possible to input data in 16-bit format. In this case, the
interface only operates if the data is accompanied by separate
HSYNC/VSYNC/BLANK signals. Sixteen-bit mode is not avail-
able in Slave Mode 0 since EAV/SAV timing codes are used.
(Mode Register 8.)
4� OVERSAMPLING AND INTERNAL PLLIt is possible to operate all six DACs at 27 MHz (2× Oversam-
pling) or 54 MHz (4× Oversampling).
The ADV7190/ADV7191 is supplied with a 27 MHz clock synced
with the incoming data. Two options are available: to run the
device throughout at 27 MHz or to enable the PLL. In the latter
case, even if the incoming data runs at 27 MHz, 4× Oversam-
pling and the internal PLL will output the data at 54 MHz.
NOTE
In 4× Oversampling Mode the requirements for the optional
output filters are different from those in 2× Oversampling. (Mode
Register 1, Mode Register 6.) See Appendix 6 for further details.
Figure 30.PLL and 4× Oversampling Block Diagram
VIDEO TIMING DESCRIPTIONThe ADV7190/ADV7191 is intended to interface to off-the-
shelf MPEG1 and MPEG2 Decoders. As a consequence, the
ADV7190/ADV7191 accepts 4:2:2 YCrCb Pixel Data via a
CCIR-656 Pixel Port and has several Video Timing Modes of
operation that allow it to be configured as either System Master
Video Timing Generator or a Slave to the System Video Timing
Generator. The ADV7190/ADV7191 generates all of the required
horizontal and vertical timing periods and levels for the analog
video outputs.
The ADV7190/ADV7191 calculates the width and placement of
analog sync pulses, blanking levels, and color burst envelopes.
Color bursts are disabled on appropriate lines and serration and
equalization pulses are inserted where required.
In addition, the ADV7190/ADV7191 supports a PAL or NTSC
square pixel operation. The part requires an input pixel clock of
24.5454 MHz for NTSC square pixel operation and an input
pixel clock of 29.5 MHz for PAL square pixel operation. The
internal horizontal line counters place the various video waveform
sections in the correct location for the new clock frequencies.
The ADV7190/ADV7191 has four distinct Master and four
distinct Slave timing configurations. Timing Control is estab-
lished with the bidirectional HSYNC, BLANK, and VSYNC
pins. Timing Register 1 can also be used to vary the timing
pulsewidths and where they occur in relation to each other.
ADV7190/ADV7191
RESET SEQUENCEWhen RESET becomes active the ADV7190/ADV7191 reverts to
the default output configuration (see Appendix 8 for register
settings). The ADV7190/ADV7191 internal timing is under the
control of the logic level on the NTSC_PAL pin.
When RESET is released Y, Cr, Cb values corresponding to a
black screen are input to the ADV7190/ADV7191. Output
timing signals are still suppressed at this stage. DACs A, B, C
are switched off and DACs D, E, F are switched on.
When the user requires valid data, Pixel Data Valid Control is
enabled (MR26 = 1) to allow the valid pixel data to pass through
Figure 31.RESET Sequence Timing Diagram
the encoder. Digital output timing signals become active and the
encoder timing is now under the control of the Timing Registers.
If at this stage, the user wishes to select a different video standard
to that on the NTSC_PAL pin, Standard I2C Control should be
enabled (MR25 = 1) and the video standard required is selected
by programming Mode Register 0 (Output Video Standard
Selection). Figure 31 illustrates the RESET sequence timing.
Figure 32.RTC Timing and Connections
Mode 0 (CCIR–656):Slave Option(Timing Register 0 TR0 = X X X X X 0 0 0)
The ADV7190/ADV7191 is controlled by the SAV (Start Active Video) and EAV (End Active Video) Time Codes in the Pixel
Data. All timing information is transmitted using a 4-byte synchronization pattern. A synchronization pattern is sent immediately
before and after each line during active picture and retrace. Mode 0 is illustrated in Figure 33. The HSYNC, VSYNC and
BLANK pins (if not used) should be tied high during this mode.
Figure 33.Timing Mode 0, Slave Mode
ADV7190/ADV7191
Mode 0 (CCIR–656):Master Option(Timing Register 0 TR0 = X X X X X 0 0 1)
The ADV7190/ADV7191 generates H, V, and F signals required for the SAV and EAV Time Codes in the CCIR656 standard. The H bit
is output on the HSYNC pin, the V bit is output on the BLANK pin and the F bit is output on the VSYNC pin. Mode 0 is illustrated
in Figure 34 (NTSC) and Figure 35 (PAL). The H, V, and F transitions relative to the video waveform are illustrated in Figure 36.
Figure 34.Timing Mode 0, NTSC Master Mode
Figure 35.Timing Mode 0, PAL Master Mode
Figure 36.Timing Mode 0 Data Transitions, Master Mode
Mode 1:Slave Option HSYNC, BLANK, FIELD(Timing Register 0 TR0 = X X X X X 0 1 0)
In this mode the ADV7190/ADV7191 accepts Horizontal SYNC and Odd/ Even FIELD signals. A transition of the FIELD
input when HSYNC is low indicates a new frame, i.e., Vertical Retrace. The BLANK signal is optional. When the BLANK
input is disabled the ADV7190/ADV7191 automatically blanks all normally blank lines as per CCIR-624. Mode 1 is illustrated
in Figure 37 (NTSC) and Figure 38 (PAL).
Figure 37.Timing Mode 1, NTSC
ADV7190/ADV7191
Mode 1:Master Option HSYNC, BLANK, FIELD(Timing Register 0 TR0 = X X X X X 0 1 1)
In this mode the ADV7190/ADV7191 can generate Horizontal SYNC and Odd/Even FIELD signals. A transition of the FIELD
input when HSYNC is low indicates a new frame, i.e., Vertical Retrace. The BLANK signal is optional. When the BLANK input is
disabled the ADV7190/ADV7191 automatically blanks all normally blank lines as per CCIR-624. Pixel data is latched on the
rising clock edge following the timing signal transitions. Mode 1 is illustrated in Figure 37 (NTSC) and Figure 38 (PAL). Figure 39
illustrates the HSYNC, BLANK and FIELD for an odd or even field transition relative to the pixel data.
Figure 39.Timing Mode 1, Odd/Even Field Transitions Master/Slave
Mode 2:Slave Option HSYNC, VSYNC, BLANK(Timing Register 0 TR0 = X X X X X 1 0 0)
In this mode the ADV7190/ADV7191 accepts Horizontal and Vertical SYNC signals. A coincident low transition of both HSYNC
and VSYNC inputs indicates the start of an Odd Field. A VSYNC low transition when HSYNC is high indicates the start of an
Even Field. The BLANK signal is optional. When the BLANK input is disabled, the ADV7190/ADV7191 automatically blanks all
normally blank lines as per CCIR-624. Mode 2 is illustrated in Figure 40 (NTSC) and Figure 41 (PAL).
Figure 40.Timing Mode 2, NTSC
Figure 41.Timing Mode 2, PAL
Mode 2:Master Option HSYNC, VSYNC, BLANK(Timing Register 0 TR0 = X X X X X 1 0 1)
In this mode the ADV7190/ADV7191 can generate Horizontal and Vertical SYNC signals. A coincident low transition of both
HSYNC and VSYNC inputs indicates the start of an Odd Field. A VSYNC low transition when HSYNC is high indicates the
start of an Even Field. The BLANK signal is optional. When the BLANK input is disabled the ADV7190/ADV7191 automatically blanks
all normally blank lines as per CCIR-624. Mode 2 is illustrated in Figure 40 (NTSC) and Figure 41 (PAL). Figure 42 illustrates
the HSYNC, BLANK and VSYNC for an even-to-odd field transition relative to the pixel data. Figure 43 illustrates the HSYNC,
BLANK and VSYNC for an odd-to-even field transition relative to the pixel data.
Figure 42.Timing Mode 2, Even-to-Odd Field Transition Master/Slave
ADV7190/ADV7191
Mode 3:Master/Slave Option HSYNC, BLANK, FIELD(Timing Register 0 TR0 = X X X X X 1 1 0 or X X X X X 1 1 1)
In this mode the ADV7190/ADV7191 accepts or generates Horizontal SYNC and Odd/Even FIELD signals. A transition of the
FIELD input when HSYNC is high indicates a new frame, i.e., Vertical Retrace. The BLANK signal is optional. When the
BLANK input is disabled the ADV7190/ADV7191 automatically blanks all normally blank lines as per CCIR-624. Mode 3 is illustrated
in Figure 44 (NTSC) and Figure 45 (PAL).
Figure 44.Timing Mode 3, NTSC
Figure 45.Timing Mode 3, PAL
MPU PORT DESCRIPTIONThe ADV7190/ADV7191 supports a two-wire serial (I2C-
compatible) microprocessor bus driving multiple peripherals.
Two inputs, Serial Data (SDA) and Serial Clock (SCL), carry
information between any device connected to the bus. Each
slave device is recognized by a unique address. The ADV7190/
ADV7191 has four possible slave addresses for both read and
write operations. These are unique addresses for each device
and are illustrated in Figure 46 and Figure 47. The LSB sets
either a read or write operation. Logic Level 1 corresponds to a
read operation while Logic Level 0 corresponds to a write opera-
tion. A1 is set by setting the ALSB pin of the ADV7190/ADV7191
to Logic Level 0 or Logic Level 1.
Figure 46.Slave Address
To control the various devices on the bus the following protocol
must be followed. First, the master initiates a data transfer by
establishing a start condition, defined by a high-to-low transition
on SDA while SCL remains high. This indicates that an address/
data stream will follow. All peripherals respond to the start con-
dition and shift the next eight bits (7-bit address + R/W bit). The
bits are transferred from MSB down to LSB. The peripheral that
recognizes the transmitted address responds by pulling the data
line low during the ninth clock pulse. This is known as an acknowl-
edge bit. All other devices withdraw from the bus at this point
and maintain an idle condition. The idle condition is where
the device monitors the SDA and SCL lines waiting for the
start condition and the correct transmitted address. The R/W bit
determines the direction of the data.
A Logic 0 on the LSB of the first byte means that the master
will write information to the peripheral. A Logic 1 on the LSB
of the first byte means that the master will read information
from the peripheral.
The ADV7190/ADV7191 acts as a standard slave device on
the bus. The data on the SDA pin is eight bits long supporting
the 7-bit addresses plus the R/W bit. It interprets the first byte as
the device address and the second byte as the starting subaddress.
The subaddresses autoincrement allowing data to be written to
or read from the starting subaddress. A data transfer is always
terminated by a stop condition. The user can also access any
unique subaddress register on a one-by-one basis without having
to update all the registers. There is one exception. The Subcarrier
Frequency Registers should be updated in sequence, starting
with Subcarrier Frequency Register 0. The autoincrement function
should be then used to increment and access Subcarrier Frequency
Registers 1, 2, and 3. The Subcarrier Frequency Registers should
not be accessed independently.
Stop and start conditions can be detected at any stage during
the data transfer. If these conditions are asserted out of sequence
with normal read and write operations, they cause an immediate
jump to the idle condition. During a given SCL high period the
user should issue only one start condition, one stop condition,
or a single stop condition followed by a single start condition.
If, an invalid subaddress is issued by the user, the ADV7190/
ADV7191 will not issue an acknowledge and will return to the
idle condition. If in autoincrement mode, the user exceeds the
highest subaddress, the following action will be taken:In Read Mode, the highest subaddress register contents
will continue to be output until the master device issues a
no-acknowledge. This indicates the end of a read. A no-
acknowledge condition is where the SDA line is not pulled
low on the ninth pulse.In Write Mode, the data for the invalid byte will be not be
loaded into any subaddress register, a no-acknowledge will
be issued by the ADV7190/ADV7191 and the part will return
to the idle condition.
Figure 47.Bus Data Transfer
Figure 47 illustrates an example of data transfer for a read
sequence and the start and stop conditions.
Figure 48 shows bus write and read sequences.
Figure 48.Write and Read Sequences
ADV7190/ADV7191
REGISTER ACCESSESThe MPU can write to or read from all of the registers of the
ADV7190/ADV7191 with the exception of the Subaddress Regis-
ters, which are write-only registers. The Subaddress Register
determines which register the next read or write operation ac-
cesses. All communications with the part through the bus start
with an access to the Subaddress Register. Then a read/write
operation is performed from/to the target address which then
increments to the next address until a stop command on the bus is
performed.
REGISTER PROGRAMMINGThe following section describes each register. All registers can
be read from as well as written to.
Subaddress Register (SR7–SR0)The Communications Register is an eight bit write-only register.
After the part has been accessed over the bus and a read/write
operation is selected, the subaddress is set up. The Subaddress
Register determines to/from which register the operation takes
place.
Figure 49 shows the various operations under the control of the
Subaddress Register 0 should always be written to SR7.
Register Select (SR6–SR0)These bits are set up to point to the required starting address.
MODE REGISTER 0
MR0 (MR07–MR00)
(Address (SR4–SR0) = 00H)Figure 50 shows the various operations under the control of
Mode Register 0.
MR0 BIT DESCRIPTION
Output Video Standard Selection (MR00–MR01)These bits are used to set up the encoder mode. The ADV7190/
ADV7191 can be set up to output NTSC, PAL (B, D, G, H, I),
PAL M or PAL N standard video.
Luminance Filter Select (MR02–MR04)These bits specify which luma filter is to be selected. The filter
selection is made independent of whether PAL or NTSC is
selected.
Chrominance Filter Select (MR05–MR07)These bits select the chrominance filter. A low-pass filter can be
selected with a choice of cut-off frequencies (0.65 MHz, 1.0 MHz,
1.3 MHz, 2 MHz, or 3 MHz) along with a choice of CIF or
QCIF filters.
MODE REGISTER 1
MR1 (MR17–MR10)
(Address (SR4–SR0) = 01H)Figure 51 shows the various operations under the control of
Mode Register 1.
MR1 BIT DESCRIPTION
DAC Control (MR10–MR15)Bits MR15–MR10 can be used to power down the DACs. This are
used to reduce the power consumption of the ADV7190/ADV7191
or if any of the DACs are not required in the application.
4� Oversampling Control (MR16)To enable 4× Oversampling this bit has to be set to 1. When
enabled, the data is output at a frequency of 54 MHz.
Note that PLL Enable Control has to be enabled (MR61 = 0) in
4× Oversampling mode.
Reserved (MR17)A Logical 0 must be written to this bit.
Figure 50.Mode Register 0 (MR0)
Figure 51.Mode Register 1 (MR1)
ADV7190/ADV7191
MODE REGISTER 2
MR2 (MR27–MR20)
(Address (SR4–SR0) = 02H)Mode Register 2 is a 8-bit wide register.
Figure 52 shows the various operations under the control of Mode
Register.
MR2 BIT DESCRIPTION— RGB/YUV Control (MR20)This bit enables the output from the small or large DACs to be
set to YUV or RGB output video standard.
DAC Output Control (MR21)This bit controls the output from DACs A, B, and C. When this
bit is set to 1, Composite, Luma, and Chroma Signals are out-
put from DACs A, B, and C (respectively). When this bit is set
to 0, RGB or YUV may be output from these DACs.
SCART Enable Control (MR22)This bit is used to switch the DAC outputs from SCART to a
EUROSCART configuration. A complete table of all DAC out-
put configurations is shown in Table III.
Pedestal Control (MR23)This bit specifies whether a pedestal is to be generated on the
NTSC composite video signal. This bit is invalid when the device
is configured in PAL mode.
Square Pixel Control (MR24)This bit is used to set up square pixel mode. This is available in
Slave Mode only. For NTSC, a 24.5454MHz clock must be
supplied. For PAL, a 29.5 MHz clock must be supplied. Square
pixel operation is not available in 4× Oversampling mode.
Standard I2C Control (MR25)This bit controls the video standard used by the ADV7190/
ADV7191. When this bit is set to 1 the video standard as pro-
grammed in Output Video Standard Selection (MR00, MR01).
When MR25 is set to 0, the ADV7190/ADV7191 is forced into
the standard selected by the NTSC_PAL pin. When NTSC_PAL
is low the standard is NTSC, when the NTSC_PAL pin is high,
the standard is PAL.
Pixel Data Valid Control (MR26)After resetting the device, this bit has the value 0 and the pixel
data input to the encoder is blanked such that a black screen is
output from the DACs. The ADV7190/ADV7191 will be set
to Master Mode timing. When this bit is set to 1 by the user
(via the I2C), pixel data passes to the pins and the encoder re-
verts to the Timing Mode defined by Timing Register 0.
Sleep Mode Control (MR27)When this bit is set (1), Sleep Mode is enabled. With this mode
enabled, the ADV7190/ADV7191 current consumption is reduced
to less than 1mA. The I2C registers can be written to and read
from when the ADV7190/ADV7191 is in Sleep Mode.
When the device is in Sleep Mode and 0 is written to MR27, the
ADV7190/ADV7191 will come out of Sleep Mode and resume
normal operation. Also, if a RESET is applied during Sleep
Mode, the ADV7190/ADV7191 will come out of Sleep Mode
and resume normal operation.
For this to operate, Power Up in Sleep Mode Control has to be
enabled (MR60 = 0), otherwise Sleep Mode is controlled by
the PAL_NTSC and SCRESET/RTC/TR pins.
Table III.DAC Output Configuration MatrixFigure 52.Mode Register 2 (MR2)
MODE REGISTER 3
MR3 (MR37–MR30)
(Address (SR4–SR0) = 03H)Mode Register 3 is a 8-bit wide register. Figure 53 shows the
various operations under the control of Mode Register 3.
MR3 BIT DESCRIPTION
Revision Code (MR30–MR31)This bit is read only and indicates the revision of the device.
VBI_Open (MR32)This bit determines whether or not data in the Vertical Blanking
Interval (VBI) is output to the analog outputs or blanked. Note
that this condition is also valid in Timing Slave Mode 0. For
further information see Vertical Blanking Data Insertion and
BLANK Input section.
Teletext Enable (MR33)This bit must be set to 1 to enable teletext data insertion on
the TTX pin.
Teletext Bit Request Mode Control (MR34)This bit enables switching of the teletext request signal from a
continuous high signal (MR34 = 0) to a bitwise request signal
(MR34 = 1).
Closed Captioning Field Control (MR35–MR36)These bits control the fields that closed captioning data is dis-
played on, closed captioning information can be displayed on
an odd field, even field or both fields.
Reserved (MR37)A Logic 0 must be written to this bit.
MODE REGISTER 4
MR4 (MR47–MR40)
(Address (SR4–SR0) = 04H)Mode Register 4 is a 8-bit wide register. Figure 54 shows the
various operations under the control of Mode Register 4.
MR4 BIT DESCRIPTION
VSYNC_3H Control (MR40)When this bit is enabled (1) in Slave Mode, it is possible to
drive the VSYNC input low for 2.5 lines in PAL mode and
three lines in NTSC mode. When this bit is enabled in Master
Mode the ADV7190/ADV7191 outputs an active low VSYNC
signal for three lines in NTSC mode and 2.5 lines in PAL mode.
Genlock Control (MR41–MR42)These bits control the Genlock feature and timing reset of
the ADV7190/ADV7191 Setting MR41 and MR42 to Logic 0
disables the SCRESET/RTC/TR pin and allows the ADV7190/
ADV7191 to operate in normal mode.By setting MR41 to zero and MR42 to one a timing reset is
applied, resetting the horizontal and vertical counters. This
has the effect of resetting the Field Count to Field 0.
If the SCRESET/RTC/TR pin is held high, the counters
will remain reset. Once the pin is released the counters will
commence counting again. For correct counter reset, the
SCRESET/RTC/TR pin has to remain high for at least
37 ns (one clock cycle at 27 MHz).If MR41 is set to one and MR42 is set to zero, the SCRESET/
RTC/TR pin is configured as a subcarrier reset input and
the subcarrier phase will reset to Field 0 whenever a low-to-
high transition is detected on the SCRESET/RTC/TR pin
(SCH phase resets at the start of the next field).If MR41 is set to one and MR42 is set to one, the SCRESET/
RTC/TR pin is configured as a real-time control input and
the ADV7190/ADV7191 can be used to lock to an external
video source working in RTC mode. For more information see
Real-Time Control, Subcarrier Reset and Timing Reset section.
Active Video Line Duration (MR43)This bit switches between two active video line durations. A zero
selects CCIR Rec. 601 (720 pixels PAL/NTSC) and a one
selects ITU-R BT. 470 standard for active video duration (710
pixels NTSC, 702 pixels PAL).
Chrominance Control (MR44)This bit enables the color information to be switched on and off
the chroma composite, color component outputs.
Burst Control (MR45)This bit enables the color burst to be switched on and off the
chroma and composite outputs.
Color Bar Control (MR46)This bit can be used to generate and output an internal color
bar test pattern. The color bar configuration is 100/7.5/75/7.5
for NTSC and 100/0/75/0 for PAL. It is important to note that
when color bars are enabled the ADV7190/ADV7191 is con-
figured in a Master Timing mode. The output pins VSYNC,
HSYNC and BLANK are three-state during color bar mode.
ADV7190/ADV7191
Interlaced Mode Control (MR47)This bit is used to setup the output to interlaced or noninterlaced
mode.
MODE REGISTER 5
MR5 (MR57–MR50)
(Address (SR4–SR0) = 05H)Mode Register 5 is a 8-bit wide register. Figure 55 shows the
various operations under the control of Mode Register 5.
MR5 BIT DESCRIPTION
Y-Level Control (MR50)This bit controls the component Y output level on the ADV7190/
ADV7191. If this bit is set (0), the encoder outputs Betacam
levels when configured in PAL or NTSC mode. If this bit is
set (1), the encoder outputs SMPTE levels when configured
in PAL or NTSC mode.
UV-Levels Control (MR51–MR52)These bits control the component U and V output levels on
the ADV7190/ADV7191. It is possible to have UV levels with
a peak-to-peak amplitude of either 700 mV (MR52 + MR51
= 01 ) or 1000 mV (MR52 + MR51 = 10) in NTSC and PAL.
It is also possible to have default values of 934 mV for NTSC
and 700 mV for PAL (MR52 + MR51 = 00).
RGB Sync (MR53)This bit is used to set up the RGB outputs with the sync infor-
mation encoded on all RGB outputs.
Clamp Delay Value (MR54–MR55)These bits control the delay or advance of the CLAMP signal
in the front or back porch of the ADV7190/ADV7191. It is pos-
sible to delay or advance the pulse by zero, one, two, or three
clock cycles.
Note:Pin 51 is a multifunctional pin (VSO/CLAMP). CLAMP/
VSO Select Control (MR77) has to be set accordingly.
Clamp Delay Direction (MR56)This bit controls a positive or negative delay in the CLAMP sig-
nal. If this bit is set (1), the delay is negative. If it is set (0), the
delay is positive.
Clamp Position (MR57)This bit controls the position of the CLAMP signal. If this bit is
set (1), the CLAMP signal is located in the back porch position.
If this bit is set (0), the CLAMP signal is located in the front
porch position.
Figure 55. Mode Register 5 (MR5)
Figure 54.Mode Register 4 (MR4)
MODE REGISTER 6
MR6 (MR67–MR60)
(ADDRESS (SR4–SR0) = 06H)Mode Register 6 is an 8-bit-wide register. Figure 56 shows the
various operations under the control of Mode Register 6.
MR6 BIT DESCRIPTION
Power-Up Sleep Mode Control (MR60)After RESET is applied this control is enabled (MR60 = 0) if
both SCRESET/RTC/TR and NTSC_PAL pins are tied high.
The ADV7190/ADV7191 will then power up in Sleep Mode to
facilitate low power consumption while the I2C is initialized.
When this control is disabled (MR60 = 1, via the I2C) Sleep
Mode control passes to Sleep Mode Control, MR27.
PPL Enable Control (MR61)The PLL control should be enabled (MR61 = 0 ) when 4×
Oversampling is enabled (MR16 = 1). It is also used to reset the
PLL when this bit is toggled.
Reserved (MR62, MR63, MR64)A Logic 0 must be written to these bits.
Field Counter (MR65, MR66, MR67)These three bits are read-only bits. The field count can be read
back over the I2C interface. In NTSC mode the field count goes
from 0–3, in PAL Mode from 0–7.
MODE REGISTER 7
MR7 (MR77–MR70)
(Address (SR4–SR0) = 07H)Mode Register 7 is an 8-bit wide register. Figure 57 shows the
various operations under the control of Mode Register 7.
MR7 BIT DESCRIPTION
Color Control Enable (MR70)This bit is used to enable control of contrast and saturation of
color. If this bit is set (1) color controls are enabled (Contrast
Control Register, U-Scale Register, V-Scale Register). If this bit
is set (0), the color control features are disabled.
Luma Saturation Control (MR71)When this bit is set (1), the luma signal will be clipped if it reaches
a limit that corresponds to an input luma value of 255 (after
scaling by the Contrast Control Register). This prevents the
chrominance component of the composite video signal being
clipped if the amplitude of the luma is too high. When this bit is
set (0), this control is disabled.
Hue Adjust Control (MR72)This bit is used to enable hue adjustment on the composite and
chroma output signals of the ADV7190/ADV7191. When this
bit is set (1), the hue of the color is adjusted by the phase offset
described in the Hue Adjust Control Register. When this bit is
set (0), hue adjustment is disabled.
Brightness Enable Control (MR73)This bit is used to enable the brightness control of the ADV7190/
ADV7191. The actual brightness level is programmed in the
Brightness Control Register. This value or “setup” level is added to
the scaled Y data. When this bit is set (1), brightness control
is enabled. When this bit is set (0), brightness control is disabled.
Sharpness Filter Enable (MR74)This bit is used to enable the sharpness control of the luminance
signal on the ADV7190/ADV7191 (Luma Filter Select has to
be set to Extended, i.e., MR04–MR02 = 100). The various
responses of the filter are determined by the Sharpness Con-
trol Register. When this bit is set (1), the luma response is altered
by the amount described in the Sharpness Control Register.
When this bit is set (0), the sharpness control is disabled. See In-
ternal Filter Response section for luma signal responses.
CSO_HSO Output Control (MR75)This bit is used to determine whether HSO or CSO TTL output
signal is output at the CSO_HSO pin. If this bit is set 1, then
the CSO TTL signal is output. If this bit is set 0, the HSO TTL
signal is output.
Figure 56.Mode Register 6 (MR6)
ADV7190/ADV7191
Reserved (MR76)A Logic 0 must be written to this bit.
CLAMP/VSO Select (MR77)This bit is used to select the functionality of Pin 51. A 1 selects
CLAMP as the output signal. A 0 selects VSO output.
MODE REGISTER 8
MR8 (MR87–MR80)
(Address (SR4–SR0) = 08H)Mode Register 8 is an 8-bit-wide register. Figure 58 shows the
various operations under the control of Mode Register 8.
MR8 BIT DESCRIPTION
Reserved (MR80, MR81)A Logic 0 must be written to these bits.
Double Buffer Control (MR82)Double buffering can be enabled or disabled on the Contrast
Control Register, U Scale Register, V Scale Register, Hue Adjust
Control Register, Closed Captioning Register, Brightness Con-
trol Register, Gamma Curve Select Bit and the Macrovision
Registers. Double Buffering is not available in Master Timing
mode.
16-Bit Pixel Port (MR83)This bit controls if the ADV7190/ADV7191 accepts 8-bit or
16-bit input data. In 8-bit mode the data will be input on Pins
P0–P7. Unused pixel inputs should be grounded.
Reserved (MR84)A Logic 0 must be written to this bit.
DNR Enable Control (MR85)To enable the DNR process this bit has to be set to 1. If this bit
is set to 0, the DNR processing is bypassed. For further infor-
mation on DNR controls see DNR Registers 2–0, DNR1 Bit
Description, and DNR2 Bit Description sections.
Gamma Enable Control (MR86)To enable the programmable gamma correction this bit has
to be set to enabled (MR86 is set to 1). For further information
on Gamma Correction controls see Gamma Correction Registers
0–13 (Gamma 0–13) (Address (SR5–SR0) = 26H–32H section.
Gamma Curve Select Control (MR87)This bit selects which of the two programmable gamma curves is
used. When setting MR87 to 0, the gamma correction curve to be
processed is Curve A. Otherwise, Curve B is selected. For fur-
ther information on Gamma Correction controls see Gamma
Correction Registers 0–13 (Gamma 0–13) (Address (SR5–SR0)
= 26H–32H section.
MODE REGISTER 9
MR9 (MR97–MR90)
(Address (SR4–SR0) = 09H)Mode Register 9 is an 8-bit-wide register. Figure 59 shows
the various operations under the control of Mode Register 9.
MR9 BIT DESCRIPTION
Undershoot Limiter (MR90–MR91)This control ensures that no luma video data will go below a
programmable level. This prevents any synchronization problems
due to luma signals going below the blanking level. Available
limit levels are –1.5 IRE, –6 IRE, –11 IRE.
Note that this facility is only available in 4× Oversampling mode
(MR16 = 1). When the device is operated in 2× Oversampling
mode (MR16 = 0) or RGB outputs without RGB sync are
selected, the minimum luma level is set in Timing Register 0,
TR06 (Min Luma Control).
Reserved (MR92–MR93)A Logic 0 must be written to these bits.
Chroma Delay Control (MR94–MR95)The Chroma Signal can be delayed by up to 296 ns (eight clock
cycles at 27 MHz) using MR94–MR95. For further informa-
tion see also Chroma/Luma Delay section.
Reserved (MR96–MR97)A Logic 0 must be written to these bits.
Figure 58.Mode Register 8 (MR8)
TIMING REGISTER 0 (TR07–TR00)
(Address (SR4–SR0) = 0AH)Figure 60 shows the various operations under the control of
Timing Register 0. This register can be read from as well as
written to.
TR0 BIT DESCRIPTION
Master/Slave Control (TR00)This bit controls whether the ADV7190/ADV7191 is in master or
slave mode.
Timing Mode Selection (TR01–TR02)These bits control the timing mode of the ADV7190/ADV7191.
These modes are described in more detail in the Video Tim-
ing Description and RESET Sequence sections of the data sheet.
BLANK Input Control (TR03)This bit controls whether the BLANK input is used to accept
blank signals or whether blank signals are internally generated.
Note:When this input pin is tied high (to 5 V), the input is dis-
abled regardless of the register setting. It, therefore, should be
tied low (to Ground) to allow control over the I2C register.
Luma Delay (TR04–TR05)The luma signal can be delayed by up to 222 ns (or six clock
cycles at 27 MHz) using TR04–TR05. For further information
see Chroma/Luma Delay section.
Min Luminance Value (TR06)This bit is used to control the minimum luma output value
by the ADV7190/ADV7191 in 2× Oversampling Mode (MR 16 =
0). When this bit is set to a Logic 1, the luma is limited to 7.5IRE
below the blank level. When this bit is set to (0), the luma value
can be as low as the sync bottom level (40IRE below blanking).
Timing Register Reset (TR07)Toggling TR07 from low to high and low again resets the inter-
nal timing counters. This bit should be toggled after power-up,
reset, or changing to a new timing mode.
TIMING REGISTER 1
(TR17–TR10)
(Address (SR4–SR0) = 0BH)Timing Register 1 is an 8-bit-wide register.
Figure 61 shows the various operations under the control of
Timing Register 1. This register can be read from as well written
to. This register can be used to adjust the width and position of
the master mode timing signals.
TR1 BIT DESCRIPTION
HSYNC Width (TR10–TR11)These bits adjust the HSYNC pulsewidth.
TPCLK = one clock cycle at 27 MHz.
HSYNC to VSYNC Delay Control (TR12–TR13)These bits adjust the position of the HSYNC output relative to
the VSYNC output.
TPCLK = one clock cycle at 27 MHz.
HSYNC to VSYNC Rising Edge Control (TR14–TR15)When the ADV7190/ADV7191 is in Timing Mode 1, these bits
adjust the position of the HSYNC output relative to the VSYNC
output rising edge.
TPCLK = one clock cycle at 27 MHz.
VSYNC Width (TR14–TR15)When the ADV7190/ADV7191 is configured in Timing Mode
2, these bits adjust the VSYNC pulsewidth.
TPCLK = one clock cycle at 27 MHz.
HSYNC to Pixel Data Adjust (TR16–TR17)This enables the HSYNC to be adjusted with respect to the
pixel data. This allows the Cr and Cb components to be swapped.
This adjustment is available in both master and slave timing
modes.
TPCLK = one clock cycle at 27 MHz.
Figure 60.Timing Register 0
