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AM27C64-255DC , 64 Kilobit (8 K x 8-Bit) CMOS EPROM
AM27C64-255DC , 64 Kilobit (8 K x 8-Bit) CMOS EPROM
AM27C64-255DI , 64 Kilobit (8 K x 8-Bit) CMOS EPROM
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AM27C64-55DC , 64 Kilobit (8 K x 8-Bit) CMOS EPROM
ADV7181BST
NTSC/PAL/SECAM Video Decoder
Multiformat SDTV Video DecoderRev. A
FEATURES
Multiformat video decoder supports NTSC-(M, N, 4.43),
PAL-(B/D/G/H/I/M/N), SECAM
Integrates three 54 MHz, 9-bit ADCs
Clocked from a single 27 MHz crystal
Line-locked clock compatible (LLC)
Adaptive Digital Line Length Tracking (ADLLT™)
5-line adaptive comb filters
Proprietary architecture for locking to weak, noisy, and
unstable video sources such as VCRs and tuners
Subcarrier frequency lock and status information output
Integrated AGC with adaptive peak white mode
Macrovision® copy protection detection
CTI (chroma transient improvement)
DNR (digital noise reduction)
Multiple programmable analog input formats:
CVBS (composite video)
S-Video (Y/C)
YPrPb component (VESA, MII, SMPTE, and BetaCam)
6 analog video input channels
Automatic NTSC/PAL/SECAM identification
Digital output formats (8-bit or16-bit):
ITU-R BT.656 YCrCb 4:2:2 output + HS, VS, and FIELD
0.5 V to 1.6 V analog signal input range
Differential gain: 0.6% typ
Differential phase: 0.6° typ
Programmable video controls:
Peak-white/hue/brightness/saturation/contrast
Integrated on-chip video timing generator
Free run mode (generates stable video ouput with no I/P)
VBI decode support for
Close captioning, WSS, CGMS, EDTV, Gemstar® 1×/2×
Power-down mode
2-wire serial MPU interface (I2C® compatible)
3.3 V analog, 1.8 V digital core; 3.3 V IO supply
Temperature grade:–40°C to +85°C
80-lead LQFP Pb-free package
APPLICATIONS
DVD recorders
PC Video
HDD-based PVRs/DVDRs
LCD TVs
Set-top boxes
Security systems
Digital televisions
Portable video devices
Automotive entertainment
AVR receiver
GENERAL DESCRIPTION The ADV7181 integrated video decoder automatically detects
and converts a standard analog baseband television signal
compatible with worldwide standards NTSC, PAL, and SECAM
into 4:2:2 component video data compatible with 16-/8-bit
CCIR601/CCIR656.
The advanced and highly flexible digital output interface
enables performance video decoding and conversion in line-
locked clock based systems. This makes the device ideally suited
for a broad range of applications with diverse analog video
characteristics, including tape based sources, broadcast sources,
security/surveillance cameras, and professional systems.
The 6 analog input channels accept standard Composite, S-
Video, YPrPb video signals in an extensive number of
combinations. AGC and clamp restore circuitry allow an input
video signal peak-to-peak range of 0.5 V up to 1.6 V.
Alternatively, these can be bypassed for manual settings.
The fixed 54 MHz clocking of the ADCs and datapath for all
modes allows very precise, accurate sampling and digital
filtering. The line-locked clock output allows the output data
rate, timing signals, and output clock signals to be synchronous,
asynchronous, or line locked even with ±5% line length
variation. The output control signals allow glueless interface
connections in almost any application. The ADV7181 modes
are set up over a 2-wire, serial, bidirectional port (I2C
compatible).
The ADV7181 is fabricated in a 3.3 V CMOS process. Its
monolithic CMOS construction ensures greater functionality
with lower power dissipation.
The ADV7181 is packaged in a small 80-lead LQFP Pb-free
package.
TABLE OF CONTENTS Introduction......................................................................................4
Analog Front End.........................................................................4
Standard Definition Processor...................................................4
Functional Block Diagram..............................................................5
Specifications.....................................................................................6
Electrical Characteristics.............................................................6
Video Specifications.....................................................................7
Timing Specifications..................................................................8
Analog Specifications...................................................................8
Thermal Specifications................................................................8
Timing Diagrams..........................................................................9
Absolute Maximum Ratings..........................................................10
ESD Caution................................................................................10
Pin Configuration and Function Descriptions...........................11
Analog Front End...........................................................................13
Analog Input Muxing................................................................13
Global Control Registers...............................................................15
Power-Save Modes......................................................................15
Reset Control..............................................................................15
Global Pin Control.....................................................................16
Global Status Registers...................................................................18
Identification...............................................................................18
Status 1.........................................................................................18
Status 2.........................................................................................19
Status 3.........................................................................................19
Standard Definition Processor (SDP)..........................................20
SD Luma Path.............................................................................20
SD Chroma Path.........................................................................20
SDP Sync Processing..................................................................21
SDP VBI Data Recovery............................................................21
SDP General Setup.....................................................................21
SDP Color Controls...................................................................24
SDP Clamp Operation...............................................................26
SDP Luma Filter.........................................................................27
SDP Chroma Filter.....................................................................30
SDP Gain Operation..................................................................31
SDP Chroma Transient Improvement (CTI)..........................35
SDP Digital Noise Reduction (DNR)......................................36
SDP Comb Filters.......................................................................36
SDP AV Code Insertion and Controls.....................................39
SDP Synchronization Output Signals......................................41
SDP Sync Processing..................................................................50
SDP VBI Data Decode...............................................................51
Pixel Port Configuration...............................................................62
MPU Port Description...................................................................63
Register Accesses........................................................................64
Register Programming...............................................................64 2C Sequencer..............................................................................64 2C Control Register Map..........................................................65 2C Register Map Details...........................................................69
Appendix A......................................................................................96 2C Programming Examples.....................................................96
Appendix B......................................................................................99
PCB Layout Recommendations...............................................99
Appendix C...................................................................................101
Typical Circuit Connection....................................................101
Outline Dimensions.....................................................................103
Ordering Guide........................................................................104
REVISION HISTORY
Revision A 7/04—Changed from Rev. 0 to Rev. A.
Addition to Applications List...........................................................1
Changes to Table 3............................................................................8
Changes to Table 5............................................................................8
Replaced Figure 3..............................................................................9
Changes to Global Pin Control Section.......................................16
Changes to Table 202......................................................................91
Changes to Table 203......................................................................92
Added package in Outline Dimensions Section.......................103
Changes to Ordering Guide.........................................................104
Revision 0 5/04—Revision 0: Initial Version
INTRODUCTION The ADV7181 is a high quality, single chip, multiformat video
decoder that automatically detects and converts PAL, NTSC,
and SECAM standards in the form of composite, S-Video, and
component video into a digital ITU-R BT.656 format.
The advanced and highly flexible digital output interface
enables performance video decoding and conversion in line
locked clock based systems. This makes the device ideally suited
for a broad range of applications with diverse analog video
characteristics, including tape based sources, broadcast sources,
security/surveillance cameras, and professional systems.
ANALOG FRONT END The ADV7181 analog front-end comprises three 9-bit ADCs
that digitize the analog video signal before applying it to the
standard definition processor. The analog front end employs
differential channels to each ADC to ensure high performance
in mixed-signal applications.
The front end also includes a 6-channel input mux that enables
multiple video signals to be applied to the ADV7181. Current
and voltage clamps are positioned in front of each ADC to
ensure that the video signal remains within the range of the
converter. Fine clamping of the video signals is performed
downstream by digital fine clamping within the ADV7181. The
ADCs are configured to run in 4× oversampling mode.
STANDARD DEFINITION PROCESSOR The ADV7181 is capable of decoding a large selection of
baseband video signals in composite, S-Video, and component
formats. The video standards supported by the SDP include
PAL B/D/I/G/H, PAL60, PAL M, PAL N, PAL Nc, NTSC M/J,
NTSC 4.43, and SECAM B/D/G/K/L. The ADV7181 can
automatically detect the video standard and process it
accordingly.
The ADV7181 has a 5-line, superadaptive, 2D comb filter that
gives superior chrominance and luminance separation when
decoding a composite video signal. This highly adaptive filter
automatically adjusts its processing mode according to video
standard and signal quality with no user intervention required.
Video user controls such as brightness, contrast, saturation, and
hue are also available within the ADV7181.
The ADV7181 implements a patented adaptive digital line-
length tracking (ADLLT) algorithm to track varying video line
lengths from sources such as a VCR. ADLLT enables the
ADV7181 to track and decode poor quality video sources such
as VCRs, noisy sources from tuner outputs, VCD players, and
camcorders. The ADV7181 contains a chroma transient
improvement (CTI) processor that sharpens the edge rate of
chroma transitions, resulting in sharper vertical transitions.
The SDP can process a variety of VBI data services such as
closed captioning (CC), wide screen signaling (WSS), copy
generation management system (CGMS), EDTV, Gemstar
1×/2×, and extended data service (XDS). The ADV7181 is fully
Macrovision certified; detection circuitry enables Type I, II, and
III protection levels to be identified and reported to the user.
The decoder is also fully robust to all Macrovision signal inputs.
FUNCTIONAL BLOCK DIAGRAM
AIN1–
IN6
ALS
CONTROLAND DATAS
CLK CONTROL
PIXELDATAFIELDLLCSFL
VID
YPrPb04820-0-001
