ADV7179KCPZ ,Chip Scale NTSC/PAL Video EncoderGeneral Description ........ 11 Mode Register 1 (MR1) ....... 29 Data Path Description. 11 Mode Reg ..
ADV7180KCP32Z , 10-Bit, 4× Oversampling SDTV Video Decoder
ADV7181B ,NTSC/PAL/SECAM Video DecoderFEATURES Differential phase: 0.6° typ Multiformat video decoder supports NTSC-(M, J, 4.43), Program ..
ADV7181BBCPZ ,NTSC/PAL/SECAM Video DecoderGENERAL DESCRIPTION video signal peak-to-peak range of 0.5 V to 1.6 V. Alternatively, The ADV7181B ..
ADV7181BBSTZ ,NTSC/PAL/SECAM Video DecoderSpecifications . 8 VBI Data Decode ........ 46 Timing Diagrams.. 8 Pixel Port Configuration 58 Abs ..
ADV7181BST ,NTSC/PAL/SECAM Video DecoderSpecifications . 8 SDP Comb Filters........ 36 Timing Diagrams.. 9 SDP AV Code Insertion and Contro ..
AM27C64-120DE , 64 Kilobit (8 K x 8-Bit) CMOS EPROM
AM27C64-120DI , 64 Kilobit (8 K x 8-Bit) CMOS EPROM
AM27C64-120JC , 64 Kilobit (8 K x 8-Bit) CMOS EPROM
AM27C64-150DE , 64 Kilobit (8 K x 8-Bit) CMOS EPROM
AM27C64-150DI , 64 Kilobit (8 K x 8-Bit) CMOS EPROM
AM27C64-150JI , 64 Kilobit (8 K x 8-Bit) CMOS EPROM
ADV7179BCP-ADV7179KCP-ADV7179KCPZ
Chip Scale NTSC/PAL Video Encoder with Macrovision® Copy Protection
Chip Scale PAL/NTSC Video Encoder with
Advanced Power Management
Rev. A
FEATURES
ITU-R1 BT601/BT656 YCrCb to PAL/NTSC video encoder
High quality 10-bit video DACs
SSAF™ (super sub-alias filter)
Advanced power management features
CGMS (copy generation management system)
WSS (wide screen signaling)
NTSC M, PAL N2, PAL B/D/G/H/I, PAL-M3 , PAL 60
Single 27 MHz clock required (×2 oversampling)
Macrovision 7.1 (ADV7174 only)
80 dB video SNR
32-bit direct digital synthesizer for color subcarrier
Multistandard video output support:
Composite (CVBS)
Component S-video (Y/C)
Video input data port supports:
CCIR-656 4:2:2 8-bit parallel input format
Programmable simultaneous composite and S-video or RGB
(SCART)/YPbPr video outputs
Programmable luma filters low-pass [PAL/NTSC] notch,
extended SSAF, CIF, and QCIF
Programmable chroma filters (low-pass [0.65 MHz, 1.0 MHz,
1.2 MHz, and 2.0 MHz], CIF, and QCIF)
Programmable VBI (vertical blanking interval)
Programmable subcarrier frequency and phase
Programmable LUMA delay
Individual on/off control of each DAC
CCIR and square pixel operation
Integrated subcarrier locking to external video source
Color signal control/burst signal control
Interlaced/noninterlaced operation
Complete on-chip video timing generator
Programmable multimode master/slave operation
Closed captioning support
Teletext insertion port (PAL-WST)
On-board color bar generation
On-board voltage reference
2-wire serial MPU interface (I2C® compatible and fast I2C)
Single-supply 2.8 V and 3.3 V operation
Small 40-lead 6 mm × 6 mm LFCSP package
−40°C to +85°C at 3.3 V
−20°C to +85°C at 2.8 V
APPLICATIONS
Portable video applications
Mobile phones
Digital still cameras
FUNCTIONAL BLOCK DIAGRAM
SCLOCKSDATAALSB
HSYNC
FIELD/VSYNC
BLANK
CLOCKGND
DACA(PIN29)
VREF
RSET
COMP
COLOR
DATA
P7–P0
SCRESET/RTC
DACB(PIN28)
DACC(PIN24)
VAA
RESET
TTXREQTTX02980-A-001
Figure 1. ITU-R and CCIR are used interchangeably in this document (ITU-R has replaced CCIR recommendations).
2 Throughout the document, N is referenced to PAL – Combination – N. ADV7174 only.
. Patent Numbers 5,343,196 and 5,442,355 and other intellectual property rights.
. Patent Numbers 4,631,603, 4,577,216, 4,819,098 and other intellectual property rights. The Macrovision anticopy process is licensed for
noncommercial home use only, which is its sole intended use in the device. Contact the sales office for the latest Macrovision version available.
TABLE OF CONTENTS Specifications.....................................................................................4
2.8 V Specifications......................................................................4
2.8 V Timing Specifications........................................................5
3.3 V Specifications......................................................................6
3.3 V Timing Specifications........................................................7
Absolute Maximum Ratings............................................................9
ESD Caution..................................................................................9
Pin Configuration and Function Descriptions...........................10
General Description.......................................................................11
Data Path Description................................................................11
Internal Filter Response.............................................................11
Typical Performance Characteristics...........................................13
Features............................................................................................16
Color Bar Generation................................................................16
Square Pixel Mode......................................................................16
Color Signal Control..................................................................16
Burst Signal Control...................................................................16
NTSC Pedestal Control.............................................................16
Pixel Timing Description..........................................................16
8-Bit YCrCb Mode.................................................................16
Subcarrier Reset..........................................................................16
Real-Time Control.....................................................................16
Video Timing Description....................................................16
Vertical Blanking Data Insertion..........................................17
Mode 0 (CCIR-656): Slave Option.......................................17
Mode 0 (CCIR-656): Master Option...................................17
Mode 1: Slave Option HSYNC, BLANK, FIELD................20
Mode 1: Master Option HSYNC, BLANK, FIELD............21
Mode 2: Slave Option HSYNC, VSYNC, BLANK..............22
Mode 3: Master/Slave Option HSYNC, BLANK, FIELD..24
Power-On Reset..........................................................................25
SCH Phase Mode........................................................................25
MPU Port Description...............................................................25
Register Accesses........................................................................26
Register Programming...................................................................27
Subaddress Register (SR7–SR0)...............................................27
Register Select (SR5–SR0).........................................................27
Mode Register 1 (MR1).............................................................29
Mode Register 2 (MR2).............................................................30
Mode Register 3 (MR3).............................................................31
Mode Register 4 (MR4).............................................................32
Timing Mode Register 0 (TR0)................................................33
Timing Mode Register 1 (TR1)................................................34
Subcarrier Frequency Registers 3–0........................................35
Subcarrier Phase Register..........................................................35
Closed Captioning Even Field Data Registers 1–0................35
Closed Captioning Odd Field Data Registers 1–0.................36
NTSC Pedestal/PAL Teletext Control Registers 3–0.............36
Teletext Request Control Register (TC07)..............................37
CGMS_WSS Register 0 (C/W0)...............................................37
CGMS_WSS Register 1 (C/W1)...............................................38
CGMS_WSS Register 2 (C/W2)...............................................38
Appendix 1—Board Design and Layout Considerations..........39
Ground Planes............................................................................39
Power Planes...............................................................................39
Supply Decoupling.....................................................................40
Digital Signal Interconnect.......................................................40
Analog Signal Interconnect.......................................................40
Appendix 3—Copy Generation Management System (CGMS)
............................................................................................................42
Function of CGMS Bits..............................................................42
Appendix 4—Wide Screen Signaling (WSS)...............................43
Function of WSS Bits..................................................................43
Appendix 5—Teletext.....................................................................44
Teletext Insertion.........................................................................44
Teletext Protocol..........................................................................44
Appendix 6—Waveforms...............................................................45
NTSC Waveforms (with Pedestal)............................................45
NTSC Waveforms (without Pedestal)......................................46
PAL Waveforms...........................................................................47
Pb Pr Waveforms.........................................................................48
Appendix 7—Optional Output Filter...........................................49
Appendix 8—Recommended Register Values.............................50
Outline Dimensions........................................................................52
Ordering Guide...........................................................................52
REVISION HISTORY
2/04—Changed from REV. 0 to REV A. Added 2.8 V Version..........................................................Universal
Format Updated..................................................................Universal
Device Currents Updated on 3.3 V Specification..........Universal
Added new Table 1 and Renumbered Subsequent Tables.............4
Added new Table 2 and Renumbered Subsequent Tables...........5
Change to Figure 54........................................................................38
Change to Figure 55........................................................................39
Change to Figure 79........................................................................48
Changed Ordering Guide Temperature Specifications..............52
Updated Outline Dimensions........................................................52
10/02—Revision 0: Initial Version SPECIFICATIONS
2.8 V SPECIFICATIONS VAA = 2.8 V, VREF = 1.235 V, RSET = 150 Ω. All specifications TMIN to TMAX1, unless otherwise noted.
Table 1. 1 Temperature range TMIN to TMAX: –20°C to +85°C. Guaranteed by characterization.
3 DACs can output 35 mA typically at 2.8 V (RSET = 150 Ω and RL = 37.5 Ω). Full drive into 37.5 Ω load. Power measurements are taken with clock frequency = 27 MHz. Max TJ = 110°C.
5 IDAC is the total current (min corresponds to 5 mA output per DAC, max corresponds to 37 mA output per DAC) to drive all three DACs. Turning off individual DACs
reduces IDAC correspondingly.
6 ICCT (circuit current) is the continuous current required to drive the device. Total DAC current in sleep mode.
8 Total continuous current during sleep mode.
2.8 V TIMING SPECIFICATIONS VAA = 2.8 V, VREF = 1.235 V, RSET = 150 Ω. All specifications TMIN to TMAX1, unless otherwise noted.
Table 2. 1 Temperature range TMIN to TMAX: –20°C to +85°C. TTL input values are 0 V to 2.8 V, with input rise/fall times −3 ns, measured between the 10% and 90% points. Timing reference points at 50% for inputs and outputs.
Analog output load –10 pF. Guaranteed by characterization.
4 Output delay measured from the 50% point of the rising edge of CLOCK to the 50% point of full-scale transition. See Figure 60.
6 Teletext Port consists of the following:
Teletext Output: TTXREQ
Teletext Input: TTX
3.3 V SPECIFICATIONS VAA = 3.0 V–3.6 V1, VREF = 1.235 V, RSET = 150 Ω. All specifications TMIN to TMAX2, unless otherwise noted.
Table 3. 1 The max/min specifications are guaranteed over this range. The max/min values are typical over 3.0 V to 3.6 V. Temperature range TMIN to TMAX: –40°C to +85°C.
3 Guaranteed by characterization. Full drive into 37.5 Ω load.
5 DACs can output 35 mA typically at 3.3 V (RSET = 150 Ω and RL = 37.5 Ω), optimum performance obtained at 18 mA DAC current (RSET = 300 Ω and RL = 75 Ω). Minimum drive current (used with buffered/scaled output load).
7 Power measurements are taken with clock frequency = 27 MHz. Max TJ = 110°C. IDAC is the total current (min corresponds to 5 mA output per DAC, max corresponds to 37 mA output per DAC) to drive all three DACs. Turning off individual DACs
reduces IDAC correspondingly. ICCT (circuit current) is the continuous current required to drive the device.
10 Total DAC current in sleep mode. Total continuous current during sleep mode.
3.3 V TIMING SPECIFICATIONS VAA = 3.0 V–3.6 V1, VREF = 1.235 V, RSET = 150 Ω. All specifications TMIN to TMAX2, unless otherwise noted.
Table 4. 1 The maximum/minimum specifications are guaranteed over this range. The maximum/minimum values are typical over 3.0 V to 3.6 V range. Temperature range TMIN to TMAX: –40°C to +85°C.
3 TTL input values are 0 V to 3 V, with input rise/fall times −3 ns, measured between the 10% and 90% points. Timing reference points at 50% for inputs and outputs.
Analog output load –10 pF.
4 Guaranteed by characterization. Output delay measured from the 50% point of the rising edge of CLOCK to the 50% point of full-scale transition.
6 See Figure 60.
t8SDATA02980-0A
Figure 2. MPU Port Timing Diagram
CLOCK
PIXEL INPUT
DATA
HSYNC,
FIELD/VSYNC,
BLANK
HSYNC,
FIELD/VSYNC,
BLANK
CONTROL
I/PS
CONTROL
O/PS02980-A
Figure 3. Pixel and Control Data Timing Diagram
TTXREQ
CLOCK
TTX02980-A
Figure 4. Teletext Timing Diagram
ABSOLUTE MAXIMUM RATINGS
Table 5. Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability
__________ Analog output short circuit to any power supply or common can be of an indefinite duration.
2 With the exposed metal paddle on the underside of LFCSP soldered to GND on the PCB.
ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS VREF
DAC A
DAC B
VAA
GND
VAA
DAC C
BLANK
GNDGND
SYN
FIELD
/VSYN
ALS
VAA
GND
GND
GND
GND
VAA
COMP
SDATA
SCLOCK
GND
GND
ESET
GNDP4P3P2P1P0TTXTTXREQR
SET
ESET/
RTC02980-A
Figure 5. Pin Configurations
Table 6. Pin Function Descriptions
GENERAL DESCRIPTION The ADV7174/ADV7179 is an integrated digital video encoder
that converts digital CCIR-601 4:2:2 8-bit component video data
into a standard analog baseband television signal compatible
with worldwide standards.
The on-board SSAF (super sub-alias filter) with extended
luminance frequency response and sharp stop-band attenuation
enables studio quality video playback on modern TVs, giving
optimal horizontal line resolution.
An advanced power management circuit enables optimal con-
trol of power consumption in both normal operating modes
and in power-down or sleep modes.
The ADV7174/ADV7179 supports both PAL and NTSC square
pixel operation. The parts incorporate WSS and CGMS-A data
control generation.
The output video frames are synchronized with the incoming
data timing reference codes. Optionally, the encoder accepts
(and can generate) HSYNC, VSYNC, and FIELD timing signals.
These timing signals can be adjusted to change pulse width and
position while the part is in the master mode. The encoder
requires a signal two times the pixel rate (27 MHz) clock for
standard operation. Alternatively, the encoder requires a
24.5454 MHz clock for NTSC or 29.5 MHz clock for PAL
square pixel mode operation. All internal timing is generated
on-chip.
A separate Teletext port enables the user to directly input
Teletext data during the vertical blanking interval.
The ADV7174/ADV7179 modes are set up over a 2-wire serial
bidirectional port (I2 C compatible) with two slave addresses.
The ADV7174/ADV7179 is packaged in a 40-lead 6 mm × 6 mm
LFCSP package.
DATA PATH DESCRIPTION For PAL B/D/G/H/I/M/N and NTSC M and N modes, YCrCb
4:2:2 data is input via the CCIR-656 compatible pixel port at a
27 MHz data rate. The pixel data is demultiplexed to form three
data paths. Y typically has a range of 16 to 235, and Cr and Cb
typically have a range of 128 ± 112; however, it is possible to
input data from 1 to 254 on both Y, Cb, and Cr. The ADV7174/
ADV7179 supports PAL (B/D/G/H/I/M/N) and NTSC (with
and without pedestal) standards. The appropriate SYNC, BLANK,
and burst levels are added to the YCrCb data. Macrovision Anti-
taping (ADV7174 only), closed-captioning, and Teletext levels
are also added to Y and the resultant data is interpolated to a
rate of 27 MHz. The interpolated data is filtered and scaled by
three digital FIR filters.
The U and V signals are modulated by the appropriate subcarrier
sine/cosine phases and added together to make up the chromi-
nance signal. The luma (Y) signal can be delayed 1–3 luma
cycles (each cycle is 74 ns) with respect to the chroma signal.
The luma and chroma signals are then added together to make
up the composite video signal. All edges are slew rate limited.
The YCrCb data is also used to generate RGB data with
appropriate SYNC and BLANK levels. The RGB data is in
synchronization with the composite video output. Alternatively,
analog YPbPr data can be generated instead of RGB data.
The three l0-bit DACs can be used to output: Composite Video + Composite Video S-Video + Composite Video YPrPb Video SCART RGB Video
Alternatively, each DAC can be individually powered off if not
required.
Video output levels are illustrated in Appendix 6.
INTERNAL FILTER RESPONSE The Y filter supports several different frequency responses,
including two low-pass responses, two notch responses, an
extended (SSAF) response, a CIF response, and a QCIF
response. The UV filter supports several different frequency
responses, including four low-pass responses, a CIF response,
and a QCIF response. These can be seen in Table 7 and Table 8
and Figure 6 to Figure 18.
Table 7. Luminance Internal Filter Specifications
Table 8. Chrominance Internal Filter Specifications TYPICAL PERFORMANCE CHARACTERISTICS
FREQUENCY (MHz)
MAGNITUDE
(dB)
–70Figure 6. Chrominance Internal Filter Specifications
FREQUENCY (MHz)
MAGNITUDE
(dB)
–70Figure 7. PAL Low-Pass Luma Filter
FREQUENCY (MHz)
MAGNITUDE
(dB)
–70Figure 8. NTSC Notch Luma Filter
FREQUENCY (MHz)
MAGNITUDE
(dB)
–70Figure 9. PAL Notch Luma Filter
FREQUENCY (MHz)
MAGNITUDE
(dB)
–70Figure 10. Extended Mode (SSAF) Luma Filter
FREQUENCY (MHz)
MAGNITUDE
(dB)
–70Figure 11. CIF Luma Filter
FREQUENCY (MHz)
MAGNITUDE
(dB)
–70Figure 12. QCIF Luma Filter
FREQUENCY (MHz)
MAGNITUDE
(dB)
–70Figure 13. 1.3 MHz Low-Pass Chroma Filter
FREQUENCY (MHz)
MAGNITUDE
(dB)
–70Figure 14. 0.65 MHz Low-Pass Chroma Filter
FREQUENCY (MHz)
MAGNITUDE
(dB)
–70Figure 15. 1.0 MHz Low-Pass Chroma Filter
FREQUENCY (MHz)
MAGNITUDE
(dB)
–70Figure 16. 2.0 MHz Low-Pass Chroma Filter
FREQUENCY (MHz)
MAGNITUDE
(dB)
–70Figure 17. CIF Chroma Filter
FREQUENCY (MHz)
MAGNITUDE
(dB)
–70Figure 18. QCIF Chroma Filter
FEATURES
COLOR BAR GENERATION The ADV7174/ADV7179 can be configured to generate 100/
7.5/75/7.5 color bars for NTSC or 100/0/75/0 for PAL color
bars. These are enabled by setting MR17 of Mode Register 1 to
Logic 1.
SQUARE PIXEL MODE The ADV7174/ADV7179 can be used to operate in square pixel
mode. For NTSC operation, an input clock of 24.5454 MHz is
required. Alternatively, for PAL operation, an input clock of
29.5 MHz is required. The internal timing logic adjusts accord-
ingly for square pixel mode operation.
COLOR SIGNAL CONTROL The color information can be switched on and off the video
output using Bit MR24 of Mode Register 2.
BURST SIGNAL CONTROL The burst information can be switched on and off the video
output using Bit MR25 of Mode Register 2.
NTSC PEDESTAL CONTROL The pedestal on both odd and even fields can be controlled on a
line-by-line basis using the NTSC pedestal control registers.
This allows the pedestals to be controlled during the vertical
blanking interval.
PIXEL TIMING DESCRIPTION The ADV7174/ADV7179 operates in an 8-bit YCrCb mode.
8-Bit YCrCb Mode This default mode accepts multiplexed YCrCb inputs through
the P7–P0 pixel inputs. The inputs follow the sequence Cb0, Y0
Cr0, Y1, Cb1, Y2, and so on. The Y, Cb, and Cr data are input on
a rising clock edge.
SUBCARRIER RESET Together with the SCRESET/RTC pin and Bits MR22 and
MR21 of Mode Register 2, the ADV7174/ADV7179 can be used
in subcarrier reset mode. The subcarrier resets to Field 0 at the
start of the following field when a low-to-high transition occurs
on this input pin.
REAL-TIME CONTROL Together with the SCRESET/RTC pin and Bits MR22 and MR21
of Mode Register 2, the ADV7174/ADV7179 can be used to
lock to an external video source. The real-time control mode
allows the ADV7174/ADV7179 to automatically alter the
subcarrier frequency to compensate for line length variation.
When the part is connected to a device that outputs a digital
data stream in the RTC format (such as a ADV7183A video
decoder; see Figure 19), the part automatically changes to the
compensated subcarrier frequency on a line-by-line basis. This
digital data stream is 67 bits wide and the subcarrier is contained
in Bits 0 to 21. Each bit is two clock cycles long. 00H should be
written into all four subcarrier frequency registers when using
this mode.
Video Timing Description The ADV7174/ADV7179 is intended to interface with off-the-
shelf MPEG1 and MPEG2 decoders. Consequently, the
ADV7174/ADV7179 accepts 4:2:2 YCrCb pixel data via a
CCIR-656 pixel port and has several video timing modes of
operation that allow it to be configured as either a system
master video timing generator or as a slave to the system video
timing generator. The ADV7174/ADV7179 generates all of the
required horizontal and vertical timing periods and levels for
the analog video outputs.
The ADV7174/ADV7179 calculates the width and placement of
analog sync pulses, blanking levels, and color burst envelopes.
Color bursts are disabled on appropriate lines, and serration and
equalization pulses are inserted where required.
In addition, the ADV7174/ADV7179 supports a PAL or NTSC
square pixel operation in slave mode. The part requires an input
pixel clock of 24.5454 MHz for NTSC and an input pixel clock
of 29.5 MHz for PAL. The internal horizontal line counters
place the various video waveform sections into the correct
location for the new clock frequencies.
The ADV7174/ADV7179 has four distinct master and four
distinct slave timing configurations. Timing control is
established with the bidirectional HSYNC, BLANK, and
FIELD/VSYNC pins. Timing Mode Register 1 can also be used
to vary the timing pulse widths and where they occur in
relation to each other.
COMPOSITE
VIDEO
(e.g., VCR
OR CABLE)
H/LTRANSITION
COUNT START4 BITS
RESERVED
5 BITS
RESERVED
RESET
BIT3
SEQUENCE
BIT2RESERVED146768
NOT USED IN THE
ADV7174/ADV7179
VALID
SAMPLE
INVALID
SAMPLE
FSCPLL INCREMENT1
8/LLC
NOTES
1FSCPLL INCREMENT IS 22 BITS LONG, VALUE LOADED INTO ADV7174/ADV7179 FSC DDS REGISTER IS
FSCPLL INCREMENT BITS 21:0 PLUS BITS 0:9 OF THE SUBCARRIER FREQUENCY REGISTERS. ALL ZEROS SHOULD
BE WRITTEN TO THE SUBCARRIER FREQUENCY REGISTERS OF THE ADV7174/ADV7179.
2SEQUENCE BIT
PAL: 0 = LINE NORMAL, 1 = LINE INVERTED
NTSC: 0 = NO CHANGE
3RESET BIT
RESET ADV7174/ADV7179 DDS02980-A
Figure 19. RTC Timing and Connections
Vertical Blanking Data Insertion It is possible to allow encoding of incoming YCbCr data on
those lines of VBI that do not bear line sync or pre-/post-
equalization pulses (see Figure 21 to Figure 32). This mode of
operation is called partial blanking and is selected by setting
MR32 to 1. It allows the insertion of any VBI data (opened VBI)
into the encoded output waveform. This data is present in the
digitized incoming YCbCr data stream, for example. WSS data,
CGMS, VPS, and so on. Alternatively, the entire VBI may be
blanked (no VBI data inserted) on these lines by setting MR32
to 0.
Mode 0 (CCIR-656): Slave Option
(Timing Register 0 TR0 = X X X X X 0 0 0) The ADV7174/ADV7179 is controlled by the SAV (start active
video) and EAV (end active video) time codes in the pixel data.
All timing information is transmitted using a 4-byte synchro-
nization pattern. A synchronization pattern is sent immediately
before and after each line during active picture and retrace.
Mode 0 is illustrated in Figure 20. The HSYNC, FIELD/VSYNC,
and BLANK (if not used) pins should be tied high during this
mode.
Mode 0 (CCIR-656): Master Option
(Timing Register 0 TR0 = X X X X X 0 0 1) The ADV7174/ADV7179 generates H, V, and F signals required
for the SAV and EAV time codes in the CCIR-656 standard. The
H bit is output on the HSYNC pin, the V bit is output on the
BLANK pin, and the F bit is output on the FIELD/VSYNC pin.
Mode 0 is illustrated in Figure 21 (NTSC) and Figure 22 (PAL).
The H, V, and F transitions relative to the video waveform are
illustrated in Figure 23.
END OF ACTIVE
VIDEO LINE
START OF ACTIVE
VIDEO LINE
NTSC/PAL M SYSTEM
(525 LlNES/60Hz)
(625 LINES/50Hz)02980-A
Figure 20. Timing Mode 0 (Slave Mode)
Figure 21. Timing Mode 0 (NTSC Master Mode)
DISPLAY
DISPLAY
31302980-A
Figure 22. Timing Mode 0 (PAL Master Mode)
Figure 23. Timing Mode 0 Data Transitions (Master Mode)
Mode 1: Slave Option HSYNC, BLANK, FIELD
(Timing Register 0 TR0 = X X X X X 0 1 0) In this mode, the ADV7174/ADV7179 accepts horizontal SYNC
and odd/even FIELD signals. A transition of the FIELD input
when HSYNC is low indicates a new frame, i.e., vertical retrace.
The BLANK signal is optional. When the BLANK input is
disabled, the ADV7174/ADV7179 automatically blanks all
normally blank lines as per CCIR-624. Mode 1 is illustrated in
Figure 24 (NTSC) and Figure 25 (PAL).
FIELD
HSYNC
BLANK
FIELDFigure 24. Timing Mode 1 (NTSC)
HSYNC
BLANK
FIELD
DISPLAY
HSYNC
BLANK
FIELD
320
Mode 1: Master Option HSYNC, BLANK, FIELD
(Timing Register 0 TR0 = X X X X X 0 1 1) In this mode, the ADV7174/ADV7179 can generate horizontal
SYNC and odd/even FIELD signals. A transition of the FIELD
input when HSYNC is low indicates a new frame, i.e., vertical
retrace. The BLANK signal is optional. When the BLANK input
is disabled, the ADV7174/ADV7179 automatically blanks all
normally blank lines as per CCIR-624. Pixel data is latched on
the rising clock edge following the timing signal transitions.
Mode 1 is illustrated in Figure 24 (NTSC) and Figure 25 (PAL).
Figure 26 illustrates the HSYNC, BLANK, and FIELD for an
odd or even field transition relative to the pixel data.
FIELD
PIXEL
DATA
PAL = 132×CLOCK/2
NTSC = 122×CLOCK/2
HSYNC
BLANK02980-A
Figure 26. Timing Mode 1 Odd/Even Field Transitions Master/Slave
Mode 2: Slave Option HSYNC, VSYNC, BLANK
(Timing Register 0 TR0 = X X X X X 1 0 0) In this mode, the ADV7174/ADV7179 accepts horizontal and
vertical SYNC signals. A coincident low transition of both and
VSYNC inputs indicates the start of an odd field. A VSYNC low
transition when HSYNC is high indicates the start of an even
field. The BLANK signal is optional. When the BLANK input is
disabled, the ADV7174/ADV7179 automatically blanks all
normally blank lines as per CCIR-624. Mode 2 is illustrated in
Figure 27 (NTSC) and Figure 28 (PAL).
HSYNC
BLANK
VSYNC
HSYNC
BLANK
VSYNCFigure 27. Timing Mode 2 (NTSC)
DISPLAY
HSYNC
BLANK
VSYNC
Mode 2: Master Option HSYNC, VSYNC, BLANK
(Timing Register 0 TR0 = X X X X X 1 0 1) In this mode, the ADV7174/ADV7179 can generate horizontal
and vertical SYNC signals. A coincident low transition of both
HSYNC and VSYNC inputs indicates the start of an odd field. A
VSYNC low transition when HSYNC is high indicates the start
of an even field. The BLANK signal is optional. When the
BLANK input is disabled, the ADV7174/ADV7179 automatically
blanks all normally blank lines as per CCIR-624. Mode 2 is
illustrated in Figure 27 (NTSC) and Figure 28 (PAL). Figure 29
illustrates the HSYNC, BLANK, and VSYNC for an even-to-odd
field transition relative to the pixel data. Figure 30 illustrates the
HSYNC, BLANK, and VSYNC for an odd-to-even field
transition relative to the pixel data.
HSYNC
VSYNC
BLANK
PIXEL
DATA02980-A
Figure 29. Timing Mode 2 Even-to-Odd Field Transition Master/Slave
VSYNC
PIXEL
DATA
HSYNC
BLANKFigure 30. Timing Mode 2 Odd-to-Even Field Transition Master/Slave
Mode 3: Master/Slave Option HSYNC, BLANK, FIELD
(Timing Register 0 TR0 = X X X X X 1 1 0 or X X X X X 1 1 1) In this mode, the ADV7174/ADV7179 accepts or generates
horizontal SYNC and odd/even FIELD signals. A transition of
the FIELD input when HSYNC is high indicates a new frame,
that is, vertical retrace. The BLANK signal is optional. When the
BLANK input is disabled, the ADV7174/ADV7179 automatically
blanks all normally blank lines as per CCIR-624. Mode 3 is
illustrated in Figure 31 (NTSC) and Figure 32 (PAL).
FIELD
HSYNC
BLANK
FIELD02980-A
Figure 31. Timing Mode 3 (NTSC)
DISPLAY
BLANK
FIELD
DISPLAY
HSYNC
BLANK
HSYNC-031
POWER-ON RESET After power-up, it is necessary to execute a reset operation. A
reset occurs on the falling edge of a high-to-low transition on
the RESET pin. This initializes the pixel port so that the pixel
inputs, P7–P0, are selected. After reset, the ADV7174/ADV7179
is automatically set up to operate in NTSC mode. Subcarrier
frequency code 21F07C16H is loaded into the subcarrier
frequency registers. All other registers, with the exception of
Mode Register 0, are set to 00H. With the exception of Bit MR44,
all bits in Mode Register 0 are set to Logic 0. Bit MR44 of Mode
Register 4 is set to Logic 1. This enables the 7.5 IRE pedestal.
SCH PHASE MODE The SCH phase is configured in default mode to reset every
four (NTSC) or eight (PAL) fields to avoid an accumulation of
SCH phase error over time. In an ideal system, 0 SCH phase
error would be maintained forever, but in reality, this is impossi-
ble to achieve due to clock frequency variations. This effect is
reduced by the use of a 32-bit DDS, which generates this SCH.
Resetting the SCH phase every four or eight fields avoids the
accumulation of SCH phase error and results in very minor
SCH phase jumps at the start of the 4- or 8-field sequence.
Resetting the SCH phase should not be done if the video source
does not have stable timing or the ADV7174/ADV7179 is
configured in RTC mode (MR21 = 1 and MR22 = 1). Under
these conditions (unstable video), the subcarrier phase reset
should be enabled (MR22 = 0 and MR21 = 1), but no reset
applied. In this configuration, the SCH phase can never be reset,
which means that the output video can now track the unstable
input video. The subcarrier phase reset, when applied, resets the
SCH phase to Field 0 at the start of the next field, for example,
subcarrier phase reset applied in Field 5 (PAL) on the start of
the next field SCH phase is reset to Field 0.
MPU PORT DESCRIPTION The ADV7174/ADV7179 supports a 2-wire serial (I2C
compatible) microprocessor bus driving multiple peripherals.
Two inputs, serial data (SDATA) and serial clock (SCLOCK),
carry information between any device connected to the bus.
Each slave device is recognized by a unique address. The
ADV7174/ADV7179 has four possible slave addresses for both
read and write operations. These are unique addresses for each
device and are illustrated in Figure 33 and Figure 34. The LSB
sets either a read or write operation. Logic 1 corresponds to a
read operation, while Logic 0 corresponds to a write operation.
A 1 is set by setting the ALSB pin of the ADV7174/ ADV7179 to
Logic 0 or Logic 1.
Figure 33. ADV7174 Slave Address
Figure 34. ADV7179 Slave Address
To control the various devices on the bus, the following protocol
must be followed: first, the master initiates a data transfer by
establishing a start condition, defined by a high-to-low transition
on SDATA while SCLOCK remains high. This indicates that an
address/data stream will follow. All peripherals respond to the
start condition and shift the next eight bits (7-bit address + R/W
bit). The bits transfer from MSB down to LSB. The peripheral
that recognizes the transmitted address responds by pulling the
data line low during the ninth clock pulse. This is known as an
Acknowledge bit. All other devices withdraw from the bus at
this point and maintain an idle condition. The idle condition is
where the device monitors the SDATA and SCLOCK lines wait-
ing for the start condition and the correct transmitted address.
The R/W bit determines the direction of the data. A Logic 0 on
the LSB of the first byte means that the master will write infor-
mation to the peripheral. A Logic 1 on the LSB of the first byte
means that the master will read information from the peripheral.
The ADV7174/ADV7179 acts as a standard slave device on the
bus. The data on the SDATA pin is eight bits long, supporting
the 7-bit addresses plus the R/W bit. The ADV7174/ADV7179
has 26 subaddresses to enable access to the internal registers. It
therefore interprets the first byte as the device address and the
second byte as the starting subaddress. The subaddresses’ auto
increment allows data to be written to or read from the starting
subaddress. A data transfer is always terminated by a stop
condition. The user can also access any unique subaddress
register on a one-by-one basis without having to update all the
registers. There is one exception. The subcarrier frequency
registers should be updated in sequence, starting with
Subcarrier Frequency Register 0. The auto increment function
should then be used to increment and access Subcarrier
Stop and start conditions can be detected at any stage during the
data transfer. If these conditions are asserted out of sequence with
normal read and write operations, they cause an immediate
jump to the idle condition. During a given SCLOCK high period,
the user should issue only one start condition, one stop condition,
or a single stop condition followed by a single start condition. If
an invalid subaddress is issued by the user, the ADV7174/
ADV7179 cannot issue an acknowledge and returns to the idle
condition. If in auto-increment mode the user exceeds the
highest subaddress, the following action is taken:
1. In read mode, the highest subaddress register contents
continues to be output until the master device issues a no-
acknowledge. This indicates the end of a read. A no-
acknowledge condition is when the SDATA line is not
pulled low on the ninth pulse.
2. In write mode, the data for the invalid byte is not loaded
into any subaddress register, a no-acknowledge is issued by
the ADV7174/ADV7179, and the part returns to the idle
condition.
Figure 35 illustrates an example of data transfer for a read
sequence and the start and stop conditions.
Figure 36 shows bus write and read sequences.
STARTADDRR/WACKSUBADDRESSACKDATAACKSTOP
SDATA
SCLOCK02980-A-034
Figure 35. Bus Data Transfer
REGISTER ACCESSES The MPU can write to or read from all of the ADV7174/
ADV7179 registers except the subaddress register, which is a
write-only register. The subaddress register determines which
register the next read or write operation accesses. All commu-
nications with the part through the bus start with an access to
the subaddress register. A read/write operation is performed
from to the target address, which then increments to the next
address until a stop command on the bus is performed.
WRITE
SEQUENCE
READ
SEQUENCE
A(S) = NO-ACKNOWLEDGE BY SLAVE
A(M) = NO-ACKNOWLEDGE BY MASTER
A(S) = ACKNOWLEDGE BY SLAVE
A(M) = ACKNOWLEDGE BY MASTER
S = START BIT
P = STOP BIT02980-A
Figure 36. Write and Read Sequences
