ADV7176AKSZ ,Digital CCIR-601 to PAL/NTSC Video Encoder with 4x10-Bit DACs and Teletext InsertionGENERAL DESCRIPTIONProgrammable VBI (Vertical Blanking Interval)The ADV7175A/ADV7176A is an integra ..
ADV7176KS ,Integrated Digital CCIR-601 YCrCb to PAL/NTSC Video EncoderSPECIFICATIONS T to T unless otherwise noted)MIN MAXModel ADV7175/ADV71761Parameter Conditions ..
ADV7177KS ,Integrated Digital CCIR-601 to PAL/NTSC Video EncoderGENERAL DESCRIPTION(VHS) Y/C or RGB (SCART)/YUV Video OutputsThe ADV7177/ADV7178 is an integrated d ..
ADV7177KSZ ,Digital CCIR-601 to PAL/NTSC Video Encoder with 3x9-Bit DACsGENERAL DESCRIPTIONProgrammable Luma Filters (Low-Pass/Notch/Extended)The ADV7177/ADV7178 is an int ..
ADV7177KSZ ,Digital CCIR-601 to PAL/NTSC Video Encoder with 3x9-Bit DACsspecifications T to T unless otherwise noted.)AA REF SET MIN MAX1Parameter Conditions Min Typ Max U ..
ADV7178KS ,Integrated Digital CCIR-601 to PAL/NTSC Video EncoderFEATURES Programmable Subcarrier Frequency and PhaseITU-R BT601/656 YCrCb to PAL/NTSC Video Encoder ..
AM27C512-90DE , 512 Kilobit ( 64 K x 8-Bit ) CMOS EPROM Speed options as fast as 55 ns
AM27C512-90DI , 512 Kilobit ( 64 K x 8-Bit ) CMOS EPROM Speed options as fast as 55 ns
AM27C512-90PC , 512 Kilobit ( 64 K x 8-Bit ) CMOS EPROM Speed options as fast as 55 ns
AM27C64 , 64 Kilobit (8 K x 8-Bit) CMOS EPROM
AM27C64-120DE , 64 Kilobit (8 K x 8-Bit) CMOS EPROM
AM27C64-120DI , 64 Kilobit (8 K x 8-Bit) CMOS EPROM
ADV7176AKSZ
Digital CCIR-601 to PAL/NTSC Video Encoder with 4x10-Bit DACs and Teletext Insertion
REV.C
High Quality, 10-Bit, Digital CCIR-601
to PAL/NTSC Video Encoder
FUNCTIONAL BLOCK DIAGRAM
FEATURES
ITU-R BT601/656 YCrCb to PAL/NTSC Video Encoder
High Quality 10-Bit Video DACs
Integral Nonlinearity <1 LSB at 10 Bits
NTSC-M, PAL-M/N, PAL-B/D/G/H/I
Single 27 MHz Clock Required (�2 Oversampling)
80 dB Video SNR
32-Bit Direct Digital Synthesizer for Color Subcarrier
Multistandard Video Output Support:
Composite (CVBS)
Component S-Video (Y/C)
Component YUV and RGB
EuroSCART Output (RGB + CVBS/LUMA)
Video Input Data Port Supports:
CCIR-656 4:2:2 8-Bit Parallel Input Format
4:2:2 16-Bit Parallel Input Format
Full Video Output Drive or Low Signal Drive Capability
34.7 mA max into 37.5 � (Doubly-Terminated 75R)
5 mA min with External Buffers
Programmable Simultaneous Composite
and S-Video Y/C or RGB (SCART)/YUV Video Outputs
Programmable Luma Filters (Low-Pass/Notch/Extended)
Programmable VBI (Vertical Blanking Interval)
Programmable Subcarrier Frequency and Phase
Programmable LUMA Delay
Individual ON/OFF Control of Each DAC
CCIR and Square Pixel Operation
Integrated Subcarrier Locking to External Video Source
Color Signal Control/Burst Signal Control
Interlaced/Noninterlaced Operation
Complete On-Chip Video Timing Generator
Programmable Multimode Master/Slave Operation
Macrovision Antitaping Rev 7.01 (ADV7175A Only)**
Closed Captioning Support
Teletext Insertion Port (PAL-WST)
Onboard Color Bar Generation
Onboard Voltage Reference
2-Wire Serial MPU Interface (I2C Compatible)
Single Supply 5 V or 3 V Operation
Small 44-Lead MQFP Thermally Enhanced Package
APPLICATIONS
MPEG-1 and MPEG-2 Video, DVD, Digital Satellite/
Cable Systems (Set Top Boxes/IRDs), Digital TVs,
CD Video/Karaoke, Video Games, PC Video/Multimedia *. patents numbers 5,343,196 and 5,442,355 and other intellectual property rights.
**This device is protected by U.S. Patent Numbers 4631603, 4577216, 4819098 and other intellectual property rights. The Macrovision anticopy process is
licensed for noncommercial home use only, which is its sole intended use in the device. Please contact sales office for latest Macrovision version available.
NOTE: ITU-R and CCIR are used interchangeably in this document (ITU-R has replaced CCIR recommendations).
(Continued on page 11)
GENERAL DESCRIPTIONThe ADV7175A/ADV7176A is an integrated digital video encoder
that converts Digital CCIR-601 4:2:2 8 or 16-bit component
video data into a standard analog baseband television signal
ADV7175A/ADV7176A–SPECIFICATIONS
(VAA = 5 V � 5%1, VREF = 1.235 V, RSET = 150 �. All specifications TMIN to TMAX2 unless otherwise noted)STATIC PERFORMANCE
NOTESThe max/min specifications are guaranteed over this range. The max/min values are typical over 4.75 V to 5.25 V.Temperature range TMIN to TMAX: 0°C to 70°C.All digital input pins except pins RESET and RTC/SCRESET.Excluding all digital input pins except pins RESET and RTC/SCRESET.Full drive into 37.5Ω load.Minimum drive current (used with buffered/scaled output load).Power measurements are taken with Clock Frequency = 27 MHz. Max TJ = 110°C.IDAC is the total current (min corresponds to 5 mA output per DAC, max corresponds to 37 mA output per DAC) to drive all four DACs. Turning off individual
DACs reduces IDAC correspondingly.ICCT (Circuit Current) is the continuous current required to drive the device.
Specifications subject to change without notice.
5 V SPECIFICATIONS
ADV7175A/ADV7176ASTATIC PERFORMANCE
NOTESThe max/min specifications are guaranteed over this range. The max/min values are typical over 3.0 V to 3.6 V.Temperature range TMIN to TMAX: 0°C to 70°C. Guaranteed by characterization.All digital input pins except pins RESET and RTC/SCRESET.Excluding all digital input pins except pins RESET and RTC/SCRESET.Full drive into 37.5Ω load.DACs can output 35 mA typically at 3.3 V (RSET = 150 Ω and RL = 75 Ω), optimum performance obtained at 18 mA DAC current (RSET = 300 Ω and RL = 150 Ω.Minimum drive current (used with buffered/scaled output load).Power measurements are taken with Clock Frequency = 27 MHz. Max TJ = 110°C.IDAC is the total current (min corresponds to 5 mA output per DAC, max corresponds to 38 mA output per DAC) to drive all four DACs. Turning off individual
DACs reduces IDAC correspondingly.ICCT (Circuit Current) is the continuous current required to drive the device.
Specifications subject to change without notice.
3.3 V SPECIFICATIONS(VAA = 3.0 V–3.6 V1, VREF = 1.235 V, RSET = 300 �. All specifications TMIN to TMAX2 unless otherwise noted)
ADV7175A/ADV7176A–SPECIFICATIONSFilter Characteristics
Luma Bandwidth
SNR
SNR
SNR
Hue Accuracy
Color Saturation Accuracy
Chroma Nonlinear Gain
Chroma/Luma Delay Ineq
Luminance Nonlinearity
Chroma AM Noise
NOTESThe max/min specifications are guaranteed over this range. The max/min values are typical over 4.75 V to 5.25 V.Temperature range TMIN to TMAX: 0°C to 70°C.These specifications are for the low-pass filter only and guaranteed by design. For other internal filters, see Figure 4.Guaranteed by characterization.
Specifications subject to change without notice.
5 V DYNAMIC SPECIFICATIONS1(VAA = 4.75 V–5.25 V1, VREF = 1.235 V, RSET = 150 �. All specifications TMIN to TMAX2
unless otherwise noted.)
ADV7175A/ADV7176AFilter Characteristics
Luma Bandwidth
SNR
SNR
SNR
Hue Accuracy
Color Saturation Accuracy
Luminance Nonlinearity
NOTESThe max/min specifications are guaranteed over this range. The max/min values are typical over 3.0 V to 3.6 V.Temperature range TMIN to TMAX: 0°C to 70°C.These specifications are for the low-pass filter only and guaranteed by design. For other internal filters, see Figure 4.Guaranteed by characterization.
Specifications subject to change without notice.
3.3 V DYNAMIC SPECIFICATIONS1(VAA = 3.0 V–3.6 V1, VREF = 1.235 V, RSET = 300 �. All specifications TMIN to TMAX2
unless otherwise noted.)
ADV7175A/ADV7176A
5 V TIMING SPECIFICATIONS
(VAA = 4.75 V–5.25 V1, VREF = 1.235 V, RSET = 150 �. All specifications TMIN to TMAX2 unless
otherwise noted.)TELETEXT PORT
RESET CONTROL
NOTESThe max/min specifications are guaranteed over this range.Temperature range TMIN to TMAX: 0°C to 70°C.TTL input values are 0 to 3 volts, with input rise/fall times ≤ 3 ns, measured between the 10% and 90% points. Timing reference points at 50% for inputs and
outputs. Analog output load ≤ 10 pF.Guaranteed by characterization.Output delay measured from the 50% point of the rising edge of CLOCK to the 50% point of full-scale transition.Pixel Port consists of the following:
Pixel Inputs:P15–P0
Pixel Controls:HSYNC, FIELD/VSYNC, BLANK
Clock Input:CLOCKTeletext Port consists of the following:
Teletext Output:TTXREQ
Teletext Input:TTX
Specifications subject to change without notice.
ADV7175A/ADV7176A
3.3 V TIMING SPECIFICATIONS
(VAA = 3.0–3.61, VREF = 1.235 V, RSET = 300 �. All specifications TMIN to TMAX2 unless
otherwise noted.)TELETEXT PORT
RESET CONTROL
NOTESThe max/min specifications are guaranteed over this range.Temperature range TMIN to TMAX: 0oC to 70oC.TTL input values are 0 to 3 volts, with input rise/fall times ≤ 3 ns, measured between the 10% and 90% points. Timing reference points at 50% for inputs and
outputs. Analog output load ≤ 10 pF.Guaranteed by characterization.Output delay measured from the 50% point of the rising edge of CLOCK to the 50% point of full-scale transition.Characterized by design.Pixel Port consists of the following:
Pixel Inputs:P15–P0
Pixel Controls:HSYNC, FIELD/VSYNC, BLANK
Clock Input:CLOCKTeletext Port consists of the following:
Teletext Output:TTXREQ
Teletext Input:TTX
Specifications subject to change without notice.
ADV7175A/ADV7176AFigure 1.MPU Port Timing Diagram
Figure 2.Pixel and Control Data Timing Diagram
Figure 3.Teletext Timing Diagram
ABSOLUTE MAXIMUM RATINGS1VAA to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
Voltage on Any Digital Input Pin . GND – 0.5 V to VAA + 0.5 V
Storage Temperature (TS) . . . . . . . . . . . . . . –65°C to +150°C
Junction Temperature (TJ) . . . . . . . . . . . . . . . . . . . . . . 150°C
Lead Temperature (Soldering, 10 secs) . . . . . . . . . . . . 260°C
Analog Outputs to GND2 . . . . . . . . . . . . . GND – 0.5 to VAA
NOTESStresses above those listed under Absolute Maximum Ratings may cause permanent
damage to the device. This is a stress rating only; functional operation of the device
at these or any other conditions above those listed in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.Analog output short circuit to any power supply or common can be of an indefinite
duration.
ORDERING GUIDE
CAUTIONESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the ADV7175A/ADV7176A feature proprietary ESD protection circuitry, permanent
damage may occur on devices subjected to high-energy electrostatic discharges. Therefore,
proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
PIN CONFIGURATION
PACKAGE THERMAL PERFORMANCEThe 44-MQFP package used for this device takes advantage of
an ADI patented thermal coastline lead frame construction.
This maximizes heat transfer into the leads and reduces the
package thermal resistance.
The junction-to-ambient (θJA) thermal resistance in still air on a
four-layer PCB is 35.5°C/W. The junction-to-case thermal
resistance (θJC) is 13.75°C/W.
ADV7175A/ADV7176A
PIN FUNCTION DESCRIPTIONS2–9, 12–14
compatible with worldwide standards. The 4:2:2 YUV video
data is interpolated to two times the pixel rate. The color-
difference components (UV) are quadrature modulated using
a subcarrier frequency generated by an on-chip 32-bit digital
synthesizer (also running at two times the pixel rate). The two
times pixel rate sampling allows for better signal-to-noise-ratio.
A 32-bit DDS with a 10-bit look-up table produces a superior
subcarrier in terms of both frequency and phase. In addition to
the composite output signal, there is the facility to output S-
Video (Y/C) video, YUV or RGB video. The Y/C, YUV or RGB
format is simultaneously available at the analog outputs with the
composite video signal.
Each analog output is capable of driving the full video-level
(35 mA) signal into an unbuffered, doubly terminated 75 Ω
load. With external buffering, the user has the additional option
to scale back the DAC output current to 5 mA min, thereby signifi-
cantly reducing the power dissipation of the device.
The ADV7175A/ADV7176A also supports both PAL and NTSC
square pixel operation.
The output video frames are synchronized with the incoming
data timing reference codes. Optionally the encoder accepts
(and can generate) HSYNC, VSYNC and FIELD timing signals.
These timing signals can be adjusted to change pulsewidth and
position while the part is in the master mode. The encoder
requires a single two times pixel rate (27 MHz) clock for standard
operation. Alternatively, the encoder requires a 24.5454 MHz
clock for NTSC or 29.5 MHz clock for PAL square pixel
mode operation. All internal timing is generated on-chip.
A separate teletext port enables the user to directly input teletext
data during the vertical blanking interval.
The ADV7175A/ADV7176A modes are set up over a two-wire
serial bidirectional port (I2C Compatible) with two slave addresses.
Functionally the ADV7175A and ADV7176A are the same with
the exception that the ADV7175A can output the Macrovision
anticopy algorithm.
The ADV7175A/ADV7176A is packaged in a 44-lead thermally
enhanced MQFP package.
DATA PATH DESCRIPTIONFor PAL B, D, G, H, I, M, N and NTSC M modes, YCrCb
4:2:2 data is input via the CCIR-656 compatible pixel port at a
27 MHz Data Rate. The pixel data is demultiplexed to from
three data paths. Y typically has a range of 16 to 235, Cr and
Cb typically have a range of 128 ± 112; however, it is pos-
sible to input data from 1 to 254 on both Y, Cb and Cr. The
ADV7175A/ADV7176A supports PAL (B, D, G, H, I, N, M)
and NTSC (with and without Pedestal) standards. The appropri-
ate SYNC, BLANK and Burst levels are added to the YCrCb
data. Macrovision antitaping (ADV7175A only), closed caption-
ing and teletext levels are also added to Y, and the resultant
data is interpolated to a rate of 27 MHz. The interpolated data
is filtered and scaled by three digital FIR filters.
The U and V signals are modulated by the appropriate subcarrier
sine/cosine phases and added together to make up the chromi-
nance signal. The luma (Y) signal can be delayed 1–3 luma
cycles (each cycle is 74 ns) with respect to the chroma signal.
The luma and chroma signals are then added together to make
up the composite video signal. All edges are slew rate limited.
The YCrCb data is also used to generate RGB data with
appropriate SYNC and BLANK levels. The RGB data is in
synchronization with the composite video output. Alternatively
analog YUV data can be generated instead of RGB.
The four 10-bit DACs can be used to output:Composite Video + RGB Video.Composite Video + YUV VideoTwo Composite Video Signals + LUMA and CHROMA(Y/C) Signals.
Alternatively, each DAC can be individually powered off if
not required.
Video output levels are illustrated in Appendix 4 and Appendix5.
INTERNAL FILTER RESPONSEThe Y filter supports several different frequency responses,
including two 4.5 MHz/5.0 MHz low pass responses, PAL/
NTSC subcarrier notch responses and a PAL/NTSC extended
response. The U and V filters have a 2/2.4 MHz low-pass
response for NTSC/PAL. These filter characteristics are illus-
trated in Figures 4 to 12.
Figure 4.Luminance Internal Filter Specifications
(Continued from page 1)
ADV7175A/ADV7176AFigure 6.NTSC Low-Pass Filter
Figure 7.NTSC Notch Filter
Figure 8.PAL Low-Pass Filter
Figure 9.PAL Notch Filter
Figure 10.NTSC/PAL Extended Mode Filter
Figure 11.NTSC UV Filter
COLOR BAR GENERATIONThe ADV7175A/ADV7176A can be configured to generate
100/7.5/75/7.5 for NTSC color bars or 100/0/75/0 for PAL
color bars. These are enabled by setting MR17 of Mode Reg-
ister 1 to Logic “1.”
SQUARE PIXEL MODEThe ADV7175A/ADV7176A can be used to operate in square
pixel mode. For NTSC operation an input clock of 24.5454 MHz
is required. Alternatively an input clock of 29.5 MHz is required
for PAL operation. The internal timing logic adjusts accordingly
for square pixel mode operation.
COLOR SIGNAL CONTROLThe color information can be switched on and off the video
output using Bit MR24 of Mode Register 2.
BURST SIGNAL CONTROLThe burst information can be switched on and off the video
output using Bit MR25 of Mode Register 2.
NTSC PEDESTAL CONTROLThe pedestal on both odd and even fields can be controlled on a
line-by-line basis using the NTSC Pedestal Control Registers.
This allows the pedestals to be controlled during the vertical
blanking interval (Lines 10 to 25 and Lines 273 to 288).
PIXEL TIMING DESCRIPTIONThe ADV7175A/ADV7176A can operate in either 8-bit or
16-bit YCrCb Mode.
8-Bit YCrCb ModeThis default mode accepts multiplexed YCrCb inputs through
the P7-P0 pixel inputs. The inputs follow the sequence Cb0, Y0
Cr0, Y1 Cb1, Y2, etc. The Y, Cb and Cr data are input on a
rising clock edge.
16-Bit YCrCb ModeThis mode accepts Y inputs through the P7–P0 pixel inputs and
multiplexed CrCb inputs through the P15–P8 pixel inputs. The
data is loaded on every second rising edge of CLOCK. The inputs
follow the sequence Cb0, Y0 Cr0, Y1 Cb1, Y2, etc.
SUBCARRIER RESETTogether with the SCRESET/RTC PIN and Bits MR22 and
MR21 of Mode Register 2, the ADV7175A/ADV7176A can be
used in subcarrier reset mode. The subcarrier will reset to
Field 0 at the start of the following field when a low to high
transition occurs on this input pin.
REAL TIME CONTROLTogether with the SCRESET/RTC PIN and Bits MR22 and
MR21 of Mode Register 2, the ADV7175A/ADV7176A can be
used to lock to an external video source. The real time control
mode allows the ADV7175A/ADV7176A to automatically alter
the subcarrier frequency to compensate for line length variation.
When the part is connected to a device that outputs a digital
datastream in the RTC format (such as an ADV7185 video
decoder [see Figure 13]), the part will automatically change to
the compensated subcarrier frequency on a line by line basis.
This digital datastream is 67 bits wide and the subcarrier is
contained in Bits 0 to 21. Each bit is two clock cycles long.
00HEX should be written to all four subcarrier frequency regis-
ters when using this mode.
VIDEO TIMING DESCRIPTIONThe ADV7175A/ADV7176A is intended to interface to off-
the-shelf MPEG1 and MPEG2 Decoders. Consequently, the
ADV7175A/ADV7176A accepts 4:2:2 YCrCb Pixel Data via a
CCIR-656 pixel port and has several video timing modes of
operation that allow it to be configured as either system master
video timing generator or a slave to the system video timing
generator. The ADV7175A/ADV7176A generates all of the
required horizontal and vertical timing periods and levels for the
analog video outputs.
The ADV7175A/ADV7176A calculates the width and place-
ment of analog sync pulses, blanking levels and color burst
envelopes. Color bursts are disabled on appropriate lines, and
serration and equalization pulses are inserted where required.
In addition the ADV7175A/ADV7176A supports a PAL or
NTSC square pixel operation in slave mode. The part requires
an input pixel clock of 24.5454 MHz for NTSC and an input
pixel clock of 29.5 MHz for PAL. The internal horizontal line
counters place the various video waveform sections in the cor-
rect location for the new clock frequencies.
The ADV7175A/ADV7176A has four distinct master and four
distinct slave timing configurations. Timing Control is estab-
lished with the bidirectional SYNC, BLANK and FIELD/
VSYNC pins. Timing Mode Register 1 can also be used to vary
the timing pulsewidths and where they occur in relation to
each other.
Figure 12.PAL UV Filter
ADV7175A/ADV7176AFigure 13.RTC Timing and Connections
Vertical Blanking Data InsertionIt is possible to allow encoding of incoming YCbCr data on those lines of VBI that do not bear line sync or pre/post-equalization
pulses (see Figures 15 to 26). This mode of operation is called “Partial Blanking” and is selected by setting MR31 to 1. It allows the
insertion of any VBI data (Opened VBI) into the encoded output waveform. This data is present in digitized incoming YCbCr data
stream (e.g., WSS data, CGMS, VPS, etc.). Alternatively, the entire VBI may be blanked (no VBI data inserted) on these lines by
setting MR31 to 0.
Mode 0 (CCIR-656):Slave Option(Timing Register 0 TR0 = X X X X X 0 0 0)
The ADV7175A/ADV7176A is controlled by the SAV (Start Active Video) and EAV (End Active Video) time codes in the pixel
data. All timing information is transmitted using a 4-byte synchronization pattern. A synchronization pattern is sent immediately
before and after each line during active picture and retrace. Mode 0 is illustrated in Figure 14. The HSYNC, FIELD/VSYNC and
BLANK (if not used) pins should be tied high during this mode.
Figure 14.Timing Mode 0 (Slave Mode)
Mode 0 (CCIR-656):Master Option(Timing Register 0 TR0 = X X X X X 0 0 1)
The ADV7175A/ADV7176A generates H, V and F signals required for the SAV (Start Active Video) and EAV (End Active Video)
time codes in the CCIR-656 standard. The H bit is output on the HSYNC pin, the V bit is output on the BLANK pin, and the F bit
is output on the FIELD/VSYNC pin. Mode 0 is illustrated in Figure 15 (NTSC) and Figure 16 (PAL). The H, V and F transitions
relative to the video waveform are illustrated in Figure 17.
Figure 15.Timing Mode 0 (NTSC Master Mode)
ADV7175A/ADV7176AFigure 16.Timing Mode 0 (PAL Master Mode)
Figure 17.Timing Mode 0 Data Transitions (Master Mode)
Mode 1:Slave Option HSYNC, BLANK, FIELD(Timing Register 0 TR0 = X X X X X 0 1 0)
In this mode the ADV7175A/ADV7176A accepts horizontal SYNC and Odd/Even FIELD signals. A transition of the FIELD input
when HSYNC is low indicates a new frame i.e., vertical retrace. The BLANK signal is optional. When the BLANK input is disabled
the ADV7175A/ADV7176A automatically blanks all normally blank lines. Mode 1 is illustrated in Figure 18 (NTSC) and Fig-
ure 19 (PAL).
Figure 18.Timing Mode 1 (NTSC)
Figure 19.Timing Mode 1 (PAL)
ADV7175A/ADV7176A
Mode 1: Master Option HSYNC, BLANK, FIELD(Timing Register 0 TR0 = X X X X X 0 1 1)
In this mode the ADV7175A/ADV7176A can generate horizontal SYNC and Odd/Even FIELD signals. A transition of the FIELD
input when HSYNC is low indicates a new frame i.e., vertical retrace. The BLANK signal is optional. When the BLANK input is
disabled, the ADV7175A/ADV7176A automatically blanks all normally blank lines. Pixel data is latched on the rising clock edge
following the timing signal transitions. Mode 1 is illustrated in Figure 18 (NTSC) and Figure 19 (PAL). Figure 20 illustrates the
HSYNC, BLANK and FIELD for an odd or even field transition relative to the pixel data.
Figure 20.Timing Mode 1 Odd/Even Field Transitions Master/Slave
Mode 2:Slave Option HSYNC, VSYNC, BLANK(Timing Register 0 TR0 = X X X X X 1 0 0)
In this mode the ADV7175A/ADV7176A accepts horizontal and vertical SYNC signals. A coincident low transition of both
HSYNC and VSYNC inputs indicates the start of an odd field. A VSYNC low transition when HSYNC is high indicates the start of
an even field. The BLANK signal is optional. When the BLANK input is disabled, the ADV7175A/ADV7176A automatically blanks
all normally blank lines as per CCIR-624. Mode 2 is illustrated in Figure 21 (NTSC) and Figure 22 (PAL).
Figure 21.Timing Mode 2 (NTSC)
Figure 22.Timing Mode 2 (PAL)
Mode 2:Master Option HSYNC, VSYNC, BLANK(Timing Register 0 TR0 = X X X X X 1 0 1)
In this mode, the ADV7175A/ADV7176A can generate horizontal and vertical SYNC signals. A coincident low transition of both
HSYNC and VSYNC inputs indicates the start of an Odd Field. A VSYNC low transition when HSYNC is high indicates the start of
an even field. The BLANK signal is optional. When the BLANK input is disabled, the ADV7175A/ADV7176A automatically blanks
all normally blank lines as per CCIR-624. Mode 2 is illustrated in Figure 21 (NTSC) and Figure 22 (PAL). Figure 23 illus-
trates the HSYNC, BLANK and VSYNC for an even-to-odd field transition relative to the pixel data. Figure 24 illustrates the
HSYNC, BLANK and VSYNC for an odd-to-even field transition relative to the pixel data.
Figure 23.Timing Mode 2 Even-to-Odd Field Transition Master/Slave
ADV7175A/ADV7176A
Mode 3:Master/Slave Option HSYNC, BLANK, FIELD(Timing Register 0 TR0 = X X X X X 1 1 0 or X X X X X 1 1 1)
In this mode, the ADV7175A/ADV7176A accepts or generates Horizontal SYNC and Odd/Even FIELD signals. A transition of the
FIELD input when HSYNC is high indicates a new frame i.e., vertical retrace. The BLANK signal is optional. When the BLANK
input is disabled, the ADV7175A/ADV7176A automatically blanks all normally blank lines as per CCIR-624. Mode 3 is illustrated in
Figure 25 (NTSC) and Figure 26 (PAL).
Figure 25.Timing Mode 3 (NTSC)
Figure 26.Timing Mode 3 (PAL)
POWER-ON RESETAfter power-up, it is necessary to execute a reset operation. A
reset occurs on the falling edge of a high-to-low transition on
the RESET pin. This initializes the pixel port so that the
pixel inputs, P7–P0 are selected. After reset, the ADV7175A/
ADV7176A is automatically set up to operate in NTSC mode.
Subcarrier frequency code 21F07C16HEX is loaded into the
subcarrier frequency registers. All other registers, with the
exception of Mode Register 0, are set to 00H. All bits in Mode
Register 0 are set to Logic Level “0” except Bit MR02. Bit
MR02 of Mode Register 0 is set to Logic “1.” This enables the
7.5 IRE pedestal.
SCH Phase ModeThe SCH phase is configured in default mode to reset every
four (NTSC) or eight (PAL) fields to avoid an accumulation of
SCH phase error over time. In an ideal system, zero SCH phase
error would be maintained forever, but in reality, this is impos-
sible to achieve due to clock frequency variations. This effect is
reduced by the use of a 32-bit DDS, which generates this SCH.
Resetting the SCH phase every four or eight fields avoids the
accumulation of SCH phase error, and results in very minor
SCH phase jumps at the start of the four or eight field sequence.
Resetting the SCH phase should not be done if the video source
does not have stable timing or the ADV7175A/ADV7176A is
configured in RTC mode (MR21 = 1 and MR22 = 1). Under
these conditions (unstable video) the subcarrier phase reset
should be enabled MR22 = 0 and MR21 = 1) but no reset
applied. In this configuration the SCH phase will never be reset,
which means that the output video will now track the unstable
input video. The subcarrier phase reset, when applied, will reset
the SCH phase to Field 0 at the start of the next field (e.g.,
subcarrier phase reset applied in Field 5 [PAL] on the start of
the next field SCH phase will be reset to Field 0).
MPU PORT DESCRIPTIONThe ADV7175A and ADV7176A support a two-wire serial (I2C
Compatible) microprocessor bus driving multiple peripherals.
Two inputs, serial data (SDATA) and serial clock (SCLOCK),
carry information between any device connected to the bus. Each
slave device is recognized by a unique address. The ADV7175A
and ADV7176A each have four possible slave addresses for both
read and write operations. These are unique addresses for each
device and are illustrated in Figure 27 and Figure 28. The LSB
sets either a read or write operation. Logic Level “1” corre-
sponds to a read operation, while Logic Level “0” corresponds
to a write operation. A1 is set by setting the ALSB pin of the
ADV7175A/ADV7176A to Logic Level “0” or Logic Level “1.”
Figure 27. ADV7175A Slave Address
Figure 28. ADV7176A Slave Address
To control the various devices on the bus, the following proto-
col must be followed: First, the master initiates a data transfer by
establishing a start condition, defined by a high-to-low transition
on SDATA while SCLOCK remains high. This indicates that
an address/data stream will follow. All peripherals respond to
the start condition and shift the next eight bits (7-bit address +
R/W bit). The bits transfer from MSB down to LSB. The
peripheral that recognizes the transmitted address responds by
pulling the data line low during the ninth clock pulse. This is
known as an acknowledge bit. All other devices withdraw from
the bus at this point and maintain an idle condition. The idle
condition is where the device monitors the SDATA and SCLOCK
lines waiting for the start condition and the correct transmitted
address. The R/W bit determines the direction of the data. A
Logic “0” on the LSB of the first byte means that the master
will write information to the peripheral. A Logic “1” on the LSB
of the first byte means that the master will read information
from the peripheral.
The ADV7175A/ADV7176A acts as a standard slave device on
the bus. The data on the SDATA pin is 8 bits long, supporting
the 7-bit addresses, plus the R/W bit. The ADV7175A has 37
subaddresses and the ADV7176A has 20 subaddresses to enable
access to the internal registers. It therefore interprets the first
byte as the device address and the second byte as the starting
subaddress. The subaddresses auto increment allow data to
be written to or read from the starting subaddress. A data
transfer is always terminated by a stop condition. The user can
ADV7175A/ADV7176Aalso access any unique subaddress register on a one by one basis
without having to update all the registers. There is one excep-
tion. The subcarrier frequency registers should be updated in
sequence, starting with Subcarrier Frequency Register 0. The
auto increment function should then be used to increment and
access Subcarrier Frequency Registers 1, 2 and 3. The subcarrier
frequency registers should not be accessed independently.
Stop and start conditions can be detected at any stage during
the data transfer. If these conditions are asserted out of sequence
with normal read and write operations, they cause an immediate
jump to the idle condition. During a given SCLOCK high
period, the user should issue only one start condition, one
stop condition or a single stop condition followed by a single
start condition. If an invalid subaddress is issued by the user,
the ADV7175A/ADV7176A will not issue an acknowledge and
will return to the idle condition. If, in auto-increment mode
the user exceeds the highest subaddress, the following action
will be taken:
Figure 30.Write and Read Sequences
1. In Read Mode, the highest subaddress register contents
will continue to be output until the master device issues a
no-acknowledge. This indicates the end of a read. A no-
acknowledge condition is where the SDATA line is not pulled
low on the ninth pulse.
2. In Write Mode, the data for the invalid byte will not be
loaded into any subaddress register, a no-acknowledge will
be issued by the ADV7175A/ADV7176A and the part will
return to the idle condition.
Figure 29.Bus Data Transfer
Figure 29 illustrates an example of data transfer for a read
sequence and the start and stop conditions.
Figure 30 shows bus write and read sequences.
REGISTER ACCESSESThe MPU can write to or read from all of the ADV7175A/
ADV7176A registers except the subaddress register, which is a
write-only register. The subaddress register determines which
register the next read or write operation accesses. All communi-
cations with the part through the bus start with an access to the
subaddress register. A read/write operation is performed from/to
the target address, which then increments to the next address
until a stop command on the bus is performed.
REGISTER PROGRAMMINGThe following section describes each register, including subaddress
register, mode registers, subcarrier frequency registers, subcarrier
phase register, timing registers, closed captioning extended data
registers, closed captioning data registers and NTSC pedestal
control registers in terms of its configuration.
Subaddress Register (SR7–SR0)The communications register is an 8-bit write-only register.
After the part has been accessed over the bus, and a read/write
operation is selected, the subaddress is set up. The subaddress
register determines to/from which register the operation takes
place.
Figure 31 shows the various operations under the control of
the subaddress register. Zero should always be written to
SR7–SR6.
Register Select (SR5–SR0)These bits are set up to point to the required starting address.
MODE REGISTER 0 MR0 (MR07–MR00)
(Address [SR4–SR0] = 00H)Figure 32 shows the various operations under the control of Mode
Register 0. This register can be read from as well as written to.
MR0 BIT DESCRIPTION
Output Video Standard Selection (MR01–MR00)These bits are used to set up the encode mode. The ADV7175A/
ADV7176A can be set up to output NTSC, PAL (B, D, G, H, I)
and PAL (M) standard video.
Pedestal Control (MR02)This bit specifies whether a pedestal is to be generated on
the NTSC composite video signal. This bit is invalid if the
ADV7175A/ADV7176A is configured in PAL mode.
Luminance Filter Control (MR04–MR03)The luminance filters are divided into two sets (NTSC/PAL) of
four filters, low-pass A, low-pass B, notch and extended. When
PAL is selected, bits MR03 and MR04 select one of four PAL
luminance filters; likewise, when NTSC is selected, bits MR03
and MR04 select one of four NTSC luminance filters. The fil-
ters are illustrated in Figures 4 to 12.
RGB Sync (MR05)This bit is used to set up the RGB outputs with the sync infor-
mation encoded on all RGB outputs. (This funcionality is only
available on the ADV7176A.)
Output Select (MR06)This bit specifies if the part is in composite video or RGB/YUV
mode. Please note that the main composite signal is still avail-
able in RGB/YUV mode.
Figure 32.Mode Register 0 (MR0)
ADV7175A/ADV7176A
MODE REGISTER 1 MR1 (MR17–MR10)
(Address (SR4–SR0) = 01H)Figure 33 shows the various operations under the control of Mode
Register 1. This register can be read from as well as written to.
MR1 BIT DESCRIPTION
Interlaced Mode Control (MR10)This bit is used to set up the output to interlaced or noninter-
laced mode. This mode is only relevant when the part is in
composite video mode.
Closed Captioning Field Selection (MR12–MR11)These bits control the fields on which closed captioning data is
displayed; closed captioning information can be displayed on an
odd field, even field or both fields.
DAC Control (MR16–MR13)These bits can be used to power down the DACs. This can
be used to reduce the power consumption of the ADV7175A/
ADV7176A if any of the DACs are not required in the application.
Color Bar Control (MR17)This bit can be used to generate and output an internal color
bar test pattern. The color bar configuration is 100/7.5/75/7.5
for NTSC and 100/0/75/0 for PAL. It is important to note that
when color bars are enabled the ADV7175A/ADV7176A is
configured in a master timing mode as per the one selected by
bits TR01 and TR02.
SUBCARRIER FREQUENCY REGISTER 3-0
(FSC3–FSC0)
(Address [SR4–SR0] = 05H–02H)These 8-bit-wide registers are used to set up the subcarrier
frequency. The value of these registers are calculated by using
the following equation:
Subcarrier Frequency Register =
i.e.:NTSC Mode,
FCLK = 27 MHz,
FSCF = 3.5795454 MHz
Subcarrier Frequency Value =
= 21F07C16 HEX
Figure 34 shows how the frequency is set up by the four registers.
Figure 34.Subcarrier Frequency Register
SUBCARRIER PHASE REGISTER (FP7–FP0)
(Address [SR4–SR0] = 06H)This 8-bit-wide register is used to set up the subcarrier phase.
Each bit represents 1.41°.
TIMING REGISTER 0 (TR07–TR00)
(Address [SR4–SR0] = 07H)Figure 35 shows the various operations under the control of
Timing Register 0. This register can be read from as well as
written to. This register can be used to adjust the width and
position of the master mode timing signals.
TR0 BIT DESCRIPTION
Master/Slave Control (TR00)This bit controls whether the ADV7175A/ADV7176A is in
master or slave mode.
Timing Mode Selection (TR02–TR01)These bits control the timing mode of the ADV7175A/
ADV7176A. These modes are described in the Timing and
Control section of the data sheet.
BLANK Input Control (TR03)This bit controls whether the BLANK input is used when the
part is in slave mode.
Luma Delay (TR05–TR04)These bits control the addition of a luminance delay. Each bit
represents a delay of 74 ns.
Pixel Port Control (TR06)This bit is used to set the pixel port to accept 8-bit or 16-bit
data. If an 8-bit input is selected the data will be set up on Pins
P7–P0.
Timing Register Reset (TR07)Toggling TR07 from low to high and low again resets the inter-
nal timing counters. This bit should be toggled after power-up,
reset or changing to a new timing mode.
CLOSED CAPTIONING EVEN FIELD
DATA REGISTER 1–0 (CED15–CED0)
(Address [SR4–SR0] = 09–08H)These 8-bit-wide registers are used to set up the closed captioning
extended data bytes on even fields. Figure 36 shows how the
high and low bytes are set up in the registers.
Figure 36.Closed Captioning Extended Data Register
CLOSED CAPTIONING ODD FIELD
DATA REGISTER 1–0 (CCD15–CCD0)
(Subaddress [SR4–SR0] = 0B–0AH)These 8-bit-wide registers are used to set up the closed captioning
data bytes on odd fields. Figure 37 shows how the high and low
bytes are set up in the registers.
Figure 37.Closed Captioning Data Register
TIMING REGISTER 1 (TR17–TR10)
(ADDRESS [SR4–SR0] = 0CH)Timing Register 1 is an 8-Bit-Wide Register
Figure 38 shows the various operations under the control of
Timing Register 1. This register can be read from as well as
written to. This register can be used to adjust the width and
position of the master mode timing signals.
TR1 BIT DESCRIPTION
HSYNC Width (TR11–TR10)These bits adjust the HSYNC pulsewidth.
HSYNC to FIELD/VSYNC Delay (TR13–TR12)These bits adjust the position of the HSYNC output relative to
the FIELD/VSYNC output.
HSYNC to FIELD Rising Edge Delay (TR15–TR14)When the ADV7175A/ADV7176A is in Timing Mode 1, these
bits adjust the position of the HSYNC output relative to the
FIELD output rising edge.
VSYNC Width (TR15–TR14)When the ADV7175A/ADV7176A is in Timing Mode 2, these
bits adjust the VSYNC pulsewidth.
HSYNC to Pixel Data Adjust (TR17–TR16)This enables the HSYNC to be adjusted with respect to the
pixel data. This allows the Cr and Cb components to be
swapped. This adjustment is available in both master and slave
timing modes.
MODE REGISTER 2 MR2 (MR27–MR20)
(Address [SR4–SR0] = 0DH)Mode Register 2 is an 8-bit-wide register.
Figure 39 shows the various operations under the control of Mode
Register 2. This register can be read from as well as written to.
MR2 BIT DESCRIPTION
Square Pixel Control (MR20)This bit is used to set up square pixel mode. This is available in
slave mode only. For NTSC, a 24.5454 MHz clock must be
supplied. For PAL, a 29.5 MHz clock must be supplied.
