ADV7176KS ,Integrated Digital CCIR-601 YCrCb to PAL/NTSC Video EncoderSPECIFICATIONS T to T unless otherwise noted)MIN MAXModel ADV7175/ADV71761Parameter Conditions ..
ADV7177KS ,Integrated Digital CCIR-601 to PAL/NTSC Video EncoderGENERAL DESCRIPTION(VHS) Y/C or RGB (SCART)/YUV Video OutputsThe ADV7177/ADV7178 is an integrated d ..
ADV7177KSZ ,Digital CCIR-601 to PAL/NTSC Video Encoder with 3x9-Bit DACsGENERAL DESCRIPTIONProgrammable Luma Filters (Low-Pass/Notch/Extended)The ADV7177/ADV7178 is an int ..
ADV7177KSZ ,Digital CCIR-601 to PAL/NTSC Video Encoder with 3x9-Bit DACsspecifications T to T unless otherwise noted.)AA REF SET MIN MAX1Parameter Conditions Min Typ Max U ..
ADV7178KS ,Integrated Digital CCIR-601 to PAL/NTSC Video EncoderFEATURES Programmable Subcarrier Frequency and PhaseITU-R BT601/656 YCrCb to PAL/NTSC Video Encoder ..
ADV7179BCP ,Chip Scale NTSC/PAL Video EncoderSpecifications subject to change without notice. No license is granted by implication www.analog.c ..
AM27C512-90DE , 512 Kilobit ( 64 K x 8-Bit ) CMOS EPROM Speed options as fast as 55 ns
AM27C512-90DI , 512 Kilobit ( 64 K x 8-Bit ) CMOS EPROM Speed options as fast as 55 ns
AM27C512-90PC , 512 Kilobit ( 64 K x 8-Bit ) CMOS EPROM Speed options as fast as 55 ns
AM27C64 , 64 Kilobit (8 K x 8-Bit) CMOS EPROM
AM27C64-120DE , 64 Kilobit (8 K x 8-Bit) CMOS EPROM
AM27C64-120DI , 64 Kilobit (8 K x 8-Bit) CMOS EPROM
ADV7175KS-ADV7176-ADV7176KS
Integrated Digital CCIR-601 YCrCb to PAL/NTSC Video Encoder
REV.A
Integrated Digital CCIR-601
YCrCb to PAL/NTSC Video Encoder
FEATURES
CCIR-601 YCrCb to PAL/NTSC Video Encoder
Single 27 MHz Clock Required (32 Oversampling)
Pixel Port Supports:
CCIR-656 4:2:2 8-Bit Parallel Input Format
4:2:2 16-Bit Parallel Input Format
SMPTE 170M NTSC Compatible Composite Video Output
CCIR624/CCIR601 PAL Compatible Composite Video Output
SCART/PeriTV Support
YUV Output Mode
Simultaneous Composite and S-VHS Y/C or RGB YUV
Video Outputs
Programmable Luma Filters (Low-Pass/Notch)
Square Pixel Support (Slave Mode)
Allows Subcarrier Phase Locking with External Video
Source
10-Bit DAC Resolution for Encoded Video Channels
8-Bit DAC Resolution for RGB Output
YUV Interpolation for Accurate Subcarrier Construction
Programmable Subcarrier Frequency and Phase
Programmable LUMA Delay
Color Signal Control/Burst Signal Control
Interlaced/Noninterlaced Operation
Complete On-Chip Video Timing Generator
Master/Slave Operation Supported
Master Mode Timing Programmability
Macrovision Antitaping Facility Rev 6.1/7.x (ADV7175 Only)*
Close Captioning Support
Teletext Support (Passthrough Mode)
On-Board Color Bar Generation
On-Board Voltage Reference
2-Wire Serial MPU Interface (I2C Compatible)
+5 V CMOS Monolithic Construction
44-Pin PQFP Thermally Enhanced Package
APPLICATIONS
MPEG-1 and MPEG-2 Video
DVD
Digital Satellite/Cable Systems (Set Top Boxes/IRDs)
Video Games
CD Video/Karaoke
Professional Studio Quality
PC Video/Multimedia
GENERAL DESCRIPTIONThe ADV7175/ADV7176 is an integrated digital video encoder
that converts Digital CCIR-601 4:2:2 component video data into a
standard analog baseband television signal compatible with world
wide standards NTSC, PAL B/D/G/H/I, PAL M or PAL N. In
addition to the composite output signal, there is the facility to out-
put S-VHS Y/C video, YUV or RGB video. The Y/C, YUV or
RGB format is simultaneously available at the analog outputs with
the composite video signal. Each analog output generates a
standard video-level signal into a doubly terminated 75 Ω load.
(Continued on page 6)
FUNCTIONAL BLOCK DIAGRAMRESET
VAA
SCLOCKSDATAALSB
HSYNC
FIELD/VSYNC
BLANK
CLOCKGND
GREEN/
LUMA/
RED/
CHROMA/
BLUE/
COMPOSITE/
COMPOSITE
VREF
RSET
COMP
COLOR
DATA
P7–P0
P15–P8
SCRESET/RTC*This device is protected by U.S. Patent Numbers 4631603, 4577216, 4819098 and other intellectual property rights. The Macrovision anticopy process is
licensed for noncommercial home use only, which is its sole intended use in the device. Please contact sales office for latest Macrovision version available.
ADV7175/ADV7176–SPECIFICATIONSDIGITAL OUTPUTS
ANALOG OUTPUTS
VOLTAGE REFERENCE
POWER REQUIREMENTS
DYNAMIC PERFORMANCE
NOTES
1±5% for all versions.
2Temperature range TMIN to TMAX: 0°C to 70°C.
3Full drive into 37.5Ω load.
4Minimum drive with buffered/scaled output load.
(VAA = +5 V1, VREF = 1.235 V RSET = 150 V. All specifications
TMIN to TMAX2 unless otherwise noted)
AC CHARACTERISTICS1
TIMING–SPECIFICATIONS2ANALOG OUTPUTS
CLOCK CONTROLAND PIXEL PORT
NOTESGuaranteed by characterization.TTL input values are 0 to 3 volts, with input rise/fall times ≤ 3 ns, measured between the 10% and 90% points. Timing reference points at 50% for inputs and
outputs. Analog Output Load ≤ 3 pF.±5% for all versions.Temperature range (TMIN to TMAX); 0°C to +70°C.Output delay measured from the 50% point of the rising edge of CLOCK to the 50% point of full-scale transition.Pixel Port consists of the following inputs:
Pixel Inputs:P15–P0
Pixel Controls:HSYNC, FIELD/VSYNC, BLANK
Clock Input:CLOCK
Specifications subject to change without notice.
ADV7175/ADV7176
(VAA = +5 V3, VREF = 1.235 V RSET = 150 V. All specifications TMIN to TMAX4 unless otherwise noted)
ADV7175/ADV7176
t5
t4 t8
SDATA
SCLOCKFigure 1.MPU Port Timing Diagram
CLOCK
PIXEL INPUT
DATA
HSYNC,
FIELD/VSYNC,
BLANK
HSYNC,
FIELD/VSYNC,
BLANK
CONTROL
I/PS
CONTROL
O/PSFigure 2.Pixel and Control Data Timing Diagram
ORDERING GUIDE
ABSOLUTE MAXIMUM RATINGS1VAA to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
Voltage on Any Digital Input Pin . GND – 0.5 V to VAA + 0.5 V
Storage Temperature (TS) . . . . . . . . . . . . . –65°C to +150°C
Junction Temperature (TJ) . . . . . . . . . . . . . . . . . . . . +150°C
Lead Temperature (Soldering, 10 secs) . . . . . . . . . . . +260°C
Analog Outputs to GND2 . . . . . . . . . . . . . GND –0.5 to VAA
NOTESStresses above those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those listed in the
operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.Analog Output Short Circuit to any Power Supply or Common can be of an
indefinite duration.
CAUTIONESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the ADV7175/ADV7176 feature proprietary ESD protection circuitry, permanent
damage may occur on devices subjected to high energy electrostatic discharges. Therefore,
proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
PIN DESCRIPTION
PIN CONFIGURATION
VREF
COMPOSITE
BLUE/COMPOSITE/U
VAA
GND
VAA
GREEN/LUMA/Y
VAA
P10
P11
P12
GND
VAA
RED/CHROMA/V
COMP
SDATA
SCLOCK
CLOCKGNDP4P3P2P1P0V
GNDSCRESET
RTCR
SET
ADV7175/ADV7176The ADV7175/ADV7176 is protected by U.S. Patent Numbers
5,343,196 and 5,442,355 and other intellectual property rights.
DATA PATH DESCRIPTIONFor PAL B, D, G, H, I, M, N and NTSC M, N modes, YCrCb
4:2:2 data is input via the CCIR-656 compatible pixel port at a
13.5 MHz data rate. The pixel data is de-multiplexed to form
three data paths. Y has a range of 16 to 235, Cr and Cb have a
range of 128 ± 112. The ADV7175/ADV7176 supports PAL
(B, D, G, H, I, N, M) and NTSC (with and without Pedestal)
standards. The appropriate SYNC, BLANK and burst levels are
added to the YCrCb data. Macrovision antitaping (ADV7175
only) and close-captioning levels are also added to Y and the
resultant data is interpolated to a rate of 27 MHz. The interpo-
lated data is filtered and scaled by three digital FIR filters.
The U and V signals are modulated by the appropriate subcarrier
sine/cosine phases and added together to make up the chromi-
nance signal. The luma (Y) signal can be delayed 1-3 luma
cycles (each cycle is 74 ns) with respect to the chroma signal.
The luma and chroma signals are then added together to make
up the composite video signal. All edges are slew rate limited.
The YCrCb data is also used to generate RGB data with appro-
priate SYNC and BLANK levels. The RGB data is in sychro-
nization with the composite video output. Alternatively analog
YUV data can be generated instead of RGB.
The four 10-bit DACs can be used to output:10-bit composite video + 8-bit RGB video.10-bit composite video + 8-bit YUV video.Two 10-bit composite video signals
+ 10-bit LUMA & CHROMA (Y/C) signals.
Alternatively, each DAC can be individually powered off if not
required.
All possible video outputs are illustrated in Appendix 3, 4 and 5.
INTERNAL FILTER RESPONSEThe Y filter supports several different frequency responses in-
cluding two 4.5/5.0 MHz low-pass and PAL/NTSC subcarrier
notch responses. The U and V filters have a 0.6/1 0.3 MHz
low-pass response.
These filter characteristics are illustrated in Figures 3 to 11.
(Continued from page 1)
The ADV7175/ADV7176 also supports both a PAL and NTSC
square pixel mode in slave mode.
The video encoder accepts an 8-bit parallel pixel data stream in
CCIR-656 format or a 16-bit parallel data stream. This 4:2:2
data stream is interpolated into 4:4:4 component video (YUV).
The YUV video is interpolated to two times the pixel rate. The
color-difference components (UV) are quadrature modulated
using a subcarrier frequency generated by an on-chip synthesizer
(also running at two times the pixel rate). The two times pixel
rate sampling allows more accurate generation of the subcarrier
because frequency and phase errors are reduced by the higher
sampling rate. The ADV7175/ADV7176 also offers the option to
output the YUV information directly.
The luminance and chrominance components are digitally com-
bined and the resulting composite signal is output via a 10-bit
DAC. Three additional 10-/8-bit DACs are provided to output
S-VHS Y/C Video (10 bits), YUV or RGB Video (8 bits).
The output video frames are synchronized with the incoming
data timing reference codes. Optionally the encoder accepts (and
can generate) HSYNC, VSYNC & FIELD timing signals. These
timing signals can be adjusted to change pulse width and posi-
tion while the part is in the master mode. The encoder requires a
single two times pixel rate (27 MHz) clock for standard operation.
Alternatively the encoder requires 24.54 MHz clock for NTSC
or 29.5 MHz clock for PAL square pixel mode operation. All in-
ternal clocks are generated on-chip. The ADV7175/ADV7176
modes are set up over a two wire serial bidirectional port (I2C
Compatible) with two slave addresses.
Additionally, the ADV7175/ADV7176 allows a subcarrier phase
lock with an external video source and has a color bar generator
on-board.
Functionally the ADV7175 and ADV7176 are the same with
the exception that the ADV7175 can output the Macrovision
(Revision 6.1/7.x) anticopy algorithm.
The ADV7175/ADV7176 is fabricated in a +5 V CMOS pro-
cess. Its monolithic CMOS construction ensures greater func-
tionality with low power dissipation.
The ADV7175/ADV7176 is packaged in a 44-pin thermally en-
hanced PQFP package (patent pending).
Figure 3.Y Filter Specifications
FREQUENCY – MHz
AMPLITUDE – dBFigure 5.NTSC Low-Pass Filter
FREQUENCY – MHz
AMPLITUDE – dBFigure 6.NTSC Notch Filter
Figure 7.PAL Low-Pass Filter
Figure 8.PAL Notch Filter
FREQUENCY – MHz
AMPLITUDE – dBFigure 9.NTSC/PAL Extended Mode Filter
ADV7175/ADV7176
COLOR BAR GENERATIONThe ADV7175/ADV7176 can be configured to generate 75%
amplitude, 75% saturation (75/7.5/75/7.5) for NTSC or 75%
amplitude, 100% saturation (100/0/75/0) for PAL color bars.
These are enabled by setting MR17 of Mode Register 1 to
Logic “1.”
SQUARE PIXEL MODEThe ADV7175/ADV7176 can be used to operate in square
pixel mode. For NTSC operation an input clock of 24.54MHz
is required. Alternatively, for PAL operation, an input clock of
29.5 MHz is required. The internal filters scale accordingly for
square pixel mode operation.
COLOR SIGNAL CONTROLThe color information can be switched on and off the video
output using Bit MR24 of Mode Register 2.
BURST SIGNAL CONTROLThe burst information can be switched on and off the video
output using Bit MR25 of Mode Register 2.
NTSC PEDESTAL CONTROLThe pedestal information on both odd and even fields can be
controlled on a line by line basis using the NTSC Pedestal
Control Registers. This allows the pedestals to be controlled
during the vertical blanking interval (Lines 10 to 25).
SUBCARRIER RESETTogether with the SCRESET/RTC PIN and Bits MR22 and
MR21 of Mode Register 2, the ADV7175/ADV7176 can be
used in subcarrier reset mode. The subcarrier will reset to field
0 at the start of the following field when a high to low transition
occurs on this input pin.
REAL TIME CONTROLTogether with the SCRESET/RTC PIN and Bits MR22 and
MR21 of Mode Register 2, the ADV7175/ADV7176 can be
used to lock an external video source. The real time control
mode allows the ADV7175/ADV7176 to automatically alter the
subcarrier frequency to compensate for line length variation.
When the part is connected to a device that outputs out a digi-
tal datastream in the RTC format (such as a Phillips SAA7110
COMPOSITE
VIDEO
e.g. VCR
OR CABLEFigure 12.RTC Connections
PIXEL TIMING DESCRIPTIONThe ADV7175/ADV7176 can operate in either 8-bit or 16-bit
YCrCb Mode.
8-Bit YCrCb ModeThis default mode accepts multiplexed YCrCb inputs through
the P7–P0 pixel inputs. The inputs follow the sequence Cb0,
Y0 Cr0, Y1 Cb1, Y2, etc. The Y, Cb and Cr data are input on
a rising clock edge.
16-Bit YCrCb ModeThis mode accepts Y inputs through the P7-P0 pixel inputs and
multiplexed CrCb inputs through the P15-P8 pixel inputs. The
data is loaded on every second rising clock edge of CLOCK.
The inputs follow the sequence Cb0, Y0 Cr0, Y1 Cb1, Y2, etc.
VIDEO TIMING DESCRIPTIONThe ADV7175/ADV7176 is intended to interface to off the shelf
MPEG1 and MPEG2 Decoders. As a consequence the
ADV7175/ADV7176 accepts 4:2:2 YCrCb pixel data via a
CCIR-656 pixel port and has several video timing modes of
operation that allow it to be configured as either system master
video timing generator or a slave to the system video timing gen-
erator. The ADV7175/ADV7176 generates all of the required
horizontal and vertical timing periods and levels for the analog
video outputs.
The ADV7175/ADV7176 calculates the width and placement
FREQUENCY – MHz
AMPLITUDE – dB
–70Figure 10.NTSC UV Filter
Figure 11.PAL UV Filter
Mode 0 (CCIR-656): Slave Option.(Timing Register 0 TR0 = X X X X X 0 0 0)
The ADV7175/ADV7176 is controlled by the SAV (Start Active Video) and EAV (End Active Video) time codes in the pixel data.
All timing information is transmitted using a 4-byte synchronization pattern. A synchronization pattern is sent immediately before
and after each line during active picture and retrace. Mode 0 is illustrated in Figure 13. The HSYNC, FIELD/VSYNC and BLANK
(if not used) pins should be tied high in this mode.
SAV CODE
ANCILLARY DATA
(HANC)4 PIXELS1440 PIXELS4 PIXELS1440 PIXELS
END OF ACTIVE
VIDEO LINE
START OF ACTIVE
VIDEO LINE
ANALOG
VIDEO
INPUT PIXELS
NTSC SYSTEM
PAL SYSTEMFigure 13.Timing Mode 0 (Slave Mode)
Mode 0 (CCIR-656): Master Option.(Timing Register 0 TR0 = X X X X X 0 0 1)
The ADV7175/ADV7176 generates H, V and F signals required for the SAV (start active video) and EAV (end active video) time
codes in the CCIR656 standard. The H bit is output on the HSYNC pin, the V bit is output on the BLANK pin and the F bit is
output on the FIELD/VSYNC pin. Mode 0 is illustrated in Figure 14 (NTSC) and Figure 15 (PAL). The H, V and F transitions
relative to the video waveform are illustrated in Figure 16.
DISPLAY
DISPLAY
ADV7175/ADV7176
DISPLAY
DISPLAY
313Figure 15.Timing Mode 0 (PAL Master Mode)
ANALOG
VIDEOFigure 16.Timing Mode 0 Data Transitions (Master Mode)
Mode 1: Slave Option. HSYNC, BLANK, FIELD.(Timing Register 0 TR0 = X X X X X 0 1 0)
In this mode the ADV7175/ADV7176 accepts horizontal SYNC and Odd/Even FIELD signals. A transition of the FIELD input
when HSYNC is low indicates a new frame, i.e., vertical retrace. The BLANK signal is optional. When the BLANK input is disabled
the ADV7175/ADV7176 automatically blanks all normally blank lines as per CCIR-624. Mode 1 is illustrated in Figure 17 (NTSC)
and Figure 18 (PAL).
DISPLAYDISPLAY
HSYNC
BLANK
FIELD
DISPLAY
HSYNC
BLANK
FIELDFigure 17.Timing Mode 1 (NTSC)
DISPLAY
HSYNC
BLANK
FIELD
DISPLAY
DISPLAY
HSYNC
BLANK
FIELD
DISPLAY
320
ADV7175/ADV7176
Mode 1:Master Option. HSYNC, BLANK, FIELD.(Timing Register 0 TR0 = X X X X X 0 1 1)
In this mode the ADV7175/ADV7176 can generate horizontal SYNC and Odd/Even FIELD signals. A transition of the FIELD
input when HSYNC is low indicates a new frame i.e., vertical retrace. The BLANK signal is optional. When the BLANK input is
disabled the ADV7175/ADV7176 automatically blanks all normally blank lines as per CCIR-624. Pixel data is latched on the rising
clock edge following the timing signal transitions. Mode 1 is illustrated in Figure 17 (NTSC) and Figure 18 (PAL). Figure 19 illus-
trates the HSYNC, BLANK and FIELD for an odd or even field transition relative to the pixel data.
HSYNC
FIELD
BLANK
PIXEL
DATA
PAL = 132 * CLOCK/2
NTSC = 118 * CLOCK/2YFigure 19.Timing Mode 1 Odd/Even Field Transitions
Mode 2:Slave Option. HSYNC, VSYNC, BLANK.(Timing Register 0 TR0 = X X X X X 1 0 0)
In this mode the ADV7175/ADV7176 accepts horizontal and vertical SYNC signals. A coincident low transition of both HSYNC
and VSYNC inputs indicates the start of an odd field. A VSYNC low transition when HSYNC is high indicates the start of an even
field. The BLANK signal is optional. When the BLANK input is disabled, the ADV7175/ADV7176 automatically blanks all nor-
mally blank lines as per CCIR-624. Mode 2 is illustrated in Figure 20 (NTSC) and Figure 21 (PAL).
DISPLAYDISPLAY
HSYNC
BLANK
VSYNC
DISPLAYDISPLAY
HSYNC
BLANK
VSYNC
DISPLAY
HSYNC
BLANK
VSYNC
DISPLAY
DISPLAY
HSYNC
BLANK
DISPLAY
VSYNCFigure 21.Timing Mode 2 (PAL)
Mode 2:Master Option. HSYNC, VSYNC, BLANK.(Timing Register 0 TR0 = X X X X X 1 0 1 )
In this mode the ADV7175/ADV7176 can generate horizontal and vertical SYNC signals. A coincident low transition of both
HSYNC and VSYNC inputs indicates the start of an odd field. A VSYNC low transition when HSYNC is high indicates the start of
an even field. The BLANK signal is optional. When the BLANK input is disabled the ADV7175/ADV7176 automatically blanks all
normally blank lines as per CCIR-624. Mode 2 is illustrated in Figure 20 (NTSC) and Figure 21 (PAL). Figure 22 illustrates the
HSYNC, BLANK and VSYNC for an even to odd field transition relative to the pixel data. Figure 23 illustrates the HSYNC,
BLANK and VSYNC for an odd to even field transition relative to the pixel data.
HSYNC
VSYNC
BLANK
PIXEL
DATAYFigure 22.Timing Mode 2 Even-to-Odd Field Transition
ADV7175/ADV7176
HSYNC
VSYNC
BLANK
PIXEL
DATAFigure 23.Timing Mode 2 Odd-to-Even Field Transition
Mode 3:Master/Slave Option. HSYNC, BLANK, FIELD.(Timing Register 0 TR0 = X X X X X 1 1 0 or X X X X X 1 1 1)
In this mode the ADV7175/ADV7176 accepts or generates Horizontal SYNC and odd/even FIELD signals. A transition of the
FIELD input when HSYNC is high indicates a new frame i.e., vertical retrace. The BLANK signal is optional. When the BLANK
input is disabled the ADV7175/ADV7176 automatically blanks all normally blank lines as per CCIR-624. Mode 3 is illustrated in
Figure 24 (NTSC) and Figure 25 (PAL).
DISPLAYDISPLAY
HSYNC
BLANK
FIELD
DISPLAYDISPLAY
HSYNC
BLANK
FIELDFigure 24.Timing Mode 3 (NTSC)
DISPLAY
HSYNC
BLANK
FIELD
DISPLAY
DISPLAY
HSYNC
BLANK
FIELD
DISPLAY
320Figure 25.Timing Mode 3 (PAL)
PAL–Interlaced:Scan lines 1–6, 311–318 and 624–625 are al-
ways blanked and vertical sync pulses are included in Fields 1,
2, 5 and 6. Scan lines 1–5, 311–319 and 624–625 are always
blanked and vertical sync pulses are included in Fields 3, 4, 7
and 8. The remaining scan lines in the vertical interval are also
blanked and can be used for close captioning data. Burst is dis-
abled on lines 1–6, 311–318 and 623–625 in Fields 1, 2, 5 and
6. Burst is disabled on lines 1–5, 311–319 and 623–625 in
Fields 3, 4, 7 and 8.
PAL–Noninterlaced:Scan lines 1–6 and 311–312 are always
blanked and vertical sync pulses are included. The remaining
scan lines in the vertical interval are also blanked and can be
used for close captioning data. Burst is disabled on lines 1–5,
POWER-ON RESET
After power-up, it is necessary to execute a reset operation. A
reset occurs on the falling edge of a high to low transition on the
RESET pin. This initializes the pixel port such that the pixel
inputs P7–P0 are selected. After reset, the ADV7175/ADV7176
is automatically set up to operate in NTSC mode. Subcarrier
frequency code 21F07C16 HEX is loaded into the subcarrier
frequency registers. All other registers, with the exception of
Mode Register 0, are set to 00H. All bits in Mode Register 0
are set to Logic Level “0” except Bit MR02. Bit MR02 of
Mode Register 0 is set to Logic “1.” This enables the 7.5 IRE
pedestal.
In addition the ADV7175/ADV7176 supports a PAL or NTSC
square pixel operation in slave mode. The part requires an in-
put pixel clock of 24.54 MHz for NTSC and an input pixel
clock of 29.5 MHz for PAL. The internal horizontal line
counters place the various video waveform sections in the cor-
rect location for the new clock frequencies.
The ADV7175/ADV7176 has 8 distinct master or slave timing
configurations. These are divided into 4 timing modes which
operate at one discrete clock frequency (27 MHz). Timing con-
trol is established with the bidirectional SYNC, BLANK and
FIELD/VSYNC pins. Timing Mode Register 1 can also be
used to vary the timing pulse widths and the where they occur in
relation to each other.
OUTPUT VIDEO TIMINGThe video timing generator generates the appropriate SYNC,
BLANK and BURST sequence that controls the output analog
waveforms. These sequences are summarized below. In slave
modes the following sequences are synchronized with the input
timing control signals. In master modes the timing generator
free runs and generates the following sequences in addition to
the output timing control signals.
NTSC–Interlaced:Scan lines 1–9 and 264–272 are always
blanked and vertical sync pulses are included. Scan lines 525,
10–21 and 262, 263, 273–284 are also blanked and can be used
for close captioning data. Burst is disabled on lines 1–6, 261–
269 and 523–525.
NTSC–Noninterlaced:Scan lines 1–9 are always blanked
(Continued from page 8)
ADV7175/ADV7176
MPU PORT DESCRIPTIONThe ADV7175 and ADV7176 support a two wire serial (I2C
compatible) microprocessor bus driving multiple peripherals.
Two inputs serial data (SDATA) and serial clock (SCLOCK)
carry information between any device connected to the bus.
Each slave device is recognized by a unique address. The
ADV7175 and ADV7176 each have four possible slave ad-
dresses for both read and write operations. These are unique
addresses for each device and are illustrated in Figure 26 and
Figure 27. The LSB sets either a read or write operation.
Logic Level “1” corresponds to a read operation while Logic
Level “0” corresponds to a write operation. A1 is set by setting
the ALSB pin of the ADV7175/ADV7176 to Logic Level “0” or
Logic Level “1.”
Fig 26.ADV7175 Slave Address
Fig 27.ADV7176 Slave Address
To control the various devices on the bus the following protocol
must be followed. First the master initiates a data transfer by es-
tablishing a start condition, defined by a high to low transition
on SDATA while SCLOCK remains high. This indicates that
an address/data stream will follow. All peripherals respond to
the start condition and shift the next eight bits (7-bit address +
R/W bit). The bits transferred from MSB down to LSB. The
peripheral that recognizes the transmitted address responds by
pulling the data line low during the ninth clock pulse. This is
known as an acknowledge bit. All other devices withdraw from
the bus at this point and maintain an idle condition. The idle
condition is where the device monitors the SDATA and SCLOCK
lines waiting for the Start condition and the correct transmitted
address. The R/W bit determines the direction of the data. A
Logic “0” on the LSB of the first byte means that the master
will write information to the peripheral. A Logic “1” on the
LSB of the first byte means that the master will read informa-
tion from the peripheral.
The ADV7175/ADV7176 acts as a standard slave device on the
bus. The data on the SDATA pin is 8 bits long supporting the
7-bit addresses plus the R/W bit. The ADV7175 has 33 sub-
addresses and the ADV7176 has 19 subaddresses to enable ac-
cess to the internal registers. It, therefore, interprets the first
byte as the device address and the second byte as the starting
subaddress. The subaddresses auto increment allowing data to
be written to or from the starting subaddress. A data transfer is
always terminated by a stop condition. The user can also access
any unique subaddress register on a one by one basis without
having to update all the registers. There is one exception. The
Subcarrier Frequency Registers should be updated in sequence,
starting with Subcarrier Frequency Register 0. The auto incre-
ment function should be then used to increment and access
subcarrier frequency registers 1, 2 and 3. The subcarrier fre-
quency registers should not be accessed independently.
Stop and start conditions can be detected at any stage during
the data transfer. If these conditions are asserted out of se-
quence with normal read and write operations, then these cause
an immediate jump to the idle condition. During a given
SCLOCK high period the user should only issue one start con-
dition, one stop condition or a single stop condition followed by
a single start condition. If an invalid subaddress is issued by the
user, the ADV7175/ADV7176 will not issue an acknowledge
and will return to the idle condition. If in auto-increment
mode, the user exceeds the highest subaddress then the follow-
ing action will be taken:In Read Mode the highest subaddress register contents will
continue to be output until the master device issues a no-ac-
knowledge. This indicates the end of a read. A no-acknowledge
condition is where the SDATA line is not pulled low on the
ninth pulse.In Write Mode, the data for the invalid byte will be not be
loaded into any subaddress register, a no-acknowledge will
be issued by the ADV7175/ADV7176 and the part will re-
turn to the idle condition.
Figure 28 illustrates an example of data transfer for a read se-
quence and the start and stop conditions.
Figure 28.Bus Data Transfer
Figure 29 shows bus write and read sequences.
LSB = 0LSB = 1
WRITE
SEQUENCE
READ
SEQUENCE
Figure 30.Subaddress Register
REGISTER ACCESSESThe MPU can write to or read from all of the registers of the
ADV7175/ADV7176 except the subaddress register which is a
write only register. The subaddress register determines which
register the next read or write operation accesses. All communi-
cations with the part through the bus start with an access to the
subaddress register. Then a read/write operation is performed
from/to the target address which then increments to the next
address until a stop command on the bus is performed.
REGISTER PROGRAMMINGThe following section describes each register, including
subaddress register, mode registers, subcarrier frequency regis-
ters, subcarrier phase register, timing registers, closed captioning
extended data registers, closed captioning data registers and
NTSC pedestal control registers in terms of its configuration.
Subaddress Register (SR7–SR0)The communications register is an eight bit write-only register.
After the part has been accessed over the bus and a read/write
operation is selected, the subaddress set up. The subaddress
register determines to/from which register the operation takes
place.
Figure 30 shows the various operations under the control of the
subaddress register. Zero should always be written to SR7–
SR5.
Register Select (SR4–SR0):These bits are setup to point to the required starting address.
MODE REGISTER 0 MR0 (MR07–MR00)
(Address (SR4–SR0) = 00H)Mode Register 0 is a 8-bit wide register.
Figure 31 shows the various operations under the control of
Mode Register 0. This register can be read from as well written to.
ADV7175/ADV7176
MODE REGISTER 1 MR1 (MR17–MR10)
(Address (SR4–SR0) = 01H)Mode Register 1 is a 8-bit wide register.
Figure 32 shows the various operations under the control of Mode
Register 1. This register can be read from as well written to.
MODE REGISTER 1 (MR17–MR10) BIT DESCRIPTION
Interlaced Mode Control (MR10):This bit is used to setup the output to interlaced or non-inter-
laced mode. This mode is only relevant when the part is in
composite video mode.
Closed Captioning Field Control (MR12–MR11)These bits control the field that close captioning data is displayed
on close captioning information can be displayed on an odd field,
even field or both fields.
DAC Control (MR16–MR13)These bits can be used to power down the DACs. This can be
used to reduce the power consumption of the ADV7175/ADV7176
if any of the DACs are not required in the application.
Color Bar Control (MR17)This bit can be used to generate and output an internal color
bar. The color bar configuration is 75/75/75/7.5 for NTSC and
100/0/75/0 for PAL.
Figure 32.Mode Register 1
MODE REGISTER 0 (MR07–MR00) BIT DESCRIPTION
Encode Mode Control (MR01–MR00):These bits are used to set up the encode mode. The ADV7175/
ADV7176 can be set up to output NTSC, PAL (B, D, G, H, I),
PAL (M) and PAL (N) standard video.
Pedestal Control (MR02)This bit specifies whether a pedestal is to be generated on the
NTSC composite video signal. This bit is invalid if the
ADV7175/ADV7176 is configured in PAL mode.
Luminance Filter Control (MR04–MR03)These bits are used for selecting between a filter for the lumi-
nance signal. These filters automatically are set to the cutoff fre-
quency for the low-pass filters and the subcarrier frequency for
the notch filter. The extended mode filter is a 5.5 MHz low-pass
filter. The filters are illustrated in Figures 3 to 11.
RGB Sync (MR05)This bit is used to set up the RGB outputs with the sync infor-
mation encoded.
Output Control (MR06)This bit specifies if the part is in composite video or RGB/YUV
mode. Please note that in RGB/YUV mode the main composite
signal is still available.
