ADV7172 ,Digital PAL/NTSC Video Encoder with Six DACs (10 Bits), Color Control, Power Management, Macrovision 7.01GENERAL DESCRIPTIONMultistandard Video Output Support:The ADV7172/ADV7173 is an integrated Digital ..
ADV7172KST ,Digital PAL/NTSC Video Encoder with Six DACs 10 Bits, Color Control and Enhanced Power ManagementSPECIFICATIONSunless otherwise noted)1Parameter Test Conditions Min Typ Max UnitsSTATIC PERFORMANCE ..
ADV7173 ,Digital PAL/NTSC Video Encoder with Six DACs (10 Bits), Color Control and Enhanced Power ManagementSPECIFICATIONS1Parameter Test Conditions Min Typ Max UnitSTATIC PERFORMANCEResolution (Each DAC) 10 ..
ADV7173KSTZ ,Digital PAL/NTSC Video Encoder with Six DACs (10 Bits), Color Control and Enhanced Power ManagementGENERAL DESCRIPTIONMultistandard Video Output Support:The ADV7172/ADV7173 is an integrated Digital ..
ADV7174KCP-REEL ,Chip Scale PAL/NTSC Video Encoder with Advanced Power ManagementFeatures .. 16 Timing Mode Register 0 (TR0) ... 33 Color Bar Generation . 16 Timing Mode Register 1 ..
ADV7175KS ,Integrated Digital CCIR-601 YCrCb to PAL/NTSC Video Encoderspecifications T to T unless otherwise noted)AA REF SET MIN MAXParameter Min Typ Max Units Conditio ..
AM27C512-255DI , 512 Kilobit ( 64 K x 8-Bit ) CMOS EPROM Speed options as fast as 55 ns
AM27C512-55DC , 512 Kilobit ( 64 K x 8-Bit ) CMOS EPROM Speed options as fast as 55 ns
AM27C512-55DI , 512 Kilobit (64 K x 8-Bit) CMOS EPROM
AM27C512-70DI , 512 Kilobit ( 64 K x 8-Bit ) CMOS EPROM Speed options as fast as 55 ns
AM27C512-70JC , 512 Kilobit ( 64 K x 8-Bit ) CMOS EPROM Speed options as fast as 55 ns
AM27C512-90DE , 512 Kilobit ( 64 K x 8-Bit ) CMOS EPROM Speed options as fast as 55 ns
ADV7172-ADV7173
Digital PAL/NTSC Video Encoder with Six DACs (10 Bits), Color Control, Power Management, Macrovision 7.01
REV.B
Digital PAL/NTSC Video Encoder
with Six DACs (10 Bits), Color Control
and Enhanced Power Management
FEATURES
ITU-R1 BT601/656 YCrCb to PAL/NTSC Video Encoder
Six High Quality 10-Bit Video DACs
SSAF™ (Super Sub-Alias Filter)
Advanced Power Management Features
PC’98-Compliant (TV Detect with Polling and Auto
Shutdown to Save On Power Consumption)
Low Power DAC Mode
Individual DAC ON/OFF Control
Variable DAC Output Current (5 mA–36 mA)
Ultralow Sleep Mode Current
Hue, Brightness, Contrast and Saturation Controls
CGMS (Copy Generation Management System)
WSS (Wide Screen Signalling)
NTSC-M, PAL-M/N, PAL-B/D/G/H/I, PAL-60
YUV Betacam, MII and SMPTE/EBU N10 Output Levels
Single 27 MHz Clock Required (�2 Oversampling)
80 dB Video SNR
32-Bit Direct Digital Synthesizer for Color Subcarrier
Multistandard Video Output Support:
Composite (CVBS)
Component S-Video (Y/C)
Component YUV
EuroSCART RGB
Component YUV + CHROMA + LUMA + CVBS
EuroSCART Output RGB + CHROMA + LUMA + CVBS
Programmable Clamping Output Signal
Advanced Programmable Power-On Reset Sequencing
Video Input Data Port Supports:
CCIR-656 4:2:2 8-Bit Parallel Input Format
SMPTE 170M NTSC-Compatible Composite Video
ITU-R BT.470 PAL-Compatible Composite Video
Luma Sharpness Control
Programmable Luma Filters (Low-Pass [PAL/NTSC],
Notch [PAL/NTSC], Extended [SSAF], CIF and QCIF)
Programmable Chroma Filters (Low-Pass [0.65 MHz,
1.0 MHz, 1.2 MHz and 2.0 MHz], CIF and QCIF)
Programmable VBI (Vertical Blanking Interval)
Programmable Subcarrier Frequency and Phase
Programmable LUMA Delay
CCIR and Square Pixel Operation
Integrated Subcarrier Locking to External Video Source
Color Signal Control/Burst Signal Control
Interlaced/Noninterlaced Operation
Complete On-Chip Video Timing Generator
Programmable Multimode Master/Slave Operation
Macrovision Antitaping Rev 7.1 (ADV7172 Only)2
Closed Captioning Support
Teletext Insertion Port (PAL-WST)
On-Board Color Bar Generation
On-Board Voltage Reference
2-Wire Serial MPU Interface (I2C®-Compatible and Fast I2C)
Single Supply 5 V or 3.3 V Operation
Small 48-Lead LQFP Package
APPLICATIONS
High Performance DVD Playback Systems, Portable
Video Equipment including Digital Still Cameras and
Laptop PCs, Video Games, PC Video/Multimedia and
Digital Satellite/Cable Systems (Set-Top Boxes/IRD)NOTES
*This device is protected by U.S. Patent Numbers 4,631,603, 4,577,216, 4,819,098 and other intellectual property rights.ITU-R and CCIR are used interchangeably in this document (ITU-R has replaced CCIR recommendations).The Macrovision anticopy process is licensed for noncommercial home use only, which is its sole intended use in the device. Please contact sales office for latest
Macrovision version available.
SSAF is a trademark of Analog Devices, Inc.2C is a registered trademark of Philips Corporation.
GENERAL DESCRIPTIONThe ADV7172/ADV7173 is an integrated Digital Video
Encoder that converts digital CCIR-601 4:2:2 8-bit component
video data into a standard analog baseband television signal
compatible with worldwide standards.
There are six DACs available on the ADV7172/ADV7173. In
addition to the Composite output signal there is the facility to
output S-VHS Y/C Video, RGB Video and YUV Video.
The on-board SSAF (Super Sub-Alias Filter), with extended
luminance frequency response and sharp stopband attenuation,
enables studio quality video playback on modern TVs, giving
optimal horizontal line resolution. An additional sharpness control
feature allows extra luminance boost on the frequency response.
An advanced power management circuit enables optimal control
of power consumption in both normal operating modes and
power down or sleep modes. A PC’98-Compliant autodetect
feature has been added to allow the user to determine whether
or not the DACs are correctly terminated. If not, the ADV7172/
ADV7173 flags that they are not connected through the Status
bit and provides the option of automatically powering them
down, thereby reducing power consumption.
The ADV7172/ADV7173 also supports both PAL and NTSC
square pixel operation. The parts also incorporate WSS and
CGMS-A data control generation.
ADV7172/ADV7173
FUNCTIONAL BLOCK DIAGRAMThe ADV7172/ADV7173 is designed with four color controls
(hue, contrast, brightness and saturation). All YUV formats
(SMPTE/EBU N10, MII and Betacam) are supported in both
PAL and NTSC.
The output video frames are synchronized with the incoming data
Timing Reference Codes. Optionally the encoder accepts (and can
generate) HSYNC, VSYNC, and FIELD timing signals. These
timing signals can be adjusted to change pulsewidth and position
while the part is in the master mode. The Encoder requires a
single two times pixel rate (27 MHz) clock for standard opera-
tion. Alternatively the Encoder requires a 24.5454 MHz clock
for NTSC or 29.5 MHz clock for PAL square pixel mode
operation. All internal timing is generated on-chip.
HSO/CSO and VSO TTL outputs, synchronous to the analog
output video, are also available. A programmable CLAMP out-
put signal is also available to enable clamping in either the front
or back porch of the video signal.
A separate teletext port enables the user to directly input teletext
data during the vertical blanking interval.
The ADV7172/ADV7173 modes are set up over a 2-wire serial
bidirectional port (I2C-Compatible) with two slave addresses.
Functionally the ADV7173 and ADV7172 are the same with the
exception that the ADV7172 can output the Macrovision anti-
copy algorithm.
The ADV7172/ADV7173 is packaged in a 48-lead LQFP pack-
age (1.4 mm thickness).
DATA PATH DESCRIPTIONFor PAL B, D, G, H, I, M, N, and NTSC M, N modes, YCrCb
4:2:2 Data is input via the CCIR-656-Compatible Pixel Port at a
27 MHz Data Rate. The Pixel Data is demultiplexed to form
three data paths. Y typically has a range of 16 to 235, Cr, and
input data from 1 to 254 on both Y, Cb, and Cr. The ADV7172/
ADV7173 supports PAL (B, D, G, H, I, N, M) and NTSC
(with and without pedestal) standards. The Y data is then
manipulated by being scaled for contrast control and a setup
level is added for brightness control. The Cr, Cb data is also
scaled and saturation control is added. The appropriate Sync,
Blank and Burst levels are then added to the YCrCb data. Mac-
rovision AntiTaping (ADV7172 only), Closed-Captioning and
Teletext levels are also added to Y, and the resultant data is
interpolated to a rate of 27 MHz. The interpolated data is fil-
tered and scaled by three digital FIR Filters.
The U and V Signals are modulated by the appropriate sub-
carrier sine/cosine phases and a phase offset may be added onto
the color subcarrier during active video to allow hue adjustment.
The resulting U and V signals are then added together to make
up the chrominance signal. The luma (Y) signal can be delayed
1–3 luma cycles (each cycle is 74 ns) with respect to the chroma
signal. The luma and chroma signals are then added together to
make up the composite video signal. All edges are slew rate limited.
The YCrCb data is also used to generate RGB data with appro-
priate Sync and Blank levels.
There are six DACs on the ADV7172/ADV7173. Three of these
DACs are capable of providing 34.66 mA of current. The other
three DACs provide 8.66 mA each.
The six l0-bit DACs can be used to output:Composite Video + RGB Video + LUMA + CHROMA.Composite Video + YUV Video + LUMA + CHROMA.
Alternatively, each DAC can be individually powered off if not
required. A complete description of DAC output configurations
is given in Appendix 8.
Video output levels are illustrated in Appendix 6.
ADV7172/ADV7173
(VAA = 5 V � 5%1, VREF = 1.235 V, RSET1,2 = 600 � unless otherwise noted. All specifications TMIN to TMAX2
unless otherwise noted.)STATIC PERFORMANCE
VOLTAGE REFERENCE
NOTESThe max/min specifications are guaranteed over this range. The max/min values are typical over 4.75 V to 5.25 V.Temperature range TMIN to TMAX: 0°C to 70°C.Characterized by design.Full drive into 75 Ω doubly terminated load.Minimum drive current (used with buffered/scaled output load).Full drive into 150 Ω load.Specification guaranteed by characterization.IDAC is the total current (“min” corresponds to 5 mA output per DAC, “max” corresponds to 8.66 mA output per DAC) to drive DACs A, B, C, D, E, F. Turning off
individual DACs reduces IDAC correspondingly, also DACs A, B, C can be configured to output a max current of 37 mA but DAC D, E, F must be turned off.All six DACs on (DAC A, B, C, D, E, F).ICCT (Circuit Current) is the continuous current required to drive the device.Only large DACs (DACs A, B, C) on per low power mode.
5 V SPECIFICATIONS
SPECIFICATIONS
ADV7172/ADV7173–SPECIFICATIONSSTATIC PERFORMANCE
POWER REQUIREMENTS
NOTES
1The max/min specifications are guaranteed over this range. The max/min values are typical over 3.0 V to 3.6 V.
2Temperature range TMIN to TMAX: 0°C to 70°C.
3Guaranteed by characterization.
4Full drive into 75Ω doubly terminated load.
5Minimum drive current (used with buffered/scaled output load).
6Full Drive into 150 Ω load.
7Power measurements are taken with Clock Frequency = 27 MHz. Max TJ = 110°C.
8IDAC is the total current (“min” corresponds to 5 mA output per DAC, “max” corresponds to 8.66 mA output per DAC) to drive DACs A, B, C, D, E, F. Turning off
individual DACs reduces IDAC correspondingly, also DACs A, B, C can be configured to output a max current of 37 mA.
9DACs A, B, C can output 35 mA typically at 3.3 V (RSET = 150 Ω and RL = 37.5 Ω), optimum performance obtained at 18 mA DAC Current (RSET = 300 Ω and
RL = 75 Ω).
10ICCT (Circuit Current) is the continuous current required to drive the device.
11Total DAC current in Sleep Mode.
12Total continuous current during Sleep Mode.
Specifications subject to change without notice.
3.3 V SPECIFICATIONS
(VAA = 3.0 V–3.6 V1, VREF = 1.235 V, RSET1,2 = 600 � unless otherwise noted. All specifications TMIN to TMAX2
unless otherwise noted.)
ADV7172/ADV7173Differential Gain
Color Saturation Accuracy
Chroma Nonlinear Gain
Luminance Nonlinearity
NOTESThe max/min specifications are guaranteed over this range. The max/min values are typical over 4.75 V to 5.25 V range.Temperature range TMIN to TMAX: 0°C to 70°C.These specifications are for the low-pass filter only and guaranteed by design.Guaranteed by characterization.
Specifications subject to change without notice.
5 V DYNAMIC SPECIFICATIONS
(VAA = 5 V � 5%1, VREF = 1.235 V, RSET1,2 = 600 � unless otherwise noted. All
specifications TMIN to TMAX2 unless otherwise noted.)NOTES
1The max/min specifications are guaranteed over this range. The max/min values are typical over 3.0 V to 3.6 V.
2Temperature range TMIN to TMAX: 0°C to 70°C.
3Guaranteed by characterization.
4These specifications are for the low-pass filter only and guaranteed by design.
Specifications subject to change without notice.
3.3 V DYNAMIC SPECIFICATIONS
(VAA = 3.0 V–3.6 V1, VREF = 1.235 V, RSET1,2 = 600 � unless otherwise noted. All
specifications TMIN to TMAX2 unless otherwise noted.)
ADV7172/ADV7173
5 V TIMING SPECIFICATIONS
(VAA = 5 V � 5%1, VREF = 1.235 V, RSET1 = 600 � unless otherwise noted. All specifications TMIN
to TMAX2 unless otherwise noted.)ANALOG OUTPUTS
TELETEXT PORT
RESET CONTROL
NOTESThe max/min specifications are guaranteed over this range. The max/min values are typical over 4.75 V to 5.25 V.Temperature range TMIN to TMAX: 0°C to 70°C.TTL input values are 0 to 3 volts, with input rise/fall times ≤ 3 ns, measured between the 10% and 90% points. Timing reference points at 50% for inputs and
outputs. Analog output load ≤ 10 pF.Guaranteed by characterization.Output delay measured from the 50% point of the rising edge of CLOCK to the 50% point of full-scale transition.Pixel Port consists of the following:
Pixel Inputs:P7–P0
Pixel Controls:HSYNC, FIELD/VSYNC, BLANK, VSO, CSO_HSO, CLAMP
Clock Input:CLOCKTeletext Port consists of the following:
Teletext Output:TTXREQ
Teletext Input:TTX
Specifications subject to change without notice.
3.3 V TIMING SPECIFICATIONS
(VAA = 3.0 V–3.6 V1, VREF = 1.235 V, RSET1,2 = 600 �. All specifications TMIN to TMAX2 unless
otherwise noted.)ANALOG OUTPUTS
TELETEXT PORT
RESET CONTROL
NOTESThe max/min specifications are guaranteed over this range. The max/min values are typical over 3.0 V to 3.6 V.Temperature range TMIN to TMAX: 0°C to 70°C.TTL input values are 0 to 3 volts, with input rise/fall times ≤ 3 ns, measured between the 10% and 90% points. Timing reference points at 50% for inputs and
outputs. Analog output load ≤ 10 pF.Guaranteed by characterization.Output delay measured from the 50% point of the rising edge of CLOCK to the 50% point of full-scale transition.Pixel Port consists of the following:
Pixel Inputs:P7–P0
Pixel Controls:HSYNC, FIELD/VSYNC, BLANK, VSO, CSO_HSO, CLAMP
Clock Input:CLOCKTeletext Port consists of the following:
Teletext Output:TTXREQ
Teletext Input:TTX
Specifications subject to change without notice.
ADV7172/ADV7173Figure 1.MPU Port Timing Diagram
Figure 2.Pixel and Control Data Timing Diagram
Figure 3.Teletext Timing Diagram
DAC Average Current ConsumptionDAC D, E, F: The average current consumed by each DAC is the DAC output current as determined by RSET2/VREF (see Appendix 8).
DAC A, B, C: In normal power mode the average current consumed by each DAC is the DAC output current as determined by RSET1
(see Appendix 8).
In Low Power Mode the average current consumed by each DAC is approximately half the DAC output current as determined by RSET1.
Consult AN-551 for detailed information on ADV7172/ADV7173 power management.
CAUTIONESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the ADV7172/ADV7173 features proprietary ESD protection circuitry, permanent
damage may occur on devices subjected to high-energy electrostatic discharges. Therefore,
proper ESD precautions are recommended to avoid performance degradation or loss of
functionality.
ABSOLUTE MAXIMUM RATINGS1VAA to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
Voltage on Any Digital Input Pin . GND – 0.5 V to VAA + 0.5 V
Storage Temperature (TS) . . . . . . . . . . . . . . –65°C to +150°C
Junction Temperature (TJ) . . . . . . . . . . . . . . . . . . . . . . 150°C
Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . . .260°C
Analog Outputs to GND2 . . . . . . . . . . . GND – 0.5 V to VAA
NOTES
1Stresses above those listed under Absolute Maximum Ratings may cause permanent
damage to the device. This is a stress rating only; functional operation of the device
at these or any other conditions above those listed in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
2Analog output short circuit to any power supply or common can be of an
indefinite duration.
PACKAGE THERMAL PERFORMANCEThe 48-lead LQFP package is used for this device. The junc-
tion-to-ambient (θJA) thermal resistance in still air on a four
layer PCB is 54.6°C/W. The junction-to-case thermal resistance
(θJC) is 16.7°C.
To reduce power consumption when using this part the user is
advised to run the part on a 3.3 V supply, turn off any unused
DACs. However, if 5 V operation is required the user can enable
Low Power mode by setting MR16 to a Logic 1. Another alter-
native way to further reduce power is to use external buffers that
dramatically reduce the DAC currents, the current can be low-
ered to as low as 5 mA (see AN-551 and Appendix 8 for more
details) from a nominal value of 36 mA.
The user must at all times stay below the maximum junction
temperature of 110°C. The following equation shows how to
calculate this junction temperature:
Junction Temperature = [VAA (IDAC + ICCT) × θJA ] 70°C
where
IDAC = 10 mA + (sum of the average currents consumed by each
powered-on DAC).
PIN CONFIGURATION
ALSB
HSYNC
FIELD/
VSYNC
BLANK
GND
VAA
CSO
VAA
GND
SCLOCK
SDATA
SET2
DAC F
COMP1
DAC A
VAA
DAC B
VAA
GND
VAA
DAC C
DAC D
VAA
GND
DAC E
CLOCKGND
VSORESETPAL
CLAMPTTXREQSCRESET/RTC
SET1
REF
COMP2
GND
TTX
ORDERING GUIDE
ADV7172/ADV7173
PIN FUNCTION DESCRIPTIONALSB
RESET
TTX
TTXREQ
VAA
Figure 4.Luminance Internal Filter Specifications
Figure 5.Chrominance Internal Filter Specifications
Figure 6.NTSC Low-Pass Luma Filter
Figure 7.PAL Low-Pass Luma Filter
INTERNAL FILTER RESPONSEThe Y Filter supports several different frequency responses,
including two low-pass responses, two notch responses, an
Extended (SSAF) response with or without gain boost/attenuation,
a CIF response and a QCIF response. The UV Filter supports
several different frequency responses, including four low-pass
responses, a CIF response and a QCIF response. These can be
seen in Figures 4 to 18.
In Extended Mode there is the option of twelve responses
in the range from –4 dB to +4 dB. The desired response can
be chosen by the user by programming the correct value via
the I2C. The variation of frequency responses can be seen in
Figures 19 to 21.
(continued from page 2)
ADV7172/ADV7173Figure 8.NTSC Notch Luma Filter
Figure 9.PAL Notch Luma Filter
Figure 10.Extended Mode (SSAF) Luma Filter
Figure 11.CIF Luma Filter
Figure 12.QCIF Luma Filter
Figure 13.1.3 MHz Low-Pass Chroma Filter
Figure 14.0.65 MHz Low-Pass Chroma Filter
Figure 15.1.0 MHz Low-Pass Chroma Filter
Figure 16.2.0 MHz Low-Pass Chroma Filter
Figure 17.CIF Chroma Filter
Figure 18.QCIF Chroma Filter
FREQUENCY – MHz1234587
MAGNITUDE
dB
–250Figure 19.Extended Mode Luma Filter with Programmable
Gain, Negative Response
ADV7172/ADV7173Figure 20.Extended Mode Luma Filter with Programmable
Gain, Positive Response
Figure 21.Extended Mode Luma Filter with Programmable
Gain, Combined Response
COLOR BAR GENERATIONThe ADV7172/ADV7173 can be configured to generate 100/
7.5/75/7.5 color bars for NTSC or 100/0/75/0 color bars for
PAL. These are enabled by setting MR46 of Mode Register 4 to
Logic “1.”
SQUARE PIXEL MODEThe ADV7172/ADV7173 can be used to operate in square pixel
mode. For NTSC operation, an input clock of 24.5454 MHz is
required. Alternatively, for PAL operation, an input clock of
29.5 MHz is required. The internal timing logic adjusts accord-
ingly for square pixel mode operation.
COLOR SIGNAL CONTROLThe color information can be switched on and off the video
output using Bit MR44 of Mode Register 4.
BURST SIGNAL CONTROLThe burst information can be switched on and off the video
output using Bit MR45 of Mode Register 4.
NTSC PEDESTAL CONTROLThe pedestal on both odd and even fields can be controlled on a
line-by-line basis using the NTSC Pedestal Control Registers.
This allows the pedestals to be controlled during the Vertical
Blanking Interval.
COLOR CONTROLSThe ADV7172/ADV7173 allows the user the advantage of control-
ling the brightness, contrast, hue and saturation of the color.
Contrast ControlContrast adjustment is achieved by scaling the Y input data
by a factor programmed by the user into the Contrast Control
Register Bits 5–0. This factor allows the data to be scaled
between 75% and 125%.
Brightness ControlThe brightness is controlled by adding a programmable setup
level onto the scaled Y data. This brightness level may be added
onto the Y data in PAL mode, NTSC mode without pedestal or
NTSC mode with pedestal, in which case it is added directly
onto the 7.5 IRE pedestal already present.
The level added is programmed by the user into the Brightness
Control Register (Bits 4–0) and the user is capable of adding
from 0 IRE to a maximum of 14 IRE in 32 (25) steps. Because
of different gains in the datapath for each mode, different values
may need to be programmed to obtain the same IRE setup level
in each mode. Maximum brightness is achieved when 31 is
programmed into the Brightness Control Register. Table I illus-
trates the maximum setup/brightness amplitudes available in the
various modes. Note that if a level of less than 7.5 IRE is required
on the Y data in NTSC mode, then NTSC without pedestal
must be the mode selected.
Table I.Maximum Brightness Levels Available
Color Saturation ControlColor adjustment is achieved by scaling the Cr and Cb input
data by a factor programmed by the user into the Color Control
Registers 1 and 2, Bits 5–0. This factor allows the data to be
scaled between 75% and 125%.
Hue ControlThe hue adjustment is achieved on the composite and chroma
outputs by adding a phase offset onto the color subcarrier in the
active video but leaving the color burst unmodified, i.e., only
the phase between the video and the color burst is modified
and hence the hue is shifted. Hue adjustment is under the con-
trol of the Hue Control Register. The ADV7172/ADV7173
YUV LEVELSThis functionality is under the control of Mode Register 5, Bits
2–0. Bit 0 (MR50) allows the ADV7172/ADV7173 to output
SMPTE levels on the Y output when configured in NTSC mode,
and Betacam levels on the Y output when configured in PAL
mode and vice-versa.
VideoSyncBetacam286 mV714 mV
SMPTE300 mV700 mV
MII300 mV700 mV
As the datapath is branched at the output of the filters, the
luma signal relating to the CVBS or S-Video Y/C output is
unaltered. Only the Y output of the YUV outputs is scaled.
Bits 2–1 (MR52–MR51) allow UV levels to have a peak-peak
amplitude of 700 mV or 1000 mV, or the default values of
934 mV in NTSC and 700 mV in PAL.
AUTODETECT CONTROLThe ADV7172/ADV7173 provides the option of automatically
powering down the DACs A, B and C if they are not correctly
terminated (i.e., the 75 Ω cable is not connected to the DAC).
The voltage at the output of DACs A and B are compared to
a selected reference level. This reference voltage (MR64) will
depend on whether the user terminates with 37.5 Ω (75 Ω con-
nected on the DAC end and 75 Ω connected at TV end of cable,
i.e., combined load of 37.5 Ω) or 75 Ω. It cannot operate in a
DAC buffering configuration. There are two modes of auto-
detect operation provided by the ADV7172/ADV7173:
(1) Mode 0: The state of termination of the DAC may be read
by reading the status bits in Mode Register 6. MR67 status bit
indicates whether or not the composite DAC is terminated,
MR66 status bit indicates whether or not the luma DAC is
terminated. The user may then decide whether or not to power
down the DACs using MR15–MR0.
(2) Mode 1: The state of the DACs may be read as in Mode 0.
If either of the DACs is unterminated, they are automatically
powered down. If the luma DAC, DAC B is powered down then
DAC C, the chroma DAC, will also be powered down. The
state of termination of the DAC is checked each frame to decide
whether or not it is to be powered up or down.
Mode Register 6, Bits 3–2, indicates which mode of operation is
used. Note that Mode Register 1, Bits 5-3, must be enabled
(“1”) for autodetect functionality to work. (DACs A, B, C are
enabled.)
Vertical Blanking Data InsertionIt is possible to allow encoding of incoming YCbCr data on
those lines of VBI that do not have line sync or pre-/post-
equalization pulses (see Figures 24 to 25). This mode of
operation is called “Partial Blanking” and is selected by setting
MR32 to “1.” It allows the insertion of any VBI data (Opened
VBI) into the encoded output waveform. This data is present in
digitized incoming YCbCr data stream (e.g., WSS data, CGMS,
VPS etc.). Alternatively the entire VBI may be blanked (no VBI
data inserted) on these lines by setting MR32 to “0.”
SUBCARRIER RESETTogether with the SCRESET/RTC PIN and Bits MR42 and
MR41 of Mode Register 4, the ADV7172/ADV7173 can be
used in subcarrier reset mode. The subcarrier phase will reset to
Field 0 at the start of the following field when a low to high
transition occurs on this input pin.
REAL-TIME CONTROLTogether with the SCRESET/RTC PIN and Bits MR42 and
MR41 of Mode Register 4, the ADV7172/ADV7173 can be
used to lock to an external video source. The real-time control
mode allows the ADV7172/ADV7173 to automatically alter the
subcarrier frequency to compensate for line length variation.
When the part is connected to a device that outputs a digital
data stream in the RTC format (such as a ADV7185 video
decoder, see Figure 22), the part will automatically change to
the compensated subcarrier frequency on a line-by-line basis.
This digital data stream is 67 bits wide and the subcarrier is
contained in Bits 0 to 21. Each bit is two clock cycles long. 00Hex
should be written into all four subcarrier frequency registers
when using this mode.
VIDEO TIMING DESCRIPTIONThe ADV7172/ADV7173 is intended to interface to off-the-
shelf MPEG1 and MPEG2 Decoders. As a consequence, the
ADV7172/ADV7173 accepts 4:2:2 YCrCb Pixel Data via a
CCIR-656 pixel port and has several video timing modes of
operation that allow it to be configured as either system master
video timing generator or a slave to the system video timing
generator. The ADV7172/ADV7173 generates all of the required
horizontal and vertical timing periods and levels for the analog
video outputs.
The ADV7172/ADV7173 calculates the width and placement
of analog sync pulses, blanking levels and color burst envelopes.
Color bursts are disabled on appropriate lines and serration and
equalization pulses are inserted where required.
In addition, the ADV7172/ADV7173 supports a PAL or NTSC
square pixel operation in slave mode. The part requires an input
pixel clock of 24.5454 MHz for NTSC and an input pixel clock
of 29.5 MHz for PAL. The internal horizontal line counters place
the various video waveform sections in the correct location for
the new clock frequencies.
The ADV7172/ADV7173 has four distinct master and four
distinct slave timing configurations. Timing control is estab-
lished with the bidirectional SYNC, BLANK, and FIELD/
VSYNC pins. Timing Mode Register 1 can also be used to
vary the timing pulsewidths and where they occur in relation to
each other.
ADV7172/ADV7173Figure 22.RTC Timing and Connections
Mode 0 (CCIR–656):Slave Option(Timing Register 0 TR0 = X X X X X 0 0 0)
The ADV7172/ADV7173 is controlled by the SAV (Start Active Video) and EAV (End Active Video) Time Codes in the Pixel Data.
All timing information is transmitted using a 4-byte Synchronization Pattern. A synchronization pattern is sent immediately before
and after each line during active picture and retrace. Mode 0 is illustrated in Figure 23. The HSYNC, FIELD/VSYNC, and BLANK
(if not used) pins should be tied high during this mode.
Figure 23.Timing Mode 0 (Slave Mode)
Mode 0 (CCIR–656):Master Option(Timing Register 0 TR0 = X X X X X 0 0 1)
The ADV7172/ADV7173 generates H, V, and F signals required for the SAV (Start Active Video) and EAV (End Active Video)
Time Codes in the CCIR656 standard. The H bit is output on the HSYNC pin, the V bit is output on the BLANK pin and the F bit
is output on the FIELD/VSYNC pin. Mode 0 is illustrated in Figure 24 (NTSC) and Figure 25 (PAL). The H, V, and F transitions
relative to the video waveform are illustrated in Figure 26.
Figure 24.Timing Mode 0 (NTSC Master Mode)
ADV7172/ADV7173Figure 26.Timing Mode 0 Data Transitions (Master Mode)
Mode 1:Slave Option HSYNC, BLANK, FIELD(Timing Register 0 TR0 = X X X X X 0 1 0)
In this mode the ADV7172/ADV7173 accepts horizontal SYNC and Odd/ Even FIELD signals. A transition of the FIELD input
when HSYNC is low indicates a new frame, i.e., Vertical Retrace. The BLANK signal is optional. When the BLANK input is dis-
abled, the ADV7172/ADV7173 automatically blanks all normally blank lines as per CCIR-624. Mode 1 is illustrated in Figure 27
(NTSC) and Figure 28 (PAL).
Figure 27.Timing Mode 1 (NTSC)
Figure 28.Timing Mode 1 (PAL)
Mode 1:Master Option HSYNC, BLANK, FIELD(Timing Register 0 TR0 = X X X X X 0 1 1)
In this mode the ADV7172/ADV7173 can generate horizontal SYNC and Odd/Even FIELD signals. A transition of the FIELD
input when HSYNC is low indicates a new frame, i.e., vertical retrace. The BLANK signal is optional. When the BLANK input is
disabled, the ADV7172/ADV7173 automatically blanks all normally blank lines as per CCIR-624. Pixel data is latched on the rising
clock edge following the timing signal transitions. Mode 1 is illustrated in Figure 27 (NTSC) and Figure 28 (PAL). Figure 29 illus-
trates the HSYNC, BLANK, and FIELD for an odd-or-even field transition relative to the pixel data.
Figure 29.Timing Mode 1 Odd/Even Field Transitions Master/Slave
ADV7172/ADV7173
Mode 2:Slave Option HSYNC, VSYNC, BLANK(Timing Register 0 TR0 = X X X X X 1 0 0)
In this mode the ADV7172/ADV7173 accepts horizontal and vertical SYNC signals. A coincident low transition of both HSYNC and
VSYNC inputs indicates the start of an odd field. A VSYNC low transition when HSYNC is high indicates the start of an Even Field.
The BLANK signal is optional. When the BLANK input is disabled, the ADV7172/ADV7173 automatically blanks all normally
blank lines as per CCIR-624. Mode 2 is illustrated in Figure 30 (NTSC) and Figure 31 (PAL).
Figure 30.Timing Mode 2 (NTSC)
Figure 31.Timing Mode 2 (PAL)
Mode 2:Master Option HSYNC, VSYNC, BLANK(Timing Register 0 TR0 = X X X X X 1 0 1)
In this mode the ADV7172/ADV7173 can generate horizontal and vertical SYNC signals. A coincident low transition of both
HSYNC and VSYNC inputs indicates the start of an odd field. A VSYNC low transition when HSYNC is high indicates the start of
an even field. The BLANK signal is optional. When the BLANK input is disabled, the ADV7172/ADV7173 automatically blanks all
normally blank lines as per CCIR-624. Mode 2 is illustrated in Figure 30 (NTSC) and Figure 31 (PAL). Figure 32 illustrates the
HSYNC, BLANK, and VSYNC for an even-to-odd field transition relative to the pixel data. Figure 33 illustrates the HSYNC,
BLANK, and VSYNC for an odd-to-even field transition relative to the pixel data.
Figure 32.Timing Mode 2 Even-to-Odd Field Transition Master/Slave
Figure 33.Timing Mode 2 Odd-to-Even Field Transition Master/Slave
ADV7172/ADV7173
Mode 3:Master/Slave Option HSYNC, BLANK, FIELD(Timing Register 0 TR0 = X X X X X 1 1 0 or X X X X X 1 1 1)
In this mode the ADV7172/ADV7173 accepts or generates horizontal SYNC and Odd/Even FIELD signals. A transition of the
FIELD input when HSYNC is high indicates a new frame, i.e., vertical retrace. The BLANK signal is optional. When the BLANK
input is disabled, the ADV7172/ADV7173 automatically blanks all normally blank lines as per CCIR-624. Mode 3 is illustrated in
Figure 34 (NTSC) and Figure 35 (PAL).
Figure 34.Timing Mode 3 (NTSC)
POWER-ON RESETAfter power-up, it is necessary to execute a reset operation. A
reset occurs on the falling edge of a high-to-low transition on
the RESET pin. This initializes the pixel port such that the pixel
inputs P7–P0 are not selected. After reset, the ADV7172/
ADV7173 is automatically set up to operate in NTSC/PAL mode,
depending on the PAL_NTSC pin. The subcarrier frequency
registers are automatically loaded with the correct values for
PAL or NTSC. All other registers, with the exception of Mode
Registers 1 and 2, are set to 00H. Mode Register 1 is set to 07H.
This is to ensure DACs D, E, and F are ON after power-up.
All bits of Mode Register 2 are set to “0,” with the exception of
Bit 3 (i.e., Mode Register 2 reads 08H). Bit MR23 of Mode
Register 2 is set to Logic “1.” This enables the 7.5 IRE pedestal.
RESET SEQUENCEWhen RESET becomes active, the ADV7172/ADV7173 reverts
to the default output configuration. DACs A, B, C are off and
DACs D, E, F are powered on and output composite, luma and
chroma signals respectively. Mode Register 2, Bit 6 (MR26),
resets to “0.” The ADV7172/ADV7173 internal timing is under
the control of the logic level on the NTSC_PAL pin.
When RESET is released Y, Cr, Cb values corresponding to a
black screen are input to the ADV7172/ADV7173. Output
timing signals are still suppressed at this stage.
When the user requires valid data, MR26 is set to “1” to allow
the valid pixel data to pass through the encoder. Digital output
timing signals become active and the encoder timing is now
under the control of the timing registers. If, at this stage, the
user wishes to select a video standard different from that on the
NTSC_PAL pin, Mode Register 2, Bit 5 (MR25) is set (“1”)
and the video standard required is selected by programming
Mode Register 0. Figure 36 illustrates the reset sequence timing.
SLEEP MODEIf after reset the SCRESET/RTC and NTSC_PAL pins are
both set to high, the part ADV7172/ADV7173 will power-up
in sleep mode to facilitate low power consumption before all
registers have been initialized. If Mode Register 6, Bit 0 (MR60) is
then set to (“1”) sleep mode control passes to Mode Register 2,
Bit 7 (i.e., control via I2C).
SCH PHASE MODEThe SCH phase is configured in default mode to reset every
four (NTSC) or eight (PAL) fields to avoid an accumulation of
SCH phase error over time. In an ideal system, zero SCH phase
error would be maintained forever, but in reality, this is impos-
sible to achieve due to clock frequency variations. This effect is
reduced by the use of a 32-bit DDS, which generates this SCH.
Resetting the SCH phase every four or eight fields avoids the
accumulation of SCH phase error, and results in very minor
SCH phase jumps at the start of the four or eight field sequence.
Resetting the SCH phase should not be done if the video source
does not have stable timing or the ADV7172/ADV7173 is con-
figured in RTC mode (MR41 = “1” and MR42 = “1”). Under
these conditions (unstable video) the subcarrier phase reset should
be enabled (MR42 = “0” and MR41 = “1”) but no reset applied.
In this configuration the SCH phase will never be reset, which
that the output video will now track the unstable input video.
The subcarrier phase reset when applied will reset the SCH
phase to Field 0 at the start of the next field (e.g., subcarrier
phase reset applied in Field 5 (PAL) on the start of the next
field SCH phase will be reset to Field 0).
Figure 36.RESET Sequence Timing Diagram
ADV7172/ADV7173
CSO, HSO, AND VSO OUTPUTSThe ADV7172/ADV7173 supports three timing signals, CSO
(composite sync signal), HSO (horizontal sync signal) and VSO
(vertical sync signal). These output TTL signals are aligned with
the analog video outputs. HSO and CSO are shared on Pin 10.
Mode Register 7, Bit MR75 can be used to configure this out-
put pin. See Figure 37 for an example of these waveforms.
CLAMP OUTPUTThe ADV7172/ADV7173 has a programmable clamp TTL
output signal. The clamp signal is programmable to the front
and back porch. Mode Register 5, Bit MR57 can be used to
control the porch position. Also the position of the clamp signal
can be varied by 1–3 clock cycles in a positive and negative
direction from the default position. Mode Register 5, Bits MR56,
MR55, and MR54 control this position.
Figure 38.Clamp Output Timing
MPU PORT DESCRIPTIONThe ADV7172 and ADV7173 support a 2-wire serial (I2C-
Compatible) microprocessor bus driving multiple peripherals.
Two inputs serial data (SDATA) and serial clock (SCLOCK)
carry information between any device connected to the bus.
Each slave device is recognized by a unique address. The
ADV7172 and ADV7173 each have four possible slave addresses
for both read and write operations. These are unique addresses
for each device and are illustrated in Figure 39 and Figure 40.
The LSB sets either a read or write operation. Logic Level
“1” corresponds to a read operation while Logic Level “0”
corresponds to a write operation. A1 is set by setting the ALSB
pin of the ADV7172/ADV7173 to Logic Level “0” or Logic
Level “1.” When ALSB is set to “0,” there is greater bandwidth
on the I2C lines, which allows high-speed data transfers on this
width on the I2C lines, which means that impulses of less
than 50 ns will not pass into the I2C internal controller. This
mode is recommended for noisy systems.
Figure 39.ADV7172 Slave Address
Figure 40.ADV7173 Slave Address
To control the various devices on the bus the following protocol
must be followed. First the master initiates a data transfer by
establishing a start condition, defined by a high-to-low transition
on SDATA while SCLOCK remains high. This indicates that
an address/data stream will follow. All peripherals respond to
the Start condition and shift the next eight bits (7-bit address +
R/W bit). The bits are transferred from MSB down to LSB. The
peripheral that recognizes the transmitted address responds by
pulling the data line low during the ninth clock pulse. This is
known as an acknowledge bit. All other devices withdraw from
the bus at this point and maintain an idle condition. The idle
condition is where the device monitors the SDATA and SCLOCK
lines waiting for the Start condition and the correct transmitted
address. The R/W bit determines the direction of the data. A
Logic “0” on the LSB of the first byte means that the master
will write information to the peripheral. A Logic “1” on the LSB
of the first byte means that the master will read information
from the peripheral.
Figure 37.CSO, HSO, VSO Timing Diagram
The ADV7172/ADV7173 acts as a standard slave device on the
bus. The data on the SDATA pin is eight bits long, supporting
the 7-bit addresses plus the R/W bit. It interprets the first byte
as the device address and the second byte as the starting sub-
address. The subaddresses auto increment allows data to be
written to or read from the starting subaddress. A data transfer
is always terminated by a stop condition. The user can also
access any unique subaddress register on a one-by-one basis
without having to update all the registers. There is one excep-
tion. The subcarrier frequency registers should be updated in
sequence, starting with Subcarrier Frequency Register 0. The
auto increment function should then be used to increment and
access Subcarrier Frequency Registers 1, 2 and 3. The subcarrier
frequency registers should not be accessed independently.
Stop and Start conditions can be detected at any stage during
the data transfer. If these conditions are asserted out of sequence
with normal read and write operations, then these cause an
immediate jump to the idle condition. During a given SCLOCK
high period, the user should issue only one start condition, one
stop condition or a single stop condition followed by a single start
condition. If an invalid subaddress is issued by the user, the
ADV7172/ADV7173 will not issue an acknowledge and will
return to the idle condition. If, in autoincrement mode, the user
exceeds the highest subaddress, the following action will be taken:In Read Mode the highest subaddress register contents
will continue to be output until the master device issues
a no-acknowledge. This indicates the end of a read. A
no-acknowledge condition is where the SDATA line is not
pulled low on the ninth pulse.In Write Mode, the data for the invalid byte will not be loaded
into any subaddress register, a no-acknowledge will be issued
by the ADV7172/ADV7173 and the part will return to the
idle condition.
Figure 41 illustrates an example of data transfer for a read
sequence and the Start and Stop conditions.
Figure 41.Bus Data Transfer
Figure 42 shows bus write and read sequences.
REGISTER ACCESSESThe MPU can write to or read from all of the registers of the
ADV7172/ADV7173 except the Subaddress Register, which is a
write-only register. The Subaddress Register determines which
register the next read or write operation accesses. All communi-
cations with the part through the bus start with an access to the
Subaddress Register. A read/write operation is then performed
from/to the target address, which then increments to the next
address until a Stop command on the bus is performed.
REGISTER PROGRAMMINGThe following section describes each register, including subaddress
register, mode registers, subcarrier frequency registers, subcar-
rier phase register, timing registers, closed captioning extended
data registers, closed captioning data registers, NTSC pedestal
Control/PAL teletext control registers, CGMS/WSS registers,
contrast register, U- or V-scale registers, hue adjust register,
brightness control register and sharpness control register in
terms of its configuration. All registers can be read from as well
as written to.
Figure 42.Write and Read Sequences
ADV7172/ADV7173
Subaddress Register (SR7–SR0)The communications register is an 8-bit write-only register. After
the part has been accessed over the bus and a read/write opera-
tion is selected, the subaddress is set up. The subaddress register
determines to/from which register the operation takes place.
Figure 43 shows the various operations under the control of the
subaddress register. “0” should always be written to SR7.
Register Select (SR6–SR0)These bits are set up to point to the required starting address.
Figure 43.Subaddress Register
MODE REGISTER 0 MR0 (MR07–MR00)
(Address (SR4–SR0) = 00H)Figure 44 shows the various operations under the control of
Mode Register 0.
MR0 BIT DESCRIPTION
Output Video Standard Selection (MR01–MR00)These bits are used to set up the encoder mode. The ADV7172/
ADV7173 can be set up to output NTSC, PAL (B, D, G, H, I),
PAL M or PAL N standard video.
Luma Filter Select (MR02–MR04)These bits specify which luma filter is to be selected. The
filter selection is made independent of whether PAL or
NTSC is selected.
Chroma Filter Select (MR05–MR07)These bits select the chroma filter. A low-pass filter can be
selected with a choice of cutoff frequencies (0.65 MHz, 1.0 MHz,
1.3 MHz, or 2 MHz), along with a choice of CIF or QCIF filters.
MODE REGISTER 1 MR1 (MR17–MR10)
(Address (SR4–SR0) = 01H)Figure 45 shows the various operations under the control of
Mode Register 1.
MR1 BIT DESCRIPTION
DAC Control (MR15–MR10)MR15–MR10 bits can be used to power down the DACs. This
can be used to reduce the power consumption of the ADV7172/
ADV7173 if any of the DACs are not required in the application.
Low Power Mode Control (MR16)This bit enables the lower power mode of the ADV7172/
ADV7173. This will reduce by approximately 50% the average
supply current consumed by each large DAC which is powered
on. For each DAC in low power mode, the relationship between
RSET1/VREF and the output current is unchanged by this (see
Appendix 8). This bit is only relevant to the larger DACs,
DACs A, B, and C. DACs D, E, and F are not affected by this
low power mode.
Reserved (MR17)A Logic “0” must be written to this bit.
Figure 44.Mode Register 0 (MR0)
ADV7172/ADV7173
MODE REGISTER 2 MR2 (MR27–MR20)
(Address (SR4–SR0) = 02H)Mode Register 2 is an 8-bit-wide register.
Figure 46 shows the various operations under the control of
Mode Register 2.
MR2 BIT DESCRIPTION
RGB/YUV Control (MR20)This bit enables the output from the DACs to be set to YUV or
RGB output video standard.
Large DACs Control (MR21)This bit controls the output from DACs A, B, and C. When this
bit is set to “1,” composite, luma, and chroma signals are output
from DACs A, B, and C (respectively). When this bit is set to
“0,” RGB or YUV may be output from these DACs.
SCART Enable Control (MR22)This bit is used to switch the DAC outputs from SCART to a
EuroSCART configuration. A complete table of all DAC output
configurations is shown in Table II.
Pedestal Control (MR23)This bit specifies whether a pedestal is to be generated on the
NTSC composite video signal. This bit is invalid in the PAL mode.
Square Pixel Control (MR24)This bit is used to set up square pixel mode. This is available in
slave mode only. For NTSC, a 24.54 MHz clock must be
supplied. For PAL, a 29.5 MHz clock must be supplied.
Standard I2C Control (MR25)This bit controls the video standard used by the ADV7172/
ADV7173. When this bit is set to “1,” the video standard bits
programmed in Mode Register 0, Bits 0–1, indicate the video
standard. When this bit is set to “0,” the ADV7172/ADV7173
is forced into the standard selected by the NTSC_PAL pin.
Pixel Data Valid Control (MR26)After reset, this bit has the value “0” and the pixel data input to
the encoder is blanked such that a black screen is output from
the DACs. The ADV7172/ADV7173 will be set to master mode
timing. When this bit is set to “1” by the user (via the I2C),
pixel data passes to the pins and the encoder reverts to the
timing mode defined by Timing Mode Register 0.
Sleep Mode Control (MR27)When this bit is set (“1”), sleep mode is enabled. With this
mode enabled the ADV7172/ADV7173 power consumption is
reduced to less than 20 µA. The I2C registers can be written to
and read from when the ADV7172/ADV7173 is in sleep mode.
If “0” is written to MR27 when the device is in sleep mode, the
ADV7172/ADV7173 will come out of sleep mode and resume
normal operation. Also, if the reset signal is applied during sleep
mode, the ADV7172/ADV7173 will come out of sleep mode
and resume normal operation. This mode will only operate
when MR60 is set to a Logic “1”; otherwise sleep mode is con-
trolled by the PAL_NTSC and SCRESET/RTC pin.
Figure 46.Mode Register 2 (MR2)
Table II.DAC Output Configuration Matrix
Figure 47.Mode Register 3 (MR3)
MODE REGISTER 3 MR3 (MR37–MR30)
(Address (SR4–SR0) = 03H)Mode Register 3 is an 8-bit-wide register. Figure 47 shows the
various operations under the control of Mode Register 3.
MR3 BIT DESCRIPTION
Revision Code (MR31–MR30)This bit is read-only and indicates the revision of the device.
VBI_Open (MR32)This bit determines whether or not data in the vertical blank-
ing interval (VBI) is output to the analog outputs or blanked.
VBI_Open is available in all timing modes. Also, if both BLANK
input (TR03) and VBI_Open are enabled, TR03 takes priority.
Teletext Enable (MR33)This bit must be set to “1” to enable teletext data insertion on
the TTX pin.
TTXRQ Bit Mode Control (MR34)This bit enables switching of the teletext request signal from a
continuous high signal (MR34 = “0”) to a bit wise request
signal (MR34 = “1”).
Closed Captioning Field Selection (MR36–MR35)These bits control the fields that closed captioning data is dis-
played on. Closed captioning information can be displayed on
an odd field, even field, or both fields.
Active Video Filter (MR37)This bit controls the filter mode applied outside the active video
portion of the line. This filter ensures that the sync rise and
fall times are always on spec regardless of which luma filter
is selected.
ADV7172/ADV7173
MODE REGISTER 4 MR4 (MR47–MR40)
(Address (SR4–SR0) = 04H)Mode Register 4 is a 8-bit wide register. Figure 48 shows the
various operations under the control of Mode Register 4.
MR4 BIT DESCRIPTION
VSYNC_3H (MR40)When this bit is enabled (“1”) in slave mode, it is possible to
drive the VSYNC active low input for 2.5 lines in PAL mode
and 3 lines in NTSC mode. When this bit is enabled in master
mode, the ADV7172/ADV7173 outputs an active low VSYNC
signal for 3 lines in NTSC mode and 2.5 lines in PAL mode.
Genlock Selection (MR42–MR41)These bits control the genlock feature of the ADV7172/ADV7173.
Setting MR41 to Logic “0” disables the SCRESET/RTC pin
and allows the ADV7172/ADV7173 to operate in normal mode.
By setting MR41 to “1,” one of two operations may be enabled:If MR42 is set to “0,” the SCRESET/RTC pin is configured
as a subcarrier reset input and the subcarrier phase will reset
to Field 0 whenever a low-to-high field transition is detected
on the SCRESET/RTC pin.If MR42 is set to “1,” the SCRESET/RTC pin is configured
as a real-time control input and the ADV7172/ADV7173 can
be used to lock to an external video source.
Active Video Line Duration (MR43)This bit switches between two active video line durations. A
“0” selects CCIR REC 601 (720 pixels PAL/NTSC) and a “1”
selects ITU-R.BT 470 “analog” standard for active video dura-
tion (710 pixels NTSC, 702 pixels PAL).
Chrominance Control (MR44)This bit enables the color information to be switched on and off
the video output.
Burst Control (MR45)This bit enables the color burst information to be switched on
and off the video output.
Color Bar Control (MR46)This bit can be used to generate and output an internal color
bar test pattern. The color bar configuration is 100/7.5/75/7.5
for NTSC and 100/0/75/0 for PAL. It is important to note that
when color bars are enabled, the ADV7172/ADV7173 is config-
ured in a master timing mode. The output pins VSYNC/FIELD,
HSYNC and BLANK are three-state during color bar mode.
Interlaced Mode Control (MR47)This bit is used to set up the output to interlaced or noninter-
laced mode.
Figure 48.Mode Register 4 (MR4)
