ADV7171KSUZ-REEL , Digital PAL/NTSC Video Encoder
ADV7172 ,Digital PAL/NTSC Video Encoder with Six DACs (10 Bits), Color Control, Power Management, Macrovision 7.01GENERAL DESCRIPTIONMultistandard Video Output Support:The ADV7172/ADV7173 is an integrated Digital ..
ADV7172KST ,Digital PAL/NTSC Video Encoder with Six DACs 10 Bits, Color Control and Enhanced Power ManagementSPECIFICATIONSunless otherwise noted)1Parameter Test Conditions Min Typ Max UnitsSTATIC PERFORMANCE ..
ADV7173 ,Digital PAL/NTSC Video Encoder with Six DACs (10 Bits), Color Control and Enhanced Power ManagementSPECIFICATIONS1Parameter Test Conditions Min Typ Max UnitSTATIC PERFORMANCEResolution (Each DAC) 10 ..
ADV7173KSTZ ,Digital PAL/NTSC Video Encoder with Six DACs (10 Bits), Color Control and Enhanced Power ManagementGENERAL DESCRIPTIONMultistandard Video Output Support:The ADV7172/ADV7173 is an integrated Digital ..
ADV7174KCP-REEL ,Chip Scale PAL/NTSC Video Encoder with Advanced Power ManagementFeatures .. 16 Timing Mode Register 0 (TR0) ... 33 Color Bar Generation . 16 Timing Mode Register 1 ..
AM27C512-200JI , 512 Kilobit ( 64 K x 8-Bit ) CMOS EPROM Speed options as fast as 55 ns
AM27C512-200LC , 512 Kilobit ( 64 K x 8-Bit ) CMOS EPROM Speed options as fast as 55 ns
AM27C512-255DI , 512 Kilobit ( 64 K x 8-Bit ) CMOS EPROM Speed options as fast as 55 ns
AM27C512-55DC , 512 Kilobit ( 64 K x 8-Bit ) CMOS EPROM Speed options as fast as 55 ns
AM27C512-55DI , 512 Kilobit (64 K x 8-Bit) CMOS EPROM
AM27C512-70DI , 512 Kilobit ( 64 K x 8-Bit ) CMOS EPROM Speed options as fast as 55 ns
ADV7170KSU-ADV7170KSU-REEL-ADV7170KSUZ-ADV7171KSU-ADV7171KSU-REEL-ADV7171KSUZ
Digital PAL/NTSC Video Encoder with 10-Bit SAFF™ and Advanced Power Management & Macrovision 7.01
REV.A
Digital PAL/NTSC Video Encoder with 10-Bit
SSAF™ and Advanced Power Management
FUNCTIONAL BLOCK DIAGRAM
SCLOCKSDATAALSB
HSYNC
FIELD/VSYNC
BLANK
CLOCKGND
DAC D (PIN 27)
DAC A (PIN 32)
VREF
RSET
COMP
COLOR
DATA
P7–P0
P15–P8
SCRESET/RTC
DAC C (PIN 26)
DAC B (PIN 31)
VAA
RESET
TTXREQTTX
FEATURES
ITU-R2 BT601/656 YCrCb to PAL/NTSC Video Encoder
High Quality 10-Bit Video DACs
SSAF (Super Sub-Alias Filter)
Advanced Power Management Features
CGMS (Copy Generation Management System)
WSS (Wide Screen Signalling)
Simultaneous Y, U, V, C Output Format
NTSC-M, PAL-M/N3, PAL-B/D/G/H/I, PAL-60
Single 27 MHz Clock Required (�2 Oversampling)
80 dB Video SNR
32-Bit Direct Digital Synthesizer for Color Subcarrier
Multistandard Video Output Support:
Composite (CVBS)
Component S-Video (Y/C)
Component YUV and RGB
EuroSCART Output (RGB + CVBS/LUMA)
Component YUV + CHROMA
Video Input Data Port Supports:
CCIR-656 4:2:2 8-Bit Parallel Input Format
4:2:2 16-Bit Parallel Input Format
Programmable Simultaneous Composite
and S-Video or RGB (SCART)/YUV Video Outputs
Programmable Luma Filters (Low-Pass [PAL/NTSC])
Notch, Extended (SSAF, CIF, and QCIF)
Programmable Chroma Filters (Low-Pass [0.65 MHz,
1.0 MHz, 1.2 MHz and 2.0 MHz], CIF and QCIF)
Programmable VBI (Vertical Blanking Interval)
Programmable Subcarrier Frequency and Phase
Programmable LUMA Delay
Individual ON/OFF Control of Each DAC
CCIR and Square Pixel Operation
Integrated Subcarrier Locking to External Video Source
Color Signal Control/Burst Signal Control
Interlaced/Noninterlaced Operation
Complete On-Chip Video Timing Generator
Programmable Multimode Master/Slave Operation
Macrovision AntiTaping Rev 7.1 (ADV7170 Only)4
Closed Captioning Support
Teletext Insertion Port (PAL-WST)
On-Board Color Bar Generation
On-Board Voltage Reference
2-Wire Serial MPU Interface (I2C®-Compatible and Fast I2C)
Single Supply 5 V or 3.3 V Operation
Small 44-Lead MQFP/TQFP Packages
APPLICATIONS
High-Performance DVD Playback Systems, Portable
Video Equipment Including Digital Still Cameras and
Laptop PCs, Video Games, PC Video/Multimedia and
Digital Satellite/Cable Systems (Set-Top Boxes/IRD)NOTES
1. Patent Numbers 5,343,196 and 5,442,355 and other intellectual property rights.
2ITU-R and CCIR are used interchangeably in this document (ITU-R has replaced CCIR recommendations).
3Throughout the document N is referenced to PAL- Combination -N.
4This device is protected by U.S. Patent Numbers 4,631,603, 4,577,216, 4,819,098 and other intellectual property rights. The Macrovision anticopy process is
licensed for noncommercial home use only, which is its sole intended use in the device. Please contact sales office for latest Macrovision version available.
SSAF is a trademark of Analog Devices, Inc.
I2C is a registered trademark of Philips Corporation.
ADV7170/ADV7171–SPECIFICATIONS
(VAA = 5 V � 5%1, VREF = 1.235 V, RSET = 150 �. All specifications TMIN to TMAX2 unless otherwise noted.)STATIC PERFORMANCE
NOTESThe max/min specifications are guaranteed over this range. The max/min values are typical over 4.75 V to 5.25 V.Temperature range TMIN to TMAX: 0°C to 70°C.Full drive into 37.5Ω doubly terminated load.Minimum drive current (used with buffered/scaled output load).Power measurements are taken with Clock Frequency = 27 MHz. Max TJ = 110°C.IDAC is the total current (min corresponds to 5 mA output per DAC, max corresponds to 37 mA output per DAC) to drive all four DACs. Turning off individual
DACs reduces IDAC correspondingly.ICCT (Circuit Current) is the continuous current required to drive the device.Total DAC current in Sleep Mode.Total continuous current during Sleep Mode.
Specifications subject to change without notice.
5 V SPECIFICATIONS
ADV7170/ADV7171NOTESThe max/min specifications are guaranteed over this range. The max/min values are typical over 3.0 V to 3.6 V.Temperature range TMIN to TMAX: 0°C to 70°C.Guaranteed by characterization.Full drive into 37.5Ω load.DACs can output 35 mA typically at 3.3 V (RSET = 150 Ω and RL = 37.5 Ω), optimum performance obtained at 18 mA DAC current (RSET = 300 Ω and RL = 75 Ω).Minimum drive current (used with buffered/scaled output load).Power measurements are taken with Clock Frequency = 27 MHz. Max TJ = 110°C.IDAC is the total current (min corresponds to 5 mA output per DAC, max corresponds to 38 mA output per DAC) to drive all four DACs. Turning off individual
DACs reduces IDAC correspondingly.ICCT (Circuit Current) is the continuous current required to drive the device.Total DAC current in Sleep Mode.Total continuous current during Sleep Mode.
Specifications subject to change without notice.
3.3 V SPECIFICATIONS(VAA = 3.0 V – 3.6 V1, VREF = 1.235 V, RSET = 150 �. All specifications TMIN to TMAX2 unless otherwise noted.)
ADV7170/ADV7171–SPECIFICATIONSDifferential Gain
Color Saturation Accuracy
Chroma Nonlinear Gain
Chroma/Luma Intermod
Chroma/Luma Gain Inequality
Chroma/Luma Delay Inequality
Luminance Nonlinearity
Chroma AM Noise
NOTESThe max/min specifications are guaranteed over this range. The max/min values are typical over 4.75 V to 5.25 V.Temperature range TMIN to TMAX: 0°C to 70°C.Guaranteed by characterization.The low pass filter only and guaranteed by design.
Specifications subject to change without notice.
5 V DYNAMIC SPECIFICATIONS
(VAA = 5 V � 5%1, VREF = 1.235 V, RSET = 150 �. All specifications TMIN to TMAX2 unless
otherwise noted.)NOTES
1The max/min specifications are guaranteed over this range. The max/min values are typical over 4.75 V to 5.25 V.
2Temperature range TMIN to TMAX: 0°C to 70°C.
3Guaranteed by characterization.
4These specifications are for the low-pass filter only and guaranteed by design. For other internal filters, see Figure 4.
Specifications subject to change without notice.
3.3 V DYNAMIC SPECIFICATIONS
(VAA = 3.0 V – 3.6 V1, VREF = 1.235 V, RSET = 150 �. All specifications TMIN to TMAX2 unless
otherwise noted.)
5 V TIMING SPECIFICATIONS
(VAA = 4.75 V – 5.25 V1, VREF = 1.235 V, RSET = 150 �. All specifications TMIN to TMAX2 unless
otherwise noted.)NOTESThe max/min specifications are guaranteed over this range. The max/min values are typical over 4.75 V to 5.25 V range.Temperature range TMIN to TMAX: 0°C to 70°C.TTL input values are 0 to 3 volts, with input rise/fall times ≤ 3 ns, measured between the 10% and 90% points. Timing reference points at 50% for inputs and
outputs. Analog output load ≤ 10 pF.Guaranteed by characterization.Output delay measured from the 50% point of the rising edge of CLOCK to the 50% point of full-scale transition.Pixel Port consists of the following:
Pixel Inputs:P15–P0
Pixel Controls:HSYNC, FIELD/VSYNC, BLANK
Clock Input:CLOCKTeletext Port consists of the following:
Teletext Output:TTXREQ
Teletext Input:TTX
Specifications subject to change without notice.
ADV7170/ADV7171
3.3 V TIMING SPECIFICATIONS
(VAA = 3.0 V – 3.6 V1, VREF = 1.235 V, RSET = 150 �. All specifications TMIN to TMAX2 unless
otherwise noted.)TELETEXT
RESET CONTROL
NOTESThe max/min specifications are guaranteed over this range. The max/min values are typical over 3.0 V to 3.6 V range.Temperature range TMIN to TMAX: 0oC to 70oC.TTL input values are 0 to 3 volts, with input rise/fall times ≤ 3 ns, measured between the 10% and 90% points. Timing reference points at 50% for inputs and
outputs. Analog output load ≤ 10 pF.Guaranteed by characterization.Output delay measured from the 50% point of the rising edge of CLOCK to the 50% point of full-scale transition.Pixel Port consists of the following:
Pixel Inputs:P15–P0
Pixel Controls:HSYNC, FIELD/VSYNC, BLANK
Clock Input:CLOCKTeletext Port consists of the following:
Teletext Output:TTXREQ
Teletext Input:TTX
Specifications subject to change without notice.
Figure 1.MPU Port Timing Diagram
Figure 2.Pixel and Control Data Timing Diagram
Figure 3.Teletext Timing Diagram
ADV7170/ADV7171
CAUTIONESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
ABSOLUTE MAXIMUM RATINGS1VAA to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
Voltage on Any Digital Input Pin . GND – 0.5 V to VAA + 0.5 V
Storage Temperature (TS) . . . . . . . . . . . . . . –65°C to +150°C
Junction Temperature (TJ) . . . . . . . . . . . . . . . . . . . . . . 150°C
Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . . 260°C
Analog Outputs to GND2 . . . . . . . . . . . GND – 0.5 V to VAA
NOTESStresses above those listed under Absolute Maximum Ratings may cause permanent
damage to the device. This is a stress rating only; functional operation of the device
at these or any other conditions above those listed in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.Analog output short circuit to any power supply or common can be of an indefinite
duration.
PACKAGE THERMAL PERFORMANCEThe 44-MQFP package used for this device takes advantage of
an ADI patented thermal coastline lead frame construction. This
maximizes heat transfer into the leads and reduces the package
thermal resistance.
For the MQFP package the junction-to-ambient (θJA) thermal
resistance in still air on a four-layer PCB is 35.5°C/W. The
junction-to-case thermal resistance (θJC) is 13.75°C/W. For the
TQFP package θJA in still air on a four-layer PCB is 53.2°C/W.
θJC is 11.1°C/W.
ORDERING GUIDE
Table I.Allowable Operating Conditions for KS and KSU
Package OptionsNOTESDAC ON Double 75R refers to a condition where the DACs are terminated in
a double 75R load and low power mode is disabled.DAC ON Low Power refers to a condition where the DACs are terminated in a
double 75R load and low power mode is enabled.DAC ON Buffering refers to a condition where the DAC current is reduced tomA and external buffers are used to drive the video load.
PIN CONFIGURATIONS
PIN FUNCTION DESCRIPTIONSTTXREQ/GND
ADV7170/ADV7171
GENERAL DESCRIPTIONThe ADV7170/ADV7171 is an integrated digital video encoder
that converts Digital CCIR-601 4:2:2 8 or 16-bit component
video data into a standard analog baseband television signal
compatible with worldwide standards.
The on-board SSAF (Super Sub-Alias Filter) with extended
luminance frequency response and sharp stopband attenuation,
enables studio quality video playback on modern TVs, giving
optimal horizontal line resolution.
An advanced power management circuit enables optimal control
of power consumption in both normal operating modes and
power-down or sleep modes.
The ADV7170/ADV7171 also supports both PAL and NTSC
square pixel operation. The parts also incorporate WSS and
CGMS-A data control generation.
The output video frames are synchronized with the incoming
data timing reference codes. Optionally, the encoder accepts
(and can generate) HSYNC, VSYNC, and FIELD timing sig-
nals. These timing signals can be adjusted to change pulsewidth
and position while the part is in the master mode. The encoder
requires a single two times pixel rate (27 MHz) clock for standard
operation. Alternatively, the encoder requires a 24.5454 MHz
clock for NTSC or 29.5 MHz clock for PAL square pixel
mode operation. All internal timing is generated on-chip.
A separate teletext port enables the user to directly input tele-
text data during the vertical blanking interval.
The ADV7170/ADV7171 modes are set up over a two-wire
serial bidirectional port (I2C-Compatible) with two slave addresses.
Functionally, the ADV7171 and ADV7170 are the same with
the exception that the ADV7170 can output the Macrovision
anticopy algorithm.
The ADV7170/ADV7171 is packaged in a 44-lead MQFP pack-
age and a 44-lead TQFP package.
DATA PATH DESCRIPTIONFor PAL B, D, G, H, I, M, N, and NTSC M, N modes, YCrCb
4:2:2 data is input via the CCIR-656 Compatible Pixel Port at a
27 MHz data rate. The pixel data is demultiplexed to form
three data paths. Y typically has a range of 16 to 235, Cr and
Cb typically have a range of 128 ± 112; however, it is possible
to input data from 1 to 254 on both Y, Cb and Cr. The ADV7170/
ADV7171 supports PAL (B, D, G, H, I, M, N) and NTSC
(with and without pedestal) standards. The appropriate SYNC,
BLANK and Burst levels are added to the YCrCb data. Macrovi-
sion AntiTaping (ADV7170 only), closed-captioning and Teletext
levels are also added to Y and the resultant data is interpolated
to a rate of 27 MHz. The interpolated data is filtered and scaled by
three digital FIR filters.
The U and V signals are modulated by the appropriate sub-
carrier sine/cosine phases and added together to make up the
chrominance signal. The luma (Y) signal can be delayed 1–3
luma cycles (each cycle is 74 ns) with respect to the chroma signal.
The luma and chroma signals are then added together to make
up the composite video signal. All edges are slew rate limited.
The YCrCb data is also used to generate RGB data with
appropriate SYNC and BLANK levels. The RGB data is in
synchronization with the composite video output. Alternatively,
analog YUV data can be generated instead of RGB.
The four l0-bit DACs can be used to output:Composite Video + RGB Video.Composite Video + YUV Video.Two Composite Video Signals + LUMA and CHROMA
(Y/C) Signals.
Alternatively, each DAC can be individually powered off if
not required.
Video output levels are illustrated in Appendix 6.
INTERNAL FILTER RESPONSEThe Y filter supports several different frequency responses,
including two low-pass responses, two notch responses, an
extended (SSAF) response, a CIF response and a QCIF response.
The UV filter supports several different frequency responses,
including four low-pass responses, a CIF response and a QCIF
response, these can be seen in the following Figures 4 to 18.
Figure 4.Luminance Internal Filter Specifications
Figure 6.NTSC Low-Pass Luma Filter
Figure 7.PAL Low-Pass Luma Filter
Figure 8.NTSC Notch Luma Filter
Figure 9.PAL Notch Luma Filter
Figure 10.Extended Mode (SSAF) Luma Filter
Figure 11.CIF Luma Filter
ADV7170/ADV7171Figure 12.QCIF Luma Filter
Figure 13.1.3 MHz Low-Pass Chroma Filter
Figure 14.0.65 MHz Low-Pass Chroma Filter
Figure 15.1.0 MHz Low-Pass Chroma Filter
Figure 16.2.0 MHz Low-Pass Chroma Filter
Figure 17.CIF Chroma Filter
COLOR BAR GENERATIONThe ADV7170/ADV7171 can be configured to generate 100/
7.5/75/7.5 color bars for NTSC or 100/0/75/0 for PAL color
bars. These are enabled by setting MR17 of Mode Register 1
to Logic “1.”
SQUARE PIXEL MODEThe ADV7170/ADV7171 can be used to operate in square pixel
mode. For NTSC operation, an input clock of 24.5454 MHz is
required. Alternatively, for PAL operation, an input clock of
29.5 MHz is required. The internal timing logic adjusts accord-
ingly for square pixel mode operation.
COLOR SIGNAL CONTROLThe color information can be switched on and off the video
output using Bit MR24 of Mode Register 2.
BURST SIGNAL CONTROLThe burst information can be switched on and off the video
output using Bit MR25 of Mode Register 2.
NTSC PEDESTAL CONTROLThe pedestal on both odd and even fields can be controlled on a
line-by-line basis using the NTSC Pedestal Control Registers.
This allows the pedestals to be controlled during the vertical
blanking interval.
PIXEL TIMING DESCRIPTIONThe ADV7170/ADV7171 can operate in either 8-bit or 16-bit
YCrCb Mode.
8-Bit YCrCb ModeThis default mode accepts multiplexed YCrCb inputs through
the P7-P0 pixel inputs. The inputs follow the sequence Cb0, Y0
Cr0, Y1 Cb1, Y2, etc. The Y, Cb and Cr data are input on a
rising clock edge.
16-Bit YCrCb ModeThis mode accepts Y inputs through the P7–P0 pixel inputs and
multiplexed CrCb inputs through the P15–P8 pixel inputs. The
data is loaded on every second rising edge of CLOCK. The inputs
SUBCARRIER RESETTogether with the SCRESET/RTC pin, and bits MR22 and
MR21 of Mode Register 2, the ADV7170/ADV7171 can be
used in subcarrier reset mode. The subcarrier will reset to Field
0 at the start of the following field when a low-to-high transition
occurs on this input pin.
REAL-TIME CONTROLTogether with the SCRESET/RTC pin, and Bits MR22 and
MR21 of Mode Register 2, the ADV7170/ADV7171 can be
used to lock to an external video source. The real-time control
mode allows the ADV7170/ADV7171 to automatically alter the
subcarrier frequency to compensate for line length variation.
When the part is connected to a device that outputs a digital
datastream in the RTC format (such as a ADV7185 video
decoder, see Figure 19), the part will automatically change to
the compensated subcarrier frequency on a line-by-line basis.
This digital datastream is 67 bits wide and the subcarrier is
contained in Bits 0 to 21. Each bit is 2 clock cycles long. 00Hex
should be written into all four subcarrier frequency registers
when using this mode.
VIDEO TIMING DESCRIPTIONThe ADV7170/ADV7171 is intended to interface to off-
the-shelf MPEG1 and MPEG2 Decoders. Consequently, the
ADV7170/ADV7171 accepts 4:2:2 YCrCb Pixel Data via a
CCIR-656 pixel port and has several video timing modes of
operation that allow it to be configured as either system master
video timing generator or a slave to the system video timing
generator. The ADV7170/ADV7171 generates all of the required
horizontal and vertical timing periods and levels for the analog
video outputs.
The ADV7170/ADV7171 calculates the width and placement of
analog sync pulses, blanking levels and color burst envelopes.
Color bursts are disabled on appropriate lines, and serration and
equalization pulses are inserted where required.
In addition, the ADV7170/ADV7171 supports a PAL or NTSC
square pixel operation in slave mode. The part requires an input
pixel clock of 24.5454 MHz for NTSC and an input pixel clock
of 29.5 MHz for PAL. The internal horizontal line counters
place the various video waveform sections in the correct location
for the new clock frequencies.
The ADV7170/ADV7171 has four distinct master and four dis-
tinct slave timing configurations. Timing Control is established
with the bidirectional SYNC, BLANK, and FIELD/VSYNC
pins. Timing Mode Register 1 can also be used to vary the timing
pulsewidths and where they occur in relation to each other.
Figure 18.QCIF Chroma Filter
ADV7170/ADV7171
Vertical Blanking Data InsertionIt is possible to allow encoding of incoming YCbCr data on those lines of VBI that do not bear line sync or pre-/post-equalization
pulses (see Figures 21 to 32). This mode of operation is called “Partial Blanking” and is selected by setting MR32 to 1. It allows the
insertion of any VBI data (Opened VBI) into the encoded output waveform. This data is present in digitized incoming YCbCr data
stream (e.g., WSS data, CGMS, VPS, etc.). Alternatively, the entire VBI may be blanked (no VBI data inserted) on these lines by
setting MR32 to 0.
Mode 0 (CCIR-656):Slave Option(Timing Register 0 TR0 = X X X X X 0 0 0)
The ADV7170/ADV7171 is controlled by the SAV (Start Active Video) and EAV (End Active Video) time codes in the pixel data.
All timing information is transmitted using a 4-byte synchronization pattern. A synchronization pattern is sent immediately before
and after each line during active picture and retrace. Mode 0 is illustrated in Figure 20. The HSYNC, FIELD/VSYNC, and BLANK
(if not used) pins should be tied high during this mode.
Figure 19.RTC Timing and Connections
Mode 0 (CCIR-656): Master Option(Timing Register 0 TR0 = X X X X X 0 0 1)
The ADV7170/ADV7171 generates H, V, and F signals required for the SAV (Start Active Video) and EAV (End Active Video)
Time Codes in the CCIR656 standard. The H bit is output on the HSYNC pin, the V bit is output on the BLANK pin and the F bit
is output on the FIELD/VSYNC pin. Mode 0 is illustrated in Figure 21 (NTSC) and Figure 22 (PAL). The H, V, and F transitions
relative to the video waveform are illustrated in Figure 23.
Figure 20.Timing Mode 0 (Slave Mode)
Figure 21.Timing Mode 0 (NTSC Master Mode)
ADV7170/ADV7171Figure 22.Timing Mode 0 (PAL Master Mode)
Figure 23.Timing Mode 0 Data Transitions (Master Mode)
Mode 1:Slave Option HSYNC, BLANK, FIELD(Timing Register 0 TR0 = X X X X X 0 1 0)
In this mode the ADV7170/ADV7171 accepts horizontal SYNC and Odd/Even FIELD signals. A transition of the FIELD input
when HSYNC is low indicates a new frame, i.e., vertical retrace. The BLANK signal is optional. When the BLANK input is dis-
abled, the ADV7170/ADV7171 automatically blanks all normally blank lines as per CCIR-624. Mode 1 is illustrated in Figure
24 (NTSC) and Figure 25 (PAL).
Figure 24.Timing Mode 1 (NTSC)
ADV7170/ADV7171
Mode 1: Master Option HSYNC, BLANK, FIELD(Timing Register 0 TR0 = X X X X X 0 1 1)
In this mode the ADV7170/ADV7171 can generate horizontal SYNC and Odd/Even FIELD signals. A transition of the FIELD
input when HSYNC is low indicates a new frame, i.e., vertical retrace. The BLANK signal is optional. When the BLANK input is
disabled, the ADV7170/ADV7171 automatically blanks all normally blank lines as per CCIR-624. Pixel data is latched on the rising
clock edge following the timing signal transitions. Mode 1 is illustrated in Figure 24 (NTSC) and Figure 25 (PAL). Figure 26 illus-
trates the HSYNC, BLANK, and FIELD for an odd or even field transition relative to the pixel data.
Figure 26.Timing Mode 1 Odd/Even Field Transitions Master/Slave
Mode 2:Slave Option HSYNC, VSYNC, BLANK(Timing Register 0 TR0 = X X X X X 1 0 0)
In this mode the ADV7170/ADV7171 accepts horizontal and vertical SYNC signals. A coincident low transition of both HSYNC and
VSYNC inputs indicates the start of an odd field. A VSYNC low transition when HSYNC is high indicates the start of an even field.
The BLANK signal is optional. When the BLANK input is disabled, the ADV7170/ADV7171 automatically blanks all normally
blank lines as per CCIR-624. Mode 2 is illustrated in Figure 27 (NTSC) and Figure 28 (PAL).
Figure 27.Timing Mode 2 (NTSC)
Figure 28.Timing Mode 2 (PAL)
Mode 2:Master Option HSYNC, VSYNC, BLANK(Timing Register 0 TR0 = X X X X X 1 0 1)
In this mode the ADV7170/ADV7171 can generate horizontal and vertical SYNC signals. A coincident low transition of both
HSYNC and VSYNC inputs indicates the start of an Odd Field. A VSYNC low transition when HSYNC is high indicates the start of
an even field. The BLANK signal is optional. When the BLANK input is disabled, the ADV7170/ADV7171 automatically blanks all
normally blank lines as per CCIR-624. Mode 2 is illustrated in Figure 27 (NTSC) and Figure 28 (PAL). Figure 29 illustrates
the HSYNC, BLANK, and VSYNC for an even-to-odd field transition relative to the pixel data. Figure 30 illustrates the HSYNC,
BLANK, and VSYNC for an odd-to-even field transition relative to the pixel data.
Figure 29.Timing Mode 2 Even-to-Odd Field Transition Master/Slave
ADV7170/ADV7171
Mode 3:Master/Slave Option HSYNC, BLANK, FIELD(Timing Register 0 TR0 = X X X X X 1 1 0 or X X X X X 1 1 1)
In this mode the ADV7170/ADV7171 accepts or generates Horizontal SYNC and Odd/Even FIELD signals. A transition of the
FIELD input when HSYNC is high indicates a new frame, i.e., vertical retrace. The BLANK signal is optional. When the BLANK
input is disabled, the ADV7170/ADV7171 automatically blanks all normally blank lines as per CCIR-624. Mode 3 is illustrated in
Figure 31 (NTSC) and Figure 32 (PAL).
Figure 31.Timing Mode 3 (NTSC)
POWER-ON RESETAfter power-up, it is necessary to execute a reset operation. A
reset occurs on the falling edge of a high-to-low transition on
the RESET pin. This initializes the pixel port so that the
pixel inputs, P7–P0 are selected. After reset, the ADV7170/
ADV7171 is automatically set up to operate in NTSC mode.
Subcarrier frequency code 21F07C16HEX is loaded into the
subcarrier frequency registers. All other registers, with the ex-
ception of Mode Register 0, are set to 00H. All bits in Mode
Register 0 are set to Logic Level “0” except Bit MR44. Bit
MR44 of Mode Register 4 is set to Logic “1.” This enables the
7.5 IRE pedestal.
SCH PHASE MODEThe SCH phase is configured in default mode to reset every
four (NTSC) or eight (PAL) fields to avoid an accumulation of
SCH phase error over time. In an ideal system, zero SCH phase
error would be maintained forever, but in reality, this is impos-
sible to achieve due to clock frequency variations. This effect is
reduced by the use of a 32-bit DDS, which generates this SCH.
Resetting the SCH phase every four or eight fields avoids the
accumulation of SCH phase error, and results in very minor
SCH phase jumps at the start of the four or eight field sequence.
Resetting the SCH phase should not be done if the video source
does not have stable timing or the ADV7170/ADV7171 is con-
figured in RTC mode (MR21 = 1 and MR22 = 1). Under these
conditions (unstable video) the subcarrier phase reset should be
enabled (MR22 = 0 and MR21 = 1) but no reset applied. In
this configuration the SCH phase will never be reset, which
means that the output video will now track the unstable input
video. The subcarrier phase reset, when applied, will reset the
SCH phase to Field 0 at the start of the next field (e.g., subcarrier
phase reset applied in Field 5 [PAL] on the start of the next
field SCH phase will be reset to Field 0).
MPU PORT DESCRIPTIONThe ADV7170 and ADV7171 support a two-wire serial (I2C
Compatible) microprocessor bus driving multiple peripherals.
Two inputs, serial data (SDATA) and serial clock (SCLOCK),
carry information between any device connected to the bus. Each
slave device is recognized by a unique address. The ADV7170
and ADV7171 each have four possible slave addresses for both
read and write operations. These are unique addresses for each
device and are illustrated in Figure 33 and Figure 34. The LSB
sets either a read or write operation. Logic Level “1” corre-
sponds to a read operation, while Logic Level “0” corresponds
to a write operation. A “1” is set by setting the ALSB pin of the
ADV7170/ADV7171 to Logic Level “0” or Logic Level “1.”
Figure 33.ADV7170 Slave Address
Figure 34.ADV7171 Slave Address
To control the various devices on the bus, the following proto-
col must be followed: first, the master initiates a data transfer by
establishing a start condition, defined by a high-to-low transition
on SDATA while SCLOCK remains high. This indicates that
an address/data stream will follow. All peripherals respond to
the start condition and shift the next eight bits (7-bit address +
R/W bit). The bits transfer from MSB down to LSB. The periph-
eral that recognizes the transmitted address responds by pulling
the data line low during the ninth clock pulse. This is known as
an acknowledge bit. All other devices withdraw from the bus at
this point and maintain an idle condition. The idle condition is
where the device monitors the SDATA and SCLOCK lines wait-
ing for the start condition and the correct transmitted address.
The R/W bit determines the direction of the data. A Logic “0”
on the LSB of the first byte means that the master will write infor-
mation to the peripheral. A Logic “1” on the LSB of the first byte
means that the master will read information from the peripheral.
ADV7170/ADV7171The ADV7170/ADV7171 acts as a standard slave device on the
bus. The data on the SDATA pin is 8 bits long, supporting
the 7-bit addresses, plus the R/W bit. The ADV7170 has 48
subaddresses and the ADV7171 has 26 subaddresses to enable
access to the internal registers. It therefore interprets the first
byte as the device address and the second byte as the starting
subaddress. The subaddresses auto increment allows data to
be written to or read from the starting subaddress. A data
transfer is always terminated by a stop condition. The user can
also access any unique subaddress register on a one-by-one basis
without having to update all the registers. There is one excep-
tion. The subcarrier frequency registers should be updated in
sequence, starting with Subcarrier Frequency Register 0. The
auto increment function should then be used to increment and
access Subcarrier Frequency Registers 1, 2, and 3. The subcarrier
frequency registers should not be accessed independently.
Stop and start conditions can be detected at any stage during
the data transfer. If these conditions are asserted out of sequence
with normal read and write operations, they cause an immediate
jump to the idle condition. During a given SCLOCK high period,
the user should issue only one start condition, one stop condi-
tion or a single stop condition followed by a single start condition.
If an invalid subaddress is issued by the user, the ADV7170/
ADV7171 will not issue an acknowledge and will return to the
idle condition. If, in auto-increment mode the user exceeds the
highest subaddress, the following action will be taken:In Read Mode, the highest subaddress register contents
will continue to be output until the master device issues
a no-acknowledge. This indicates the end of a read. A
no-acknowledge condition is where the SDATA line is not
pulled low on the ninth pulse.
2. In Write Mode, the data for the invalid byte will not be
loaded into any subaddress register, a no-acknowledge will
be issued by the ADV7170/ADV7171 and the part will
return to the idle condition.
Figure 35.Bus Data Transfer
Figure 35 illustrates an example of data transfer for a read
sequence and the start and stop conditions.
Figure 36 shows bus write and read sequences.
REGISTER ACCESSESThe MPU can write to or read from all of the ADV7170/
ADV7171 registers except the subaddress register, which is a
write-only register. The subaddress register determines which
register the next read or write operation accesses. All communi-
cations with the part through the bus start with an access to the
subaddress register. A read/write operation is performed from/to
the target address, which then increments to the next address
until a stop command on the bus is performed.
REGISTER PROGRAMMINGThe following section describes each register, including subaddress
register, mode registers, subcarrier frequency registers, subcarrier
phase register, timing registers, closed captioning extended data
registers, closed captioning data registers and NTSC pedestal
control registers, in terms of its configuration.
Subaddress Register (SR7–SR0)The communications register is an 8-bit write-only register.
After the part has been accessed over the bus, and a read/write
operation is selected, the subaddress is set up. The subaddress
register determines to/from which register the operation takes place.
Figure 37 shows the various operations under the control of
the subaddress register. Zero should always be written to
SR7–SR6.
Register Select (SR5–SR0)These bits are set up to point to the required starting address.
MODE REGISTER 0 MR0 (MR07–MR00)
(Address [SR4–SR0] = 00H)Figure 38 shows the various operations under the control of Mode
Register 0. This register can be read from as well as written to.
MR0 BIT DESCRIPTION
Output Video Standard Selection (MR01–MR00)These bits are used to set up the encode mode. The ADV7170/
ADV7171 can be set up to output NTSC, PAL (B, D, G, H, I)
and PAL (M, N) standard video.
Luminance Filter Control (MR02–MR04)These bits specify which luma filter is to be selected. The filter
selection is made independent of whether PAL or NTSC is
selected.
Chrominance Filter Control (MR05–MR07)These bits select the chrominance filter. A low-pass filter can be
selected with a choice of cutoff frequencies, 0.65 MHz, 1.0 MHz,
1.3 MHz or 2 MHz, along with a choice of CIF or QCIF filters.
Figure 36.Write and Read Sequences
Figure 37.Subaddress Register Map
ADV7170/ADV7171
MODE REGISTER 1 MR1 (MR17–MR10)
(Address (SR4–SR0) = 01H)Figure 39 shows the various operations under the control of Mode
Register 1. This register can be read from as well as written to.
MR1 BIT DESCRIPTION
Interlace Control (MR10)This bit is used to set up the output to interlaced or noninter-
laced mode. This mode is only relevant when the part is in
composite video mode.
Closed Captioning Field Selection (MR12–MR11)These bits control the fields on which closed captioning data is
displayed; closed captioning information can be displayed on an
odd field, even field or both fields.
DAC Control (MR16–MR13)These bits can be used to power down the DACs. This can
be used to reduce the power consumption of the ADV7170/
ADV7171 if any of the DACs are not required in the application.
Color Bar Control (MR17)This bit can be used to generate and output an internal color
bar test pattern. The color bar configuration is 100/7.5/75/7.5
for NTSC and 100/0/75/0 for PAL. It is important to note that
when color bars are enabled the ADV7170/ADV7171 is config-
ured in a master timing mode.
MODE REGISTER 2 MR2 (MR27–MR20)
(Address [SR4-SR0] = 02H)Mode Register 2 is an 8-bit-wide register.
Figure 40 shows the various operations under the control of Mode
Register 2. This register can be read from as well as written to.
MR2 BIT DESCRIPTION
Square Pixel Control (MR20)This bit is used to set up square pixel mode. This is available in
slave mode only. For NTSC, a 24.5454 MHz clock must be
supplied. For PAL, a 29.5 MHz clock must be supplied.
Figure 39. Mode Register 1
Figure 40.Mode Register 2
Genlock Control (MR22–MR21)These bits control the genlock feature of the ADV7170/ADV7171.
Setting MR21 to a Logic “1” configures the SCRESET/RTC
pin as an input. Setting MR22 to Logic Level “0” configures the
SCRESET/RTC pin as a subcarrier reset input. Therefore, the
subcarrier will reset to Field 0 following a low-to-high transition
on the SCRESET/RTC pin. Setting MR22 to Logic Level “1”
configures the SCRESET/RTC pin as a real-time control input.
Active Video Line Duration (MR23)This bit switches between two active video line durations. A
zero selects CCIR REC601. (720 pixels PAL/NTSC) and a
one selects ITU-R.BT470 standard for active video duration
(710 pixels NTSC 702 pixels PAL).
Chrominance Control (MR24)This bit enables the color information to be switched on and off
the video output.
Burst Control (MR25)This bit enables the burst information to be switched on and off
the video output.
Low Power Mode (MR26)This bit enables the lower power mode of the ADV7170/ADV7171.
This will reduce the DAC current by 45%.
Reserved (MR27)A Logical 0 must be written to this bit.
MODE REGISTER 3 MR3 (MR37–MR30)
(Address [SR4–SR0] = 03H)Mode Register 3 is an 8-bit-wide register.
Figure 41 shows the various operations under the control of
Mode Register 3.
MR3 BIT DESCRIPTION
Revision Code (MR30–MR31)These bits are read only and indicates the revision of the device.
VBI Open (MR32)This bit determines whether or not data in the vertical blanking
interval (VBI) is output to the analog outputs or blanked. VBI data
insertion is not available in Slave Mode 0. Also, when both,
BLANK input control and VBI-open are enabled, BLANK input
control has priority, i.e., VBI data insertion will not work.
DAC Output (MR33)This bit is used to switch the DAC outputs from SCART to a
EUROSCART configuration. A complete table of all DAC
output configurations is shown below.
Chroma Output Select (MR34)With this active high bit it is possible to output YUV data with a
composite output on the fourth DAC or a chroma output on the
fourth DAC (0 = CVBS; 1 = CHROMA).
Teletext Enable (MR35)This bit must be set to “1” to enable teletext data insertion on
the TTX pin.
TTXREQ Bit Mode Control (MR36)This bit enables switching of the teletext request signal from a
continuous high signal (“MR36 = 0”) to a bit wise request sig-
nal (“MR36 = 1”).
Input Default Color (MR37)This bit determines the default output color from the DACs for
zero input pixel data (or disconnected). A Logical “0” means
that the color corresponding to 00000000 will be displayed. A
Logical “1” forces the output color to black for 00000000 pixel
input video data.
Table II.DAC Output Configuration Matrix0011Y
0101G
1001Y
1010C
1011Y
1100C
CVBS:Composite Video Baseband SignalLuminance Component Signal (For YUV or Y/C Mode)Chrominance Signal (For Y/C Mode)Chrominance Component Signal (For YUV Mode)Chrominance Component Signal (For YUV Mode)
NOTE
Each DAC can be powered ON or OFF individually with the following control
bits (“0” = ON, “1” = OFF).
MR13-DAC C
MR14-DAC D
ADV7170/ADV7171Figure 42. Mode Register 4
MODE REGISTER 4 MR4 (MR47–MR40)
(Address (SR4–SR0) = 04H)Mode Register 4 is a 8-bit-wide register.
Figure 42 shows the various operations under the control of
Mode Register 4.
MR4 BIT DESCRIPTION
Output Select (MR40)This bit specifies if the part is in composite video or RGB/YUV
mode. Note that in RGB/YUV mode the composite signal is still
available.
RGB/YUV Control (MR41)This bit enables the output from the RGB DACs to be set to
YUV output video standard.
RGB Sync (MR42)This bit is used to set up the RGB outputs with the sync infor-
mation encoded on all RGB outputs.
VSYNC_3H (MR43)When this bit is enabled (“1”) in slave mode, it is possible to
drive the VSYNC active low input for 2.5 lines in PAL mode
and 3 lines in NTSC mode. When this bit is enabled in master
mode, the ADV7170/ADV7171 outputs an active low VSYNC
signal for 3 lines in NTSC mode and 2.5 lines in PAL mode.
Pedestal Control (MR44)This bit specifies whether a pedestal is to be generated on
the NTSC composite video signal. This bit is invalid if the
ADV7170/ADV7171 is configured in PAL mode.
Active Video Filter Control (MR45)This bit controls the filter mode applied outside the active video
portion of the line. This filter ensures that the Sync rise and fall
times are always on spec regardless of which Luma filter is
selected. A Logic “1” enables this mode.
Sleep Mode Control (MR46)When this bit is set (“1”) Sleep Mode is enabled. With this
mode enabled, the ADV7170/ADV7171 power consumption is
reduced to typically 200 nA. The I2C registers can be written to
and read from when the ADV7170/ADV7171 is in Sleep Mode.
If MR46 is set to a (“0”) when the device is in Sleep Mode,
the ADV7170/ADV7171 will come out of Sleep Mode and
resume normal operation. Also, if the RESET signal is applied
during Sleep Mode the ADV7170/ADV7171 will come out of
Sleep Mode and resume normal operation.
Reserved (MR47)A Logical 0 should be written to this bit.
TIMING MODE REGISTER 0 (TR07–TR00)
(Address [SR4–SR0] = 07H)Figure 43 shows the various operations under the control of
Timing Register 0. This register can be read from as well as
written to.
TR0 BIT DESCRIPTION
Master/Slave Control (TR00)This bit controls whether the ADV7170/ADV7171 is in master
or slave mode.
Timing Mode Selection (TR02–TR01)These bits control the timing mode of the ADV7170/ADV7171.
These modes are described in more detail in the Timing and
Control section of the data sheet.
BLANK Control (TR03)This bit controls whether the BLANK input is used when the
part is in slave mode.
Luma Delay (TR05–TR04)These bits control the addition of a luminance delay. Each bit
represents a delay of 74 ns.
Pixel Port Control (TR06)This bit is used to set the pixel port to accept 8-bit or 16-bit
data. If an 8-bit input is selected the data will be set up on
Pins P7–P0.
Timing Register Reset (TR07)Toggling TR07 from low to high and low again resets the inter-
nal timing counters. This bit should be toggled after power-up,
reset or changing to a new timing mode.
TIMING MODE REGISTER 1 (TR17–TR10)
(Address (SR4–SR0) = 08H)Timing Register 1 is a 8-bit-wide register.
Figure 44 shows the various operations under the control of
Timing Register 1. This register can be read from as well written
to. This register can be used to adjust the width and position of
the master mode timing signals.
TR1 BIT DESCRIPTION
HSYNC Width (TR11–TR10)These bits adjust the HSYNC pulsewidth.
HSYNC to FIELD/VSYNC Delay (TR13–TR12)These bits adjust the position of the HSYNC output relative to
the FIELD/VSYNC output.
HSYNC to FIELD Rising Edge Delay (TR15–TR14)When the ADV7170/ADV7171 is in timing mode 1, these bits
adjust the position of the HSYNC output relative to the FIELD
output rising edge.
VSYNC Width (TR15–TR14)When the ADV7170/ADV7171 is configured in Timing Mode 2,
these bits adjust the VSYNC pulsewidth.
HSYNC to Pixel Data Adjust (TR17–TR16)This enables the HSYNC to be adjusted with respect to the pixel
data. This allows the Cr and Cb components to be swapped. This
adjustment is available in both master and slave timing modes.
Figure 44.Timing Register 1
ADV7170/ADV7171
SUBCARRIER FREQUENCY REGISTER 3–0
(FSC3–FSC0)
(Address [SR4–SR0] = 09H–0CH)These 8-bit-wide registers are used to set up the subcarrier fre-
quency. The value of these registers is calculated by using the
following equation:
Subcarrier Frequency Register =
i.e.:NTSC Mode,
FCLK = 27 MHz,
FSCF = 3.5795454 MHz
Subcarrier Frequency Value =
= 21F07C16HEX
Figure 45 shows how the frequency is set up by the four registers.
SUBCARRIER PHASE REGISTER (FP7–FP0)
(Address [SR4–SR0] = 0DH)This 8-bit-wide register is used to set up the subcarrier phase.
Each bit represents 1.41°. For normal operation this register is
set to 00Hex.
Figure 45.Subcarrier Frequency Register
CLOSED CAPTIONING EVEN FIELD
DATA REGISTER 1–0 (CED15–CED0)
(Address [SR4–SR0] = 0E–0FH)These 8-bit-wide registers are used to set up the closed captioning
extended data bytes on even fields. Figure 46 shows how the
high and low bytes are set up in the registers.
Figure 46.Closed Captioning Extended Data Register
CLOSED CAPTIONING ODD FIELD
DATA REGISTER 1–0 (CCD15–CCD0)
(Subaddress [SR4–SR0] = 10–11H)These 8-bit-wide registers are used to set up the closed
captioning data bytes on odd fields. Figure 47 shows how the
high and low bytes are set up in the registers.
NTSC PEDESTAL/PAL TELETEXT CONTROL
REGISTERS 3–0 (PCE15–0, PCO15–0)/(TXE15–0, TXO15–0)
(Subaddress [SR4–SR0] = 12–15H)These 8-bit-wide registers are used to enable the NTSC pedes-
tal/PAL Teletext on a line-by-line basis in the vertical blanking
interval for both odd and even fields. Figures 48 and 49 show
the four control registers. A Logic “1” in any of the bits of these
registers has the effect of turning the Pedestal OFF on the
equivalent line when used in NTSC. A Logic “1” in any of the
bits of these registers has the effect of turning Teletext ON on
the equivalent line when used in PAL.
Figure 48.Pedestal Control Registers
Figure 49.Teletext Control Registers
TELETEXT REQUEST CONTROL REGISTER TC07
(TC07–TC00)
(Address [SR4–SR0] = 19H)Teletext Control Register is an 8-bit-wide register. See Figure 50.
TTXREQ Rising Edge Control (TC07–TC04)These bits control the position of the rising edge of TTXREQ.
It can be programmed from zero CLOCK cycles to a max of 15
CLOCK cycles. See Figure 59.
TTXREQ Falling Edge Control (TC03–TC00)These bits control the position of the falling edge of TTXREQ.
It can be programmed from zero CLOCK cycles to a max of 15
CLOCK cycles. This controls the active window for Teletext
data. Increasing this value reduces the amount of Teletext bits
below the default of 360. If Bits TC03-TC00 are 00Hex when
bits TC07–TC04 are changed, the falling edge of TTXREQ will
track that of the rising edge (i.e., the time between the falling
and rising edge remains constant). See Figure 59.
CGMS_WSS REGISTER 0 C/W0 (C/W07–C/W00)
(Address [SR4–SR0] = 16H)
