ADV7152LS135 ,CMOS 220 MHz True-Color Graphics Triple 10-Bit Video RAM-DACGENERAL DESCRIPTION®Palette Priority Select RegistersThe ADV7152 (ADV ) is a complete analog output ..
ADV7152LS220 ,CMOS 220 MHz True-Color Graphics Triple 10-Bit Video RAM-DACSPECIFICATIONS (V = +5 V; V = +1.235 V; R = 280 V. IOR, IOG, IOB (R = 37.5 V,AA REF SET L2C = 10 pF ..
ADV7152LS85 ,CMOS 220 MHz True-Color Graphics Triple 10-Bit Video RAM-DACCHARACTERISTICS (V = +5 V; V = +1.235 V; R = 280 V. IOR, IOG, IOB (R = 37.5 V, C = 10 pF);AA REF SE ..
ADV7160KS220 ,96-Bit, 220 MHz True-Color Video RAM-DACspecifications T to T unless otherwise noted.)L MIN MAXParameter Min Typ Max Units Test Conditions ..
ADV7162KS140 ,96-Bit, 220 MHz True-Color Video RAM-DACGENERAL DESCRIPTION8-Bit (Pseudo)The ADV7160/ADV7162® is a 96-bit pixel port Video RAM-Pixel Data S ..
ADV7170KS ,Digital PAL/NTSC Video Encoder with 10-Bit SSAF⑩ and Advanced Power ManagementSPECIFICATIONSAA REF SET MIN MAX1Parameter Conditions Min Typ Max Units3STATIC PERFORMANCEResolutio ..
AM27C512-150DE , 512 Kilobit ( 64 K x 8-Bit ) CMOS EPROM Speed options as fast as 55 ns
AM27C512-150DIB , 512 Kilobit ( 64 K x 8-Bit ) CMOS EPROM Speed options as fast as 55 ns
AM27C512-150JC , 512 Kilobit ( 64 K x 8-Bit ) CMOS EPROM Speed options as fast as 55 ns
AM27C512-150JC , 512 Kilobit ( 64 K x 8-Bit ) CMOS EPROM Speed options as fast as 55 ns
AM27C512-150JC , 512 Kilobit ( 64 K x 8-Bit ) CMOS EPROM Speed options as fast as 55 ns
AM27C512-150PC , 512 Kilobit ( 64 K x 8-Bit ) CMOS EPROM Speed options as fast as 55 ns
ADV7152LS110-ADV7152LS135-ADV7152LS220-ADV7152LS85
CMOS 220 MHz True-Color Graphics Triple 10-Bit Video RAM-DAC
REV.B
CMOS 220 MHz True-Color Graphics
Triple 10-Bit Video RAM-DAC
FEATURES
220 MHz, 24-Bit (30-Bit Gamma Corrected) True Color
Triple 10-Bit “Gamma Correcting” D/A Converters
Triple 256 3 10 (256 3 30) Color Palette RAM
On-Chip Clock Control Circuit
Palette Priority Select Registers
RS-343A/RS-170 Compatible Analog Outputs
TTL Compatible Digital Inputs
Standard MPU l/O Interface
10-Bit Parallel Structure
8+2 Byte Structure
Programmable Pixel Port: 24-Bit and 8-Bit (Pseudo)
Pixel Data Serializer
Multiplexed Pixel Input Ports; 1:1, 2:1
+5 V CMOS Monolithic Construction
100-Lead Plastic Quad Flatpack (QFP)
Thermally Enhanced to Achieve uJC < 1.08C/W
MODES OF OPERATION
24-Bit True Color (30-Bit Gamma Corrected)
@ 220 MHz
@ 170 MHz
@ 135 MHz
@ 110 MHz
@ 85 MHz
8-Bit Pseudo Color
15-Bit True Color
APPLICATIONS
High Resolution, True Color Graphics
Professional Color Prepress Imaging
GENERAL DESCRIPTIONThe ADV7152 (ADV®) is a complete analog output, Video
RAM-DAC on a single CMOS monolithic chip. The part is spe-
cifically designed for use in high performance, color graphics
workstations. The ADV7152 integrates a number of graphic
functions onto one device allowing 24-bit direct True-Color op-
eration at the maximum screen update rate of 220 MHz. The
ADV7152 implements 30-bit True Color in 24-bit frame buffer
designs. The part also supports other modes, including 15-bit
True Color and 8-bit Pseudo or Indexed Color. Either the Red,
Green or Blue input pixel ports can be used for Pseudo Color.
The device consists of three, high speed, 10-bit, video D/A con-
verters (RGB), three 256 3 10 (one 256 3 30) color look-up
tables, palette priority selects, a pixel input data multiplexer/
serializer and a clock generator/divider circuit. The ADV7152
implements 1:1 and 2:1 pixel data multiplexing. The onboard
palette priority select inputs enable multiple palette devices to
be connected together for use in multipalette and window
(Continued on page 10)
ADV is a registered trademark of Analog Devices, Inc.
FUNCTIONAL BLOCK DIAGRAM
ADV7152–SPECIFICATIONS(VAA1 = +5 V; VREF = +1.235 V; RSET = 280 V. IOR, IOG, IOB (RL = 37.5 V,
CL = 10 pF); IOR, IOG, IOB = GND. All specifications TMIN to TMAX2 unless otherwise noted.)NOTES±5% for all versions.Temperature range (TMIN to TMAX): 0°C to +70°C; TJ (Silicon Junction Temperature) ≤ 100°C.
TIMING CHARACTERISTICS1
CLOCK CONTROL AND PIXEL PORT4
ANALOG OUTPUTS7
MPU PORTS8, 9
(VAA2 = +5 V; VREF = +1.235 V; RSET = 280 V. IOR, IOG, IOB (RL = 37.5 V, CL = 10 pF);
IOR, IOG, I0B = GND. All specifications TMIN to TMAX3 unless otherwise noted.)
ADV7152NOTESTTL input values are 0 to 3 volts, with input rise/fall times ≤ 3 ns, measured between the 10% and 90% points. ECL inputs (CLOCK, CLOCK) are
VAA–0.8 V to VAA–1.8 V, with input rise/fall times ≤ 2 ns, measured between the 10% and 90% points. Timing reference points at 50% for inputs and out-
puts. Analog output load ≤ 10 pF. Databus (D0–D9) loaded as shown in Figure 1. Digital output load for LOADOUT, PRGCKOUT, SCKOUT, IPLL and
SYNCOUT ≤ 30 pF.±5% for all versions.Temperature range (TMIN to TMAX): 0°C to +70°C; TJ (Silicon Junction Temperature) ≤ 100°C.Pixel Port consists of the following inputs: Pixel Inputs: RED [A, B]; GREEN [A, B]; BLUE [A, B], Palette Selects: PS0 [A, B]; PS1 [A, B]; Pixel Controls:
SYNC, BLANK; Clock Inputs: CLOCK, CLOCK, LOADIN, SCKIN; Clock Outputs: LOADOUT, PRGCKOUT, SCKOUT.τ is the LOADOUT Cycle Time and is a function of the Pixel CLOCK Rate and the Multiplexing Mode: 1:1 multiplexing; τ = CLOCK = t1 ns; 2:1 multi-
plexing, τ = CLOCK × 2 = 2 × t1 ns.These fixed values for Pipeline Delay are valid under conditions where t10 and τ–t11 are met. If either t10 or τ–t11 are not met, the part will operate but the Pipe-
line Delay is increased by 2 clock cycles for 2:1 mode after calibration cycle is performed.Output delay measured from the 50% point of the rising edge of CLOCK to the 50% point of full-scale transition. Output rise/fall time measured between the
10% and 90% points of full-scale transition. Settling time measured from the 50% point of full-scale transition to the output remaining within ±1 LSB. (Settling time
does not include clock and data feedthrough.)t23 and t24 are measured with the load circuit of Figure 1 and defined as the time required for an output to cross 0.4 V or 2.4 V.t25 is derived from the measured time taken by the data outputs to change by 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrapo-
lated back to remove the effects of charging the 100 pF capacitor. This means that the time, t25, quoted in the Timing Characteristics is the true value for the device
and as such is independent of external databus loading capacitances.
Specifications subject to change without notice.
Figure 1.Load Circuit for Databus Access and Relinquish Times
Figure 2.LOADOUT vs. Pixel Clock Input (CLOCK, CLOCK)
Figure 3.LOADIN vs. Pixel Input Data
Figure 4.Pixel Input to Analog Output Pipeline with Minimum LOADOUT to LOADIN Delay (2:1 Multiplex Mode)
Figure 5.Pixel Input to Analog Output Pipeline with Maximum LOADOUT to LOADIN Delay (2:1 Multiplex Mode)
ADV7152Figure 7.Video Data Shift Clock Input (SCKIN) & BLANK vs. Video Data Shift Clock Output (SCKOUT)
Figure 8.Analog Output Response vs. CLOCKAA
AAAAAA
D0–D9
(READ MODE)
D0–D9
(WRITE MODE)
R/W, C0, C1Figure 9.Microprocessor Port (MPU) Interface Timing
RECOMMENDED OPERATING CONDITIONS
ABSOLUTE MAXIMUM RATINGS1VAA to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 V
Voltage on Any Digital Pin . . . .GND – 0.5 V to VAA + 0.5 V
Ambient Operating Temperature (TA) . . . . .–55°C to +125°C
Storage Temperature (TS) . . . . . . . . . . . . . .–65°C to +150°C
Junction Temperature (TJ) . . . . . . . . . . . . . . . . . . . .+150°C
Lead Temperature (Soldering, 10 secs) . . . . . . . . . . .+260°C
Vapor Phase Soldering (1 minute) . . . . . . . . . . . . . . .+220°C
Analog Outputs to GND2 . . . . . . . . . . . . .GND – 0.5 to VAA
NOTESStresses above those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those listed in the
operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.Analog Output Short Circuit to any Power Supply or Common can be of an
indefinite duration.
ORDERING GUIDE1, 2, 3
SpeedNOTESADV7152 is packaged in a 100-pin plastic quad flatpack, QFP.All devices are specified for 0°C to +70°C operation.Contact sales office for latest information on package design.
100-Lead QFP Configuration
CAUTIONESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the ADV7152 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
PIN ASSIGNMENTS
ADV7152
PIN FUNCTION DESCRIPTION
ADV7152(Continued from page 1)
applications. The part is controlled and programmed through
the microprocessor (MPU) port. The part also contains a num-
ber of onboard test registers, associated with self diagnostic test-
ing of the device.
The individual Red, Green and Blue pixel input ports allow
True-Color, image rendition. True-Color image rendition, at
speeds of up to 220 MHz, is achieved through the use of the
onboard data multiplexer/serializer. The pixel input ports flex-
ibility allows for direct interface to most standard frame buffer
memory configurations.
The 30 bits of resolution, associated with the color look-up
table and triple 10-bit DAC, realizes 24-bit True-Color resolu-
tion, while also allowing for the onboard implementation of lin-
earization algorithms, such as Gamma-Correction. This allows
effective 30-bit True-Color operation.
The on-chip video clock controller circuit generates all the in-
ternal clocking and some additional external clocking signals.
An external ECL oscillator source with differential outputs is all
that is required to drive the CLOCK and CLOCK inputs of the
ADV7152. The part can also be driven by an external clock
generator chip circuit, such as the AD730.
The ADV7152 is capable of generating RGB video output sig-
nals which are compatible with RS-343A and RS-170 video
standards, without requiring external buffering.
Test diagnostic circuitry has been included to complement the
users system level debugging.
The ADV7152 is fabricated in a +5 V CMOS process. Its
monolithic CMOS construction ensures greater functionality
with low power dissipation.
The ADV7152 is packaged in a plastic 100-pin power quad flat-
pack (QFP). Superior thermal dissipation is achieved by inclu-
sion of a copper heatslug, within the standard package outline
to which the die is attached.
Pixel Port and Clock Control CircuitThe Pixel Port of the ADV7152 is directly interfaced to the
video/graphics pipeline of a computer graphics subsystem. It is
connected directly or through a gate array to the video RAM of
the systems Frame-Buffer (video memory). The pixel port on
the device consists of:
Color DataRED, GREEN, BLUE
Pixel ControlsSYNC, BLANK
Palette SelectsPS0–PS1
The associated clocking signals for the pixel port include:
Clock InputsCLOCK, CLOCK,
LOADIN, SCKIN
Clock OutputsLOADOUT, PRGCKOUT,
SCKOUT
These onboard clock control signals are included to simplify
interfacing between the part and the frame buffer. Only two
control input signals are necessary to get the part operational,
CLOCK and CLOCK (ECL Levels). No additional signals or
external glue logic are required to get the Pixel Port & Clock
Control Circuit of the part operational.
Pixel Port (Color Data)The ADV7152 has 48 color data inputs. The part has two (for
2:1 multiplexing) 24-bit wide direct color data inputs. These
are user programmed to support a number of color data for-
mats including 24-Bit True Color, 15-Bit True Color and
8-Bit Pseudo Color (see “Color Data Formats” section) in 2:1
and 1:1 multiplex modes.
CIRCUIT DETAILS AND OPERATION
OVERVIEWDigital video or pixel data is latched into the ADV7152 over the
devices Pixel Port. This data acts as a pointer to the onboard
Color Palette RAM. The data at the RAM address pointed to is
latched into the digital-to-analog converters (DACs) and output
as an RGB analog video signal.
For the purposes of clarity of description, the ADV7152 is bro-
ken down into three separate functional blocks. These are:
1. Pixel port and clock control circuit
2. MPU port, registers and color palette
3. Digital-to-analog converters and video outputs
Table I shows the architectural and packaging differences be-
tween other devices in the ADV715x series of workstation parts.
(For more details consult the relevant data sheets.)
Table I.Architectural and Packaging Differences of the
ADV715x Series*See ADV7151 and ADV7150 data sheets for more information on these parts.
Color data is latched into the parts pixel port on every rising
edge of LOADIN (see Timing Waveform, Figure 3). The
required frequency of LOADIN is determined by the multiplex
rate, where
fLOADIN = fCLOCK/22:1Multiplex Mode
fLOADIN = fCLOCK1:1Multiplex Mode
Other pixel data signals latched into the device by LOADIN
include SYNC, BLANK and PS0–PS1.
Internally, data is pipelined through the part by the differential
pixel clock inputs, CLOCK and CLOCK. The LOADIN con-
trol signal needs only have a frequency synchronous relationship
to the pixel CLOCK (see “Pipeline Delay & Onboard Calibra-
tion” section). A completely phase independent LOADIN signal
can be used with the ADV7152, allowing the CLOCK to occur
anywhere during the LOADIN cycle.
Alternatively, the LOADOUT signal of the ADV7152 can be
used. LOADOUT can be connected either directly or indirectly
to LOADIN. Its frequency is automatically set to the correct
LOADIN requirement.
SYNC, BLANKThe BLANK and SYNC video control signals drive the analog
outputs to the blanking and SYNC levels respectively. These
signals are latched into the part on the rising edge of LOADIN.
The SYNC information is encoded onto the IOG analog signal
when bit CR22 of Command Register 2 is set to a Logic “1.”
The SYNC input is ignored if CR22 is set to “0.”
SYNCOUTIn some applications where it is not permissible to encode
SYNC on green (IOG), SYNCOUT can be used as a separate
TTL digital SYNC output. This has the advantage over an inde-
pendent (of the ADV7150) SYNC in that it does not necessitate
knowing the absolute pipeline delay of the part. This allows
complete independence between LOADIN/Pixel Data and
CLOCK. The SYNC input is connected to the device as normal
with Bit CR22 of Command Register 2 set to “0” thereby pre-
venting SYNC from being encoded onto IOG. Bit CR12 of
Command Register 1 is set to “1,” enabling SYNCOUT. The
output signal generates a TTL SYNCOUT with correct pipeline
delay that is capable of directly driving the composite SYNC
signal of a computer monitor.
PS0–PS1 (Palette Priority Select Inputs)These pixel port select inputs determine whether or not the de-
vice is selected. These controls effectively determine whether the
devices RGB analog outputs are turned-on or shut down. When
the analog outputs are shut down, IOR, IOG and IOB are
forced to 0 mA regardless of the state of the pixel and control
data inputs. This state is determined on a pixel by pixel basis as
the PS0–PS1 inputs are multiplexed in exactly the same format
as the pixel port color data. These controls allow for switching
between multiple palette devices (see Appendix 4). If the values
of PS0 and PSI match the values programmed into bits MR16
and MR17 of the Mode Register, then the device is selected, if
there is no match the device is effectively shut down.
MultiplexingThe onboard multiplexers of the ADV7152 eliminate the need
resultant pixel or dot clock rate of 100 MHz. As mentioned in
the previous section, the ADV7152 supports a number of color
data formats in 2:1 and 1:1 multiplex modes.
In 1:1 multiplex mode, the ADV7152 is clocked using the
LOADIN signal. This means that there is no requirement for
differential ECL inputs on CLOCK and CLOCK. The pixel
clock is connected directly to LOADIN. (Note: The ECL
CLOCK can still be used to generate LOADOUT PRGCKOUT,
etc.)
ADV7152Alternatively, the ADV7152 CLOCK inputs can be driven by a
Programmable Clock Generator (Figure 13), such as the
ICS1562. The ICS1562 is a monolithic, phase-locked-loop,
clock generator chip. It is capable of synthesizing differential
ECL output frequencies in a range up to 220 MHz from a single
low frequency reference crystal.
Figure 13.PLL Generator Driving CLOCK, CLOCK of the
ADV7152
CLOCK CONTROL SIGNALS LOADOUTThe ADV7152 generates a LOADOUT control signal which
runs at a divided down frequency of the pixel CLOCK. The
frequency is automatically set to the programmed multiplex
rate, controlled by CR36 of Command Register 3.
fLOADOUT = fCLOCK/22:1 Multiplex Mode
fLOADOUT = fCLOCK1:1 Multiplex Mode
The LOADOUT signal is used to directly drive the LOADIN
pixel latch signal of the ADV7152. This is most simply achieved
by tying the LOADOUT and LOADIN pins together. Alterna-
tively, the LOADOUT signal can be used to drive the frame
buffer’s shift clock signals, returning to the LOADIN input de-
layed with respect to LOADOUT.
Figure 14.LOADOUT vs. Pixel Clock Input (CLOCK, CLOCK)
If it is not necessary to have a known fixed number of pipeline
delays, then there is no limitation on the delay between LOAD-
OUT and LOADIN (LOADOUT(1) and LOADOUT(2)).
LOADIN and Pixel Data must conform to the setup and hold
times (t8 and t9).
If however, it is required that the ADV7152 has a fixed number
of pipeline delays (tPD), LOADOUT and LOADIN must con-
form to timing specifications t10 and τ-t11 as illustrated in Fig-
ures 4 and 5.
PRGCKOUTThe PRGCKOUT control signal outputs a user programmable
clock frequency. It is a divided down frequency of the pixel
CLOCK (see Figure 8). The rising edge of PRGCKOUT is
synchronous to the rising edge of LOADOUT
fPRGCKOUT = f CLOCK/N
where N = 4, 8, 16 or 32.
One application of the PRGCKOUT is to use it as the master
clock frequency of the graphics subsystems processor or
controller.
SCKIN, SCKOUTThese video memory signals are used to minimize external sup-
port chips. Figure 15 illustrates the function that is provided.
An input signal applied to SCKIN is synchronously AND-ed
with the video blanking signal (BLANK). The resulting signal is
output on SCKOUT. Figure 7 of the Timing Waveform section
shows the relationship between SCKOUT, SCKIN and
BLANK.
The SCKOUT signal is essentially the video memory shift con-
trol signal. It is stopped during the screen retrace. Figure 16
shows a suggested frame buffer to ADV7152 interface. This is a
minimum chip solution and allows the ADV7152 control the
overall graphics system clocking and synchronization.
Figure 16.
Pipeline Delay and On-Board CalibrationThe ADV7152 has a fixed number of pipeline delays (tPD), so
long as timings t10 and τ-t11 are met. However, if a fixed pipeline
delay is not a requirement, timings t10 and τ-t11 can be ignored,
a calibration cycle must be run and there is no restriction on
LOADIN to LOADOUT timing. If timings t10 and τ-t11 are not
met, the part will function correctly though with an increased
number of pipeline delays, tPD + N CLOCKS (for 2:1 mode
N = 2, for 1:1 mode N = 0). The ADV7152 has onboard cali-
bration circuitry which synchronizes pixel data and LOADIN
with the internal ADV7152 clocking signals. Calibration can be
performed in two ways: during the devices initialization se-
quence by toggling two bits of the Mode Register, MR10 fol-
lowed by MR15, or by writing a “1” to Bit CR10 of Command
Register 1 which executes a calibration on every Vertical Sync.
COLOR VIDEO MODESThe ADV7152 supports a number of color video modes all at
the maximum video rate. Command bits CR24–CR27 of Com-
mand Register 2 along with Bit MR11 of Mode Register 1 deter-
mine the color mode.
24-Bit “Gamma” True Color
(CR25, CR26, CR27 = 1, 1, 1 and MR11 = 1)The part is set to 24-bit/30-bit True-Color operation. The pixel
port accepts 24 bits of color data which is directly mapped to
the Look-Up Table RAM. The Look-Up Table is configured as
a 256 location by 30 bits deep RAM (10 bits each for Red,
Green and Blue). The output of the RAM drives the DACs with
30-bit data (10 bits each for Red, Green and Blue). The RAM is
preloaded with a user determined, nonlinear function, such as a
gamma correction curve.
Figure 17.24-Bit to 30-Bit True-Color Configuration
This mode allows for the display of full 24-bit, Gamma-
Corrected True-Color Images.
24-Bit “Standard” True Color
(CR25, CR26, CR27 = 1, 1, 1 and MR11 = 0)This mode sets the part into direct 24-bit True-Color operation.
The pixel port accepts 24 bits of color data which is directly
mapped to Look-Up Table RAM. The Look-Up Table is con-
figured as a 256 location by 24 bits deep RAM (8 bits each for
Red, Green and Blue) and essentially acts as a bypass RAM.
The output of the RAM drives the DACs with 24-bit data (8
bits each for Red, Green and Blue). The RAM is preloaded with
a linear function.
This mode allows for the display of full 24-bit True-Color
Figure 18.
8-Bit “Gamma” Pseudo Color
(CR25, CR26, CR27 = X, 0, 0 or X, 1, 0 or X, 0, 1 and
MR11 = 1)This mode sets the part into 8-bit Pseudo-Color operation. The
pixel port accepts 8 bits of pixel data which indexes a 30-bit
word in the Look-Up Table RAM. The Look-Up Table is con-
figured as a 256 location by 30 bits deep RAM (10 bits each for
Red, Green and Blue). The output of the RAM drives the
DACs with 30-bit data (10 bits each for Red, Green and Blue).
This mode allows for the display of 256 simultaneous colors out
of a total palette of millions of addressable colors.
8-Bit “Standard” Pseudo Color
(CR25, CR26, CR27 = X, 0, 0 or X, 1, 0 or X, 0, 1 and
MR11 = 0)This mode sets the part into 8-bit Pseudo-Color operation. The
pixel port accepts 8 bits of pixel data which indexes a 24-bit
word in the Look-Up Table RAM. The Look-Up Table is con-
figured as a 256 location by 24 bits deep RAM (10 bits each for
Red, Green and Blue). The output of the RAM drives the
DACs with 24-bit data (8 bits each for Red, Green and Blue).
ADV7152This mode allows for the display of 256 simultaneous colors out
of a total palette of millions of addressable colors.
15-Bit “Gamma” True Color
(CR24, CR25, CR26, CR27 = 0, 0, 1, 1 or 1, 0, 1, 1 and
MR11 = 1)The part is set to 15-bit True-Color operation. The pixel port
accepts 15 bits of color data which is mapped to the 5 LSBs of
each of the red, green and blue palettes of the Look-Up Table
RAM. The Look-Up Table is configured as a 32 location by 30
bits deep RAM (10 bits each for Red, Green and Blue). The
output of the RAM drives the DACs with 30-bit data (10 bits
each for Red, Green and Blue).
Figure 21.15-Bit to 30-Bit True-Color Configuration
This mode allows for the display of 15-bit, Gamma-Corrected
True-Color Images.
15-Bit “Standard” True Color
(CR24, CR25, CR26, CR27 = 0, 0, 1, 1 or 1, 0, 1, 1 and
MR11 = 0)The part is set to 15-bit True-Color operation. The pixel port
accepts 15 bits of color data which is mapped to the 5 LSBs of
each of the red, green and blue palettes of the Look-Up Table
RAM. The Look-Up Table is configured as a 32 location by 24
bits deep RAM (8 bits each for Red, Green and Blue). The out-
put of the RAM drives the DACs with 24-bit data (8 bits each
for Red, Green and Blue).
Figure 22.15-Bit to 24-Bit True-Color Configuration
This mode allows for the display of 15-bit True-Color Images.
PIXEL PORT MAPPINGThe pixel data to the ADV7152 is automatically mapped in the
parts pixel port as determined by the pixel data mode pro-
grammed (Bits CR24–CR27 of Command Register 2).
Pixel data in the 24-bit True-Color modes is directly mapped to
the 24 color inputs R0–R7, G0–G7 and B0–B7.
Figure 23. 15-Bit True-Color Mapping Using R3–R7, G3–G7
and B3–B7
There are three modes of operation for 8-bit Pseudo Color.
Each mode maps the input pixel data differently. Data can be
input one of the three color channels, R0–R7 or G0–G7 or
B0–B7.
The part has two modes of operation for 15-bit True Color. In
the first mode, data is input to the device over the red, green
and blue channel (R3–R7, G3–G7 and B3–B7) and is internally
mapped to locations 0 to 31 of the Look-Up Table (LUT) ac-
cording to Figure 23. In the second mode, data is input to the
device over just two of the color ports, red and green (R0–R7
and G0–G6) and is internally mapped to LUT locations 0 to 31
according to Figure 24. (Note: Data on unused pixel inputs is
ignored.)
Figure 24. 15-Bit True-Color Mapping Using R0–R7
and G0–G6
MICROPROCESSOR (MPU) PORTThe ADV7152 supports a standard MPU Interface. All the
functions of the part are controlled via this MPU port. Direct
access is gained to the Address Register, Mode Register and all
the Control Registers as well as the Color Palette. The follow-
ing sections describe the setup for reading and writing to all of
the devices registers.
MPU InterfaceThe MPU interface (Figure 25) consists of a bidirectional,
10-bit wide databus and interface control signals CE, C0, C1
and R/W. The 10-bit wide databus is user configurable as
illustrated.
Table II.Databus Width Table
Register MappingThe ADV7152 contains a number of onboard registers includ-
ing the Mode Register (MR17–MR10), Address Register (A7–
A0) and nine Control Registers as well as Red (R9–R0), Green
(G9–G0) and Blue (B9–B0) Color Registers. These registers
control the entire operation of the part. Figure 26 shows the
internal register configuration.
Control lines C1 and C0 determine which register the MPU is
accessing. C1 and C0 also determine whether the Address Reg-
ister is pointing to the color registers and look-up table RAM or
the control registers. If C1, C0 = 1, 0, the MPU has access to
whatever control register is pointed to by the Address Register
(A7–A0). If C1, C0 = 0, 1, the MPU has access to the Look-Up
Table RAM (Color Palette) through the associated color regis-
ters. The CE input latches data to or from the part.
The R/W control input determines between read or write ac-
cesses. The Truth Tables III and IV show all modes of access to
the various registers and color palette for both the 8-bit wide
databus configuration and 10-bit wide databus configuration. It
should be noted that after power-up, the devices MPU port is
automatically set to 10-bit wide operation (see Power-On Reset
section).
Color Palette AccessesData is written to the color palette by first writing to the address
register of the color palette location to be modified. The MPU
performs three successive write cycles for each of the red, green
and blue registers (10 bit or 8 bit). An internal pointer moves
from red to green to blue after each write is completed. This
pointer is reset to red after a blue write or whenever the address
register is written. During the blue write cycle, the three bytes of
red, green and blue are concatenated into a single 30-bit/24-bit
word and written to the RAM location as specified in the ad-
dress register (A7–A0). The address register then automatically
increments to point to the next RAM location and a similar red,
green and blue palette write sequence is performed. The address
register resets to 00H following a blue write cycle to color pal-
ette RAM location FFH.
ADV7152Data is read from the color palette by first writing to the address
register of the color palette location to be read. The MPU per-
forms three successive read cycles from each of the red, green
and blue locations (10-bit or 8-bit) of the RAM. An internal
pointer moves from red to green to blue after each read is com-
pleted. This pointer is reset to red after a blue read or whenever
the address register is written. The address register then auto-
matically increments to point to the next RAM location, and a
similar red, green and blue palette read sequence is performed.
The address register resets to 00H following a blue read cycle of
color palette RAM location FFH.
Register AccessesThe MPU can write to or read from all of the ADV7152s regis-
ters. C0 and C1 determine whether the Mode Register or Ad-
dress Register is being accessed. Access to these registers is
direct. The Control Registers are accessed indirectly. The
Address Register must point to the desired Control Register.
Figure 28 along with the 8-bit and 10-bit Interface Truth Tables
illustrate the structure and protocol for device communication
over the MPU port.
Table III. Interface Truth Table (10-Bit Databus Mode)
ADDRESS REG + 1
* THIS REGISTER IS READ ONLY.
POINTS TO LOCATION
CORRESPONDING TO
ADDRESS REG (A7–A0)
C1 = 0
C0 = 1
C1 = 1
C0 = 1
C1 = 0
C0 = 0
C1 = 1
C0 = 0Figure 26.Internal Register Configuration and Address Decoding
