ADV7151LS170 ,CMOS 220 MHz Pseudo-Color Graphics Triple 10-Bit Video RAM-DACapplications.
The part is controlled and programmed through the micropro-
cessor (MPU) port. The ..
ADV7151LS220 ,CMOS 220 MHz Pseudo-Color Graphics Triple 10-Bit Video RAM-DACAPPLICATIONS
High Resolution Graphics
ADV7151
The ADV7151 (ADV*) is a complete analog output ..
ADV7152LS110 ,CMOS 220 MHz True-Color Graphics Triple 10-Bit Video RAM-DACspecifications T to T unless otherwise noted.)L MIN MAXParameter All Versions Unit Test Conditions/ ..
ADV7152LS135 ,CMOS 220 MHz True-Color Graphics Triple 10-Bit Video RAM-DACGENERAL DESCRIPTION®Palette Priority Select RegistersThe ADV7152 (ADV ) is a complete analog output ..
ADV7152LS220 ,CMOS 220 MHz True-Color Graphics Triple 10-Bit Video RAM-DACSPECIFICATIONS (V = +5 V; V = +1.235 V; R = 280 V. IOR, IOG, IOB (R = 37.5 V,AA REF SET L2C = 10 pF ..
ADV7152LS85 ,CMOS 220 MHz True-Color Graphics Triple 10-Bit Video RAM-DACCHARACTERISTICS (V = +5 V; V = +1.235 V; R = 280 V. IOR, IOG, IOB (R = 37.5 V, C = 10 pF);AA REF SE ..
AM27C512-150DE , 512 Kilobit ( 64 K x 8-Bit ) CMOS EPROM Speed options as fast as 55 ns
AM27C512-150DIB , 512 Kilobit ( 64 K x 8-Bit ) CMOS EPROM Speed options as fast as 55 ns
AM27C512-150JC , 512 Kilobit ( 64 K x 8-Bit ) CMOS EPROM Speed options as fast as 55 ns
AM27C512-150JC , 512 Kilobit ( 64 K x 8-Bit ) CMOS EPROM Speed options as fast as 55 ns
AM27C512-150JC , 512 Kilobit ( 64 K x 8-Bit ) CMOS EPROM Speed options as fast as 55 ns
AM27C512-150PC , 512 Kilobit ( 64 K x 8-Bit ) CMOS EPROM Speed options as fast as 55 ns
ADV7151LS110-ADV7151LS170-ADV7151LS220
CMOS 220 MHz Pseudo-Color Graphics Triple 10-Bit Video RAM-DAC
ANALOG
DEVICES
220 MHz Pseudo-Color Graphics
Triple lil-Bit Video RAM-DAC
FEATURES
220 MHz, 10-Bit (30-Bit Gamma Corrected) Pseudo
Color (lndexed-Color)
Triple 10-Bit "Gamma Correcting" D/A Converters
Triple 256 x 10 (256 x 30) Color Palette RAM
(256 Colors out of 1 Billion)
On-Chip Clock Control Circuit
Palette Priority Select Registers
RS-343AlRS-170 Compatible Analog Outputs
TTL Compatible Digital Inputs
Standard MPU " Interface
10-Bit Parallel Structure
8+2 Byte Structure
Multiplexed Pixel Input Ports; 1:1, 2:1, 4:1
+5 V CMOS Monolithic Construction
100-Lead Plastic Quad Flatpack (OFP)
Thermally Enhanced to Achieve 0oc < 1.0°C/W
MODES OF OPERATION
8-Bit Pseudo Color
Cd 220 MHz
tCr 170 MHz
(trt 135 MHz
Cd 110 MHz
C4 85 MHz
APPLICATIONS
High Resolution Graphics
ADV7151
The ADV7151 (ADV*) is a complete analog output, Video
RAM-DAC on a single CMOS monolithic chip. The part is spe-
cifically designed for use in high performance, color graphics
workstations. The ADV7151 integrates a number of graphic
functions onto one device allowing 8-bit Pseudo-Color (Indexed-
Color) operation at the maximum screen update rate of
220 MHz.
The device consists of three, high speed, lO-bit, video D/A con-
verters (RGB), three 256 X 10 (one 256 y, 30) color look-up
tables, palette priority selects, a pixel input data multiplexer/
serializer and a clock generator/divider circuit. The ADV7151 is
capable of 1:1, 2:1 and 4:1 multiplexing. The on-board palette
priority select inputs enable multiple palette devices to be con-
nected together for use in multipalette and window applications.
The part is controlled and programmed through the micropro-
cessor (MPU) port. The part also contains a number of on-board
test registers, associated with self diagnostic testing of the device.
*ADV is a registered trademark of Analog Devices, Inc.
(Continued on page 12)
FUNCTIONAL BLOCK DIAGRAM
256.C0LOR/GAMMA
a PALETTE RAM ADV7151
( , V IOR
.2 RED 10, - -
I a p 256 x 10 ' IOR
RED (RT-RO), Ii") I 32 e l
GREEN (GT-GO), I g MUX g, a, b GREEN 10,» man 106
BLUE (BF-BO) 8 L 4:1 ' / 256 X 10 ' GREEN DAC m
COLOR DATA Vie) f
I P BLUE
1 10, man I08
I a o tctr-- 256x10 ,> BLUE DAC IO-B
I I V R
PALETTE a MUX 2 I SYNC _
SELECTS 4:1 ' OUTPUT IPLL
(PS0,PS1) CONTROL REGISTERS SVNCOUT
CLOCK CONTROL PIXEL MASK - VOLTAGE VnEF
LOADIN REG’STER comma DATA TO REFERENCE RSET
LOADOUT CLOCK DIVIDE TEST - "tttgg PALETTES CIRCUIT COMP
& ADDRESS REGISTERS '-'
PRGCKOUT SYNCHRONlzATlON REGISTER MODE REV s ON so COLOR REGISTERS
-1 I I
sCSCKIN CIRCUIT ADDR REGISTER REGIETER - REGISTER RED GREEN BLUE
KOUT :32 -16. -8, " " (AT-AO) REGISTER REGISTER REGISTER
BLANK t
I I I MPU PORT I
I ECL TO CMOS I i
CLOCK 10 (8r2)
5g n/W co CI D9-DO GND
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, PO. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700
Fax: 617/326-8703
!lll.l,,7,n1,11.iii.-,
SPECIFICATIONS (hal = +5 ll; la, = +1235 ll;
= 28ll n, IUR, IOG. IUB (h-- 37.5 n,
CL- - lil pF); IOR Iilil = Mil. All specifications TMIN to U/ unless otherwise noted.)
Parameter All Versions Unit Test Conditions/Comments
STATIC PERFORMANCE
Resolution (Each DAC) 10 Bits
Accuracy (Each DAC)
Integral Nonlinearity LSB max
Differential Nonlinearity tl LSB max Guaranteed Monotonic
Gray Scale Error t5 % Gray Scale max
Coding Binary
DIGITAL INPUTS (Excluding CLOCK, CLOCK)
Input High Voltage, V,NH 2 V min
Input Low Voltage, VINL 0.8 V max
Input Current, hr: :10 wh max VIN = 0.4 V or 2.4 V
Input Capacitance, Cm 10 pF typ
CLOCK INPUTS (CLOCK, CLOCK)
Input High Voltage, V,NH VAA - 1.0 V min
Input Low Voltage, VINL VAA - 1.6 V max
Input Current, I,N t10 WA max VIN = 0.4 V or 2.4 V
Input Capacitance, Cm 10 pF typ
DIGITAL OUTPUTS
Output High Voltage, Vor, 2.4 V min [SOURCE = 400 MA
Output Low Voltage, Von 0.4 V max IsiNK = 3.2 mA
Floating-State Leakage Current 20 WA max
Floating-State Output Capacitance 20 pF typ
ANALOG OUTPUTS
Gray Scale Current Range 15 mA min
22 mA max
Output Current
White Level Relative to Blank 17.69 mA min Typically 19.05 mA
20.40 mA max
White Level Relative to Black 16.74 mA min Typically 17.62 mA
18.50 mA max
Black Level Relative to Blank 0.95 mA min Typically 1.44 mA
1.90 mA max
Blank Level on IOR, 10B 0 " min Typically 5 WA
50 " max
Blank Level on ICC 6.29 mA min Typically 7.62 mA
_ 8.96 mA max
Sync Level on IOG 0 11A min Typically 5 WA
50 " max
LSB Size 17.22 " typ
DAC-to-DAC Matching 2 % max Typically 1%
Output Compliance, V oc 0 V min
+ 1.4 V max
Output Impedance, Rour 100 kil typ
Output Capacitance, Cowr 30 pF max [OUT = 0 mA
VOLTAGE REFERENCE
Voltage Reference Range, VREF 1.14/ 1.26 V min/V max VREF = 1.235 V for Specified Performance
Input Current, IVREF +5 11A typ
POWER REQUIREMENTS
V AA 5 V nom
[M5 400 mA max 220 MHz Parts
I AA 370 mA max 170 MHz Parts
IAA 350 mA max 135 MHz Parts
IAA 330 mA max 110 MHz Parts
IAA 315 mA max 85 MHz Parts
Power Supply Rejection Ratio 0.5 %/% max Typically 0.12%/%: COMP = 0.1 WF
DYNAMIC PERFORMANCE
Clock and Data Feedthrough' 5 -30 dB typ
Glitch Impulse 50 pV secs typ
DAC-to-DAC Crosstalk“ -23 dB typ
':59'o for all versions.
2Temperature range (TMIN to TMAX),' 0° C to +70'C; T, (Silicon Junction Temperature)_ < 100°C
'Pixel Port IS continuously clocked with data corresponding to a linear ramp. T, - 100°C.
"Clock and data feedthrough is a function of the amount of overshoot and undershoot on the digital inputs. Glitch impulse includes clock and data feedthrough.
'TTL input values are 0 to 3 volts, with input rise/fall times S3 ns, measured the 10% and 90% points. Timing reference points at 50% for inputs and outputs.
"DAC-to-DAC crosstalk is measured by holding one DAC high while the other two are making low-to-high and high-to-low transitions.
Specifications subject to change without notice.
REV. A
ADV7151
TIMING tyatgirrERIsnCs1 (sz = +5 ll; Iles, = +1235 ll; RSET = 230 n. IOR, IOG, " (h = 37.5 n, ik = Ill pF);
IOR, IOG, I08 = Mil. Ill specifications TMIN to TMAX3 unless otherwise noted.)
CLOCK CONTROL AND PIXEL PORT"
220 MHz 170 MHz 135 MHz 110 MHz 85 MHz '
Parameter Version Version Version Version Version Units Conditions/Comments
chocx 220 170 135 110 85 MHz max Pixel CLOCK Rate
t, 4.55 5.88 7.4 9.1 11.77 ns min Pixel CLOCK Cycle Time
te 2 2.5 3.2 4 4 ns min Pixel CLOCK High Time
ts 1 2 2.5 3 4 4 ns min Pixel CLOCK Low Time
t, 10 10 10 10 10 ns max Pixel CLOCK t0 LOADOUT Delay
{LOADIN -' LOADIN Clocking Rate
1:1 Multiplexing 110 110 110 110 85 MHz max
2:1 Multiplexing 110 85 67.5 55 42.5 MHz max
4:1 Multiplexing 55 42.5 42.5 33.75 27.5 21.25 MHz max
ts LOADIN Cycle Time
1:1 Multiplexing 9.1 9.1 9.1 9.1 11.76 ns min
2:1 Multiplexing 9.1 11.76 14.8 18.18 23.53 ns min
4:1 Multiplexing 18.18 23.53 29.63 36.36 47.1 ns min
tr, LOADIN High Time
1:1 Multiplexing 4 4 4 4 4 ns min
2:1 Multiplexing 4 5 6 8 9 ns min
4:1 Multiplexing 8 9 12 15 18 ns min
t, LOADIN Low Time
1:1 Multiplexing 4 4 4 4 4 ns min
2:1 Multiplexing 4 5 6 8 9 ns min
4:1 Multiplexing 8 9 12 15 18 ns min
ts 0 0 0 0 0 ns min Pixel Data Setup Time
ts, 5 5 5 5 5 ns min Pixel Data Hold Time
tn, 0 0 0 1 0 0 ns min LOADOUT to LOADIN Delay
T-t115 m-5 m-5 m-5 7-5 7-4 ns max LOADOUT Io LOADIN Delay
rm," Pipeline Delay
1:1 Multiplexing 5 5 5 5 5 CLOCKS (l X CLOCK = twl
2:1 Multiplexing 6 6 6 6 6 CLOCKS
4:1 Multiplexing 8 8 8 8 8 CLOCKS
tn 10 10 10 10 10 ns max Pixel CLOCK t0 PRGCKOUT Delay
ti3 5 5 5 5 5 l ns max SCKIN t0 SCKOUT Delay
tr, 5 5 , 5 5 5 1 ns min BLANK t0 SCKIN Setup Time
tis 1 1 1 1 1 1 1 ns min BLANK to SCKIN Hold Time
ANALOG OUTPUTS'
220 MHz 170 MHz 135 MHz 110 MHz 85 MHz
Parameter Version Version Version Version Version Units Conditions/Comments
tus 15 15 15 15 15 ns typ Analog Output Delay
[17 1 1 1 1 1 ns typ Analog Output Rise/Fall Time
[18 15 15 1 15 15 15 ns typ Analog Output Transition Time
tso: 2 2 [ 2 2 2 ns max Analog Output Skew (IOR, IOG, 10B)
0 0 0 0 0 ns typ
MPU PORTS‘ 9
220 MHz 170 MHz 135 MHz 110 MHz 85 MHz
Parameter Version Version Version Version Version Units Conditions/Comments
tw 3 3 1 3 3 1 3 , ns min W, co, Cl to E Setup Time
teo 10 10 _ 10 10 1 IO ns min aw, C0, C1 to CE Hold Time
ter 45 45 f 45 45 1 45 ns min fili Low Time
tee 25 25 25 25 25 ns min CE High Time
t.vs 5 5 5 5 5 ns min CE Asserted t0 Databus Driven
tug 45 45 45 i' 45 45 _ ns max CE Asserted to Data Valid
[259 20 20 20 ' 20 20 ns max CE Disabled to Databus Three-Stated
5 5 S _ 5 1 5 ns min
tet, 20 20 20 20 20 ns min Write Data (DO-D9) Setup Time
te; 5 5 5 i 5 _ 5 ns min Write Data (DO-D9) Hold Time
REV. A -3-
ADV7151
NOTES -
"TTL input values are 0 t0 3 volts, with input rise/fall times :- 3 ns, measured between the 10% and 90% points. ECL inputs (CLOCK, CLOCK) are
VAA-0.8 V to VA.,-1.8 V, with input rise/fall times Ec. 2 ns, measured between the 10% and 90% points. Timing reference points at 50% for inputs and out-
puts. Analog output load " 10 pF. Databus (DO-D9) loaded as shown in Figure 1. Digital output load for LOADOUT, PRGCKOUT and SCKOUT
S 30 pF.
2:5% for all versions.
'Temperature range (TMIN to TMAX); 0°C to +70'''C; T, (Silicon Junction Temperature) 5 100°C.
"Pixel Port consists of the following inputs: Pixel Inputs: PO-P [A, B, C, D]; Palette Selects: PSO [A, B, C, D] PSI [A, B, C, D]; Pixel Controls: SYNC,
BLANK; Clock Inputs: CLOCK, CLOCK, LOADIN, SCKIN; Clock Outputs: LOADOUT, PRGCKOUT, SCKOUT.
57 is the LOADOUT Cycle Time and is a function of the Pixel CLOCK Rate and the Multiplexing Mode: 1:1 multiplexing; T = CLOCK = t, nr. 2:l
multiplexing; T = CLOCK A 2 = 2 X t1 ns: 4:1 multiplexing; T = CLOCK A 4 = 4 / tl ns.
"These fixed values for Pipeline Delay are valid under conditions where tu, and T-IH are met. If either tu, or T-til are not met, the part will operate but the
Pipeline Delay is increased by an additional 2 Clock Cycles for 2:1 Mode and is increased by an additional 4 Clock Cycles for 4:1 Mode, after calibration is
performed.
7Output delay measured from the 50% point of the rising edge of CLOCK t0 the 50% point of full-scale transition. Output rise/fall time measured between the
10% and 90% points of full-scale transition. Transition time measured from the 50% point of full-scale transition to the output remaining within tl LSB.
/1'ransition time does not include clock and data feedthrough.)
"t13 and tr, are measured with the load circuit of Figure 1 and defined as the time required for an output to cross 0.4 V or 2.4 V.
''t,, is derived from the measured time taken by the data outputs to change by 0.5 V when loaded with the circuit of Figure l. The measured number is then
extrapolated back to remove the effects of charging the 100 pF capacitor. This means that the time, tss, quoted in the Timing Characteristics is the true value
for the device and as such is independent of external databus loading capacitances.
Specifications subject to change without notice.
'souace
Figure 1. Load Circuit for Databus Access and Relinquish Times
CLOCK Jr
cu-lu/N/Ny/N/N/N/Ny/_/lc/NCC/Ny/_
- <- te
LOADOUT
(1:1 MULTIPLEXING) -,/
LOADOUT
(2:1 MULTIPLEXING) _/
LOADOUT
(4:1 MULTIPLEXING) _/
Figure 2. LOADOUT vs. Pixel Clock Input (CLOCK, CLOCK)
-4- REV. A
