ADV7123KST140 ,CMOS, 240 MHz Triple 10-Bit High Speed Video DACSPECIFICATIONS otherwise noted, T = 1108C)J MAX1Parameter Min Typ Max Units Test ConditionsSTATIC ..
ADV7123KST-140 ,CMOS, 240 MHz Triple 10-Bit High Speed Video DACGENERAL DESCRIPTION3. Compatible with a wide variety of high resolution color®The ADV7123 (ADV ) is ..
ADV7123KST50 ,CMOS, 240 MHz Triple 10-Bit High Speed Video DACSPECIFICATIONS otherwise noted, T = 1108C)J MAX2Parameter Min Typ Max Units Test ConditionsSTATIC ..
ADV7123KSTZ140 , CMOS, 330 MHz Triple 10-Bit High Speed Video DAC
ADV7123KSTZ140 , CMOS, 330 MHz Triple 10-Bit High Speed Video DAC
ADV7123KST-Z140 , CMOS, 330 MHz Triple 10-Bit High Speed Video DAC
AM27C4096-100DC , 4 Megabit (256 K x 16-Bit) CMOS EPROM
AM27C4096-100DI , 4 Megabit (256 K x 16-Bit) CMOS EPROM
AM27C4096-105DC , 4 Megabit (256 K x 16-Bit) CMOS EPROM
AM27C4096-105DI , 4 Megabit (256 K x 16-Bit) CMOS EPROM
AM27C4096-120DE , 4 Megabit (256 K x 16-Bit) CMOS EPROM
AM27C4096-120DI , 4 Megabit (256 K x 16-Bit) CMOS EPROM
ADV7123JST240-ADV7123-JST240-ADV7123JST-240-ADV7123KST140-ADV7123KST-140-ADV7123KST50
CMOS, 240 MHz Triple 10-Bit High Speed Video DAC
REV.A
CMOS, 240 MHzriple 10-Bit High Speed Video DAC
FUNCTIONAL BLOCK DIAGRAM
FEATURES
240 MSPS Throughput Rate
Triple 10-Bit D/A Converters
SFDR
–70 dB at fCLK = 50 MHz; fOUT = 1 MHz
–53 dB at fCLK = 140 MHz; fOUT = 40 MHz
RS-343A/RS-170 Compatible Output
Complementary Outputs
DAC Output Current Range 2 mA to 26 mA
TTL-Compatible Inputs
Internal Reference (1.23 V)
Single Supply +5 V/+3.3 V Operation
48-Lead LQFP Package
Low Power Dissipation (30 mW min @ 3 V)
Low Power Standby Mode (6 mW typ @ 3 V)
Industrial Temperature Range (–408C to +858C)
APPLICATIONS
Digital Video Systems (1600 3 1200 @ 100 Hz)
High Resolution Color Graphics
Digital Radio Modulation
Image Processing
Instrumentation
Video Signal Reconstruction
GENERAL DESCRIPTIONThe ADV7123 (ADV®) is a triple high speed, digital-to-analog
converter on a single monolithic chip. It consists of three
high speed, 10-bit, video D/A converters with complementary
outputs, a standard TTL input interface and a high impedance,
analog output current source.
The ADV7123 has three separate 10-bit-wide input ports. A
single +5 V/+3.3 V power supply and clock are all that are
required to make the part functional. The ADV7123 has addi-
tional video control signals, composite SYNC and BLANK.
The ADV7123 also has a power-save mode.
The ADV7123 is fabricated in a +5 V CMOS process. Its
monolithic CMOS construction ensures greater functionality
with lower power dissipation. The ADV7123 is available in a
48-lead LQFP package.
PRODUCT HIGHLIGHTS240 MSPS Throughput.Guaranteed monotonic to 10 bits.Compatible with a wide variety of high resolution color
graphics systems including RS-343A and RS-170A.
ADV is a registered trademark of Analog Devices, Inc.
ADV7123–SPECIFICATIONS
5 V SPECIFICATIONSNOTESTemperature range TMIN to TMAX: –40°C to +85°C at 50 MHz and 140 MHz, 0°C to 70°C at 240 MHz.Gain error = (Measured (FSC)/Ideal (FSC) –1) × 100), where Ideal = VREF /RSET × K × (3FFH) and K = 7.9896.Digital supply is measured with continuous clock with data input corresponding to a ramp pattern and with an input level at 0 V and VDD.4These max/min specifications are guaranteed by characterization to be over 4.75 V to 5.25 V range.
Specifications subject to change without notice.
(VAA = +5 V 6 5%, VREF = 1.235 V, RSET = 560 V, CL = 10 pF. All specifications TMIN to TMAX1 unless
otherwise noted, TJ MAX = 1108C)
ADV7123
3.3 V SPECIFICATIONS1NOTESThese max/min specifications are guaranteed by characterization to be over 3.0 V to 3.6 V range.Temperature range TMIN to TMAX: –40°C to +85°C at 50 MHz and 140 MHz, 0°C to 70°C at 240 MHz.Gain error = (Measured (FSC)/Ideal (FSC) –1) × 100), where Ideal = VREF /RSET × K × (3FFH) and K = 7.9896.Digital supply is measured with continuous clock with data input corresponding to a ramp pattern and with an input level at 0 V and VDD.
Specifications subject to change without notice.
(VAA = +3.0 V –3.6 V, VREF = 1.235 V, RSET = 560 V, CL = 10 pF. All specifications TMIN to TMAX2 unless
otherwise noted, TJ MAX = 1108C)
ADV7123–SPECIFICATIONS
5 V DYNAMIC SPECIFICATIONS1NOTESThese max/min specifications are guaranteed by characterization over 4.75 V to 5.25 V range.Note that the ADV7123 exhibits high performance when operating with an internal voltage reference, VREF.3DAC to DAC Crosstalk is measured by holding one DAC high while the other two are making low to high and high to low transitions.Clock and data feedthrough is a function of the amount of overshoot and undershoot on the digital inputs. Glitch impulse includes clock and data feedthrough.TTL input values are 0 V to 3 V, with input rise/fall times ≤3 ns, measured the 10% and 90% points. Timing reference points is 50% for inputs and outputs.
(VAA = +5 V 6 5%1, VREF = 1.235 V, RSET = 560 V, CL = 10 pF. All specifications are for
TA = +258C unless otherwise noted, TJ MAX = 1108C)
ADV7123
3.3 V DYNAMIC SPECIFICATIONSDAC PERFORMANCE
NOTES
1These max/min specifications are guaranteed by characterization over 3.0 V to 3.6 V range.
2Note that the ADV7123 exhibits high performance when operating with an internal voltage reference, VREF.
3DAC to DAC Crosstalk is measured by holding one DAC high while the other two are making low to high and high to low transitions.
4Clock and data feedthrough is a function of the amount of overshoot and undershoot on the digital inputs. Glitch impulse includes clock and data feedthrough.
5TTL input values are 0 V to 3 V, with input rise/fall times ≤3 ns, measured the 10% and 90% points. Timing reference points is 50% for inputs and outputs.
(VAA = +3.0 V–3.6 V1, VREF = 1.235 V, RSET = 680 V, CL = 10 pF. All specifications are
TA = +258C unless otherwise noted, TJ MAX = 1108C)
ADV7123
5 V TIMING–SPECIFICATIONS1NOTESTiming specifications are measured with input levels of 3.0 V (VIH) and 0 V (VIL) 0 for both 5 V and 3.3 V supplies.These maximum and minimum specifications are guaranteed over this range.Temperature range: TMIN to TMAX: –40°C to +85°C at 50 MHz and 140 MHz, 0°C to +70°C at 240 MHz.Rise time was measured from the 10% to 90% point of zero to full-scale transition, fall time from the 90% to 10% point of a full-scale transition.Measured from 50% point of full-scale transition to 2% of final value.Guaranteed by characterization.fCLK max specification production tested at 125 MHz and 5 V limits specified here are guaranteed by characterization.
Specifications subject to change without notice.
(VAA = +5 V 6 5%2, VREF = 1.235 V, RSET = 560 V, CL = 10 pF. All specifications TMIN to TMAX3
unless otherwise noted, TJ MAX = 1108C)
3.3 V TIMING–SPECIFICATIONS1CLOCK CONTROL
NOTESTiming specifications are measured with input levels of 3.0 V (VIH) and 0 V (VIL) 0 for both 5 V and 3.3 V supplies.These maximum and minimum specifications are guaranteed over this range.Temperature range: TMIN to TMAX: –40°C to +85°C at 50 MHz and 140 MHz, 0°C to +70°C at 240 MHz.Rise time was measured from the 10% to 90% point of zero to full-scale transition, fall time from the 90% to 10% point of a full-scale transition.Measured from 50% point of full-scale transition to 2% of final value.Guaranteed by characterization.fCLK max specification production tested at 125 MHz and 5 V limits specified here are guaranteed by characterization.
Specifications subject to change without notice.
CLOCK
NOTES:
1. OUTPUT DELAY (t6) MEASURED FROM THE 50% POINT OF THE RISING EDGE OF CLOCK
TO THE 50% POINT OF FULL-SCALE TRANSITION.OUTPUT RISE/FALL TIME (t7) MEASURED BETWEEN THE 10% AND 90% POINTS OF FULL-SCALE TRANSITION.TRANSITION TIME (t8) MEASURED FROM THE 50% POINT OF FULL-SCALE TRANSITION
TO WITHIN 2% OF THE FINAL OUTPUT VALUE.
ANALOG OUTPUTS
(IOR, IOR, IOG, IOG, IOB, IOB)
DIGITAL INPUTS
(R9–R0, G9–G0, B9–B0,
SYNC, BLANK)t5t8Figure 1.Timing Diagram
(VAA = +3.0 V–3.6 V2, VREF = 1.235 V, RSET = 560 V, CL = 10 pF. All specifications TMIN to
TMAX3 unless otherwise noted, TJ MAX = 1108C)
ADV7123
ORDERING INFORMATIONNOTESSpecified for –40°C to +85°C operation.Specified for 0°C to +70°C operation.
ABSOLUTE MAXIMUM RATINGS1VAA to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+7 V
Voltage on any Digital Pin . . . . .GND – 0.5 V to VAA + 0.5 V
Ambient Operating Temperature (TA) . . . . .–40°C to +85°C
Storage Temperature (TS) . . . . . . . . . . . . . .–65°C to +150°C
Junction Temperature (TJ) . . . . . . . . . . . . . . . . . . . . .+150°C
Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . .+300°C
Vapor Phase Soldering (1 Minute) . . . . . . . . . . . . . . . .220°C
IOUT to GND2 . . . . . . . . . . . . . . . . . . . . . . . . . . . .0 V to VAA
NOTES
1Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute maximum rating condi-
tions for extended periods may affect device reliability.
2Analog Output Short Circuit to any Power Supply or Common can be of an
indefinite duration.
PIN CONFIGURATIONPSAVER8R2R6R5R7R0R1
VREF
COMP
IOR
IOR
IOG
IOG
VAAB1B2B3
SYNC
VAA
IOB
IOB
GNDB7B8B9
SET
CLOCK
BLANK
GNDR4
CAUTIONESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the ADV7123 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
