ADV601JS12 ,Low Cost Multiformat Video Codecapplications, so it is advisableto evaluate image quality of known source material at differentcomp ..
ADV601LCJST ,Ultralow Cost Video Codecapplications, so it isadvisable to evaluate image quality of known source material atdifferent comp ..
ADV611JST ,CLOSED CIRCUIT TV DIGITAL VIDEO CODECapplications, so it is advisableHost Interface (Compressed Data) Register Timing . . . . . . . 42to ..
ADV611JST ,CLOSED CIRCUIT TV DIGITAL VIDEO CODECGENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . 1COMPARING THE ADV6xx FAM ..
ADV611JSTZ ,Closed Circuit TV Digital Video CodecGENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . 1COMPARING THE ADV6xx FAM ..
ADV7120KN30 ,CMOS 80 MHz, Triple 8-Bit Video DACAPPLICATIONSREDR088REGISTERIORHigh Resolution Color Graphics DACR7CAE/CAD/CAM
AM27C256-255DI , 256 Kilobit (32 K x 8-Bit) CMOS EPRO
AM27C256-45DC , 256 Kilobit (32 K x 8-Bit) CMOS EPRO
AM27C256-45DI , 256 Kilobit (32 K x 8-Bit) CMOS EPRO
AM27C256-55DI , 256 Kilobit (32 K x 8-Bit) CMOS EPRO
AM27C256-55JC , 256 Kilobit (32,768 x 8-Bit) CMOS EPROM
AM27C256-70DC , 256 Kilobit (32 K x 8-Bit) CMOS EPRO
ADV601JS12
Low Cost Multiformat Video Codec
REV.0
Low Cost
Multiformat Video Codec
FUNCTIONAL BLOCK DIAGRAM
HOST
256K X 16-BIT DRAM
(FIELD STORE)
DSP
(OPTIONAL)
DIGITAL
COMPONENT
VIDEO I/O
FEATURES
Precise Compressed Bit Rate Control
Field Independent Compression
Flexible Video Interface Supports All Common
Formats, Including CCIR-656
General Purpose 8-, 16- or 32-Bit Host Interface With
512 Deep 32-Bit FIFO
PERFORMANCE
Real-Time Compression Or Decompression of CCIR-601
And Square Pixel Video:
720 3 288 @ 50 Fields/Sec — PAL
768 3 288 @ 50 Fields/Sec — PAL
720 3 243 @ 60 Fields/Sec — NTSC
640 3 243 @ 60 Fields/Sec — NTSC
Compression Ratios from Visually Loss-Less To 350:1
Visually Loss-Less Compression At 4:1 on Natural
Images (Typical)
APPLICATIONS
Nonlinear Video Editing
Video Capture Systems
Remote CCTV Surveillance
Digital Camcorders
Broadcast Quality Video Distribution Systems
Video Insertion Equipment
Image And Video Archival Systems
Digital Video Tape
High Quality Video Teleconferencing
GENERAL DESCRIPTIONThe ADV601 is a very low cost, single chip, dedicated function,
all digital CMOS VLSI device capable of supporting visually
loss-less to 350:1 real-time compression and decompression of
CCIR-601 digital video at very high image quality levels. The
chip integrates glueless video and host interfaces with on-chip
SRAM to permit low part count, system level implementations
suitable for a broad range of applications.
The ADV601 is a video encoder/decoder optimized for real-time
compression and decompression of interlaced digital video. All
features of the ADV601 are designed to yield high performance
at a breakthrough systems-level cost. Additionally, the unique
sub-band coding architecture of the ADV601 offers you many
application-specific advantages. A review of the General Theory
of Operation and Applying the ADV601 sections will help you
get the most use out of the ADV601 in any given application.
The ADV601 accepts component digital video through the
Video Interface and outputs a compressed bit stream though the
Host Interface in Encode Mode. While in Decode Mode, the
ADV601 accepts a compressed bit stream through the Host
Interface and outputs component digital video through the
Video Interface. The host accesses all of the ADV601’s control
and status registers using the Host Interface. An optional Digital
Signal Processor (DSP) may be used for calculating quantiza-
tion Bin Widths (BW) (instead of the host); the ADV601 sends
current field statistics and receives Bin Width results as a packet
I/O over the DSP serial port interface. A generic fixed-point DSP
(for instance the ADSP-2105) is more than adequate for these
calculations. Figure 1 summarizes the basic function of the part.
(continued on page 2)
ADV601
TABLE OF CONTENTSThis data sheet gives an overview of the ADV601 functionality
and provides details on designing the part into a system. The
text of the data sheet is written for an audience with a general
knowledge of designing digital video systems. Where appropri-
ate, additional sources of reference material are noted through-
out the data sheet.
GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . 1
INTERNAL ARCHITECTURE . . . . . . . . . . . . . . . . . . . . . 3
GENERAL THEORY OF OPERATION . . . . . . . . . . . . . . . 3
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
THE WAVELET KERNEL . . . . . . . . . . . . . . . . . . . . . . . . . 4
THE PROGRAMMABLE QUANTIZER . . . . . . . . . . . . . . . 7
THE RUN LENGTH CODER AND HUFFMAN CODER . . 8
Encoding vs. Decoding . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
PROGRAMMER’S MODEL . . . . . . . . . . . . . . . . . . . . . . . . 8
ADV601 REGISTER DESCRIPTIONS . . . . . . . . . . . . . . . 10
PIN FUNCTION DESCRIPTIONS . . . . . . . . . . . . . . . . . 16
Video Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Host Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
DSP Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
DRAM Manager . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Compressed Data-Stream Definition . . . . . . . . . . . . . . . . 26
APPLYING THE ADV601 . . . . . . . . . . . . . . . . . . . . . . . . . 32
Using the ADV601 in Computer Applications . . . . . . . . 32
Using the ADV601 in Stand-Alone Applications . . . . . . . 32
Connecting the ADV601 to Popular Video Decoders
and Encoders . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
GETTING THE MOST OUT OF ADV601 . . . . . . . . . . . 35
ADV601 SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . 36
TEST CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
TIMING PARAMETERS . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Clock Signal Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
CCIR-656 Video Format Timing . . . . . . . . . . . . . . . . . . . 38
Gray Scale/Philips Video Timing . . . . . . . . . . . . . . . . . . . 40
Multiplexed Philips Video Timing . . . . . . . . . . . . . . . . . . 43
Host Interface (Indirect Address, Indirect Register Data,
and Interrupt Mask/Status) Register Timing . . . . . . . . 45
Host Interface (Compressed Data) Register Timing . . . . 47
DSP Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
GENERAL DESCRIPTION (Continued from page 1)
ADV601
LOW COST,
MULTIFORMAT
VIDEO CODEC
VIDEO INTERFACEHOST INTERFACE
DIGITAL VIDEO IN
(ENCODE)
DIGITAL VIDEO OUT
(DECODE)
COMPRESSED
VIDEO OUT
(ENCODE)
COMPRESSED VIDEO IN
(DECODE)
STATUS & CONTROLFigure 1.Functional Block Diagram
The ADV601 adheres to international standard CCIR-601 for
studio quality digital video. The codec also supports a range of
field sizes and rates providing high performance in computer,
PAL, NTSC, or still image environments. The ADV601 is
designed only for real-time interlaced video, full frames of video
are formed and processed as two independent fields of data.
The ADV601 supports the field rates and sizes in Table I. Note
that the maximum active field size is 768 by 288. The maximum
pixel rate is 14.75 MHz.
The ADV601 has a generic 8-/16-/32-bit host interface, which
includes a 512 position, 32-bit wide FIFO for compressed video.
With additional external hardware, the ADV601’s host interface
is suitable (when interfaced to other devices) for moving com-
pressed video over PCI, ISA, SCSI, SONET, 10 Base T, ARCnet,
HDSL, ADSL, and a broad range of digital interfaces. For a full
description of the Host Interface, see the Host Interface section.
The compressed data rate is determined by the input data rate
and the selected compression ratio. The ADV601 can achieve a
near constant compressed bit rate by using the current field
statistics in the off-chip bin width calculator on the external
DSP or Host. The process of calculating bin widths on a DSP
or Host can be “adaptive,” optimizing the compressed bit rate
in real time. This feature provides a near constant bit rate out of
the host interface in spite of scene changes or other types of
source material changes that would otherwise create bit rate
burst conditions. For more information on the quantizer, see
the Programmable Quantizer section.
The ADV601 typically yields visually loss-less compression on
natural images at a 4:1 compression ratio. Desired image quality
levels can vary widely in different applications, so it is advisable
to evaluate image quality of known source material at different
compression ratios to find the best compression range for the
Table I.ADV601 Field Rates and Sizes
StandardNOTESThe maximum active field size is 768 by 288.The maximum pixel rate is 14.75 MHz.
application. The sub-band coding architecture of the ADV601
provides a number of options to stretch compression perfor-
mance. These options are outlined on in the Applying the
ADV601 section.
The DSP serial port interface (SPORT) enables performance of
Bin Width calculations on a DSP instead of the host. The ADV601
transfers current video field statistics to the DSP and receives Bin
Width data from the DSP as packet I/O through the DSP Inter-
face. A generic fixed-point DSP (i.e., the ADSP-2105 low cost,
fixed-point DSP) is more than adequate for these calculations.
INTERNAL ARCHITECTUREThe ADV601 is composed of nine blocks. Four of these blocks
are interface blocks and five are processing blocks. The interface
blocks are the Digital Video I/O Port, the Host I/O Port, exter-
nal DRAM manager, and the DSP serial I/O Port. The process-
ing blocks are the Wavelet Kernel, the On-Chip Transform
Buffer, the Programmable Quantizer, the Run Length Coder,
and the Huffman Coder.
Digital Video I/O PortProvides a real-time uncompressed video interface to support a
broad range of component digital video formats, including “D1.”
Host I/O Port and FIFOCarries control, status, and compressed video to and from the
host processor. A 512 position by 32-bit FIFO buffers the com-
pressed video stream between the host and the Huffman Coder.
DRAM ManagerPerforms all tasks related to writing, reading, and refreshing the
external DRAM. The external host buffer DRAM is used for
reordering and buffering quantizer input and output values.
Serial Port (to Optional DSP)Supports, during encode only, communication of wavelet statis-
tics between the Wavelet Kernel and the DSP and quantizer
control information between the DSP and the Quantizer block.
The user programmed compression ratio is also sent from the
ADV601 host interface to the DSP automatically. Note that a
host processor can be used to replace the DSP functionality in
computer applications.
Wavelet Kernel (Filters, Decimator, and Interpolator)Gathers statistics on a per field basis and includes a block of
filters, interpolators, and decimators. The kernel calculates
forward and backward bi-orthogonal, two-dimensional, sepa-
rable wavelet transforms on horizontal scanned video data. This
block uses the internal transform buffer when performing wave-
let transforms calculated on an entire image’s data and so
eliminates any need for extremely fast external memories in
an ADV601-based design.
On-Chip Transform BufferProvides an internal set of SRAM for use by the wavelet trans-
form kernel. Its function is to provide enough delay line storage
to support calculation of separable two dimensional wavelet
transforms for horizontally scanned images.
Programmable QuantizerQuantizes wavelet coefficients. Quantize controls are calculated
by the external DSP or host processor during encode operations
and de-quantize controls are extracted from the compressed bit
stream during decode. Each quantizer Bin Width is computed
by the BW calculator software to maintain a constant com-
pressed bit rate or constant quality bit rate. A Bin Width is a per
block parameter the quantizer uses when determining the num-
ber of bits to allocate to each block (sub-band).
Run Length CoderPerforms run length coding on zero data and models nonzero
data, encoding or decoding for more efficient Huffman coding.
This data coding is optimized across the sub-bands and varies
depending on the block being coded.
Huffman CoderPerforms Huffman coder and decoder functions on quantized
run-length coded coefficient values. The Huffman coder/de-
coder uses three ROM-coded Huffman tables that provide ex-
cellent performance for wavelet transformed video.
GENERAL THEORY OF OPERATIONThe ADV601 processor’s compression algorithm is based on the
bi-orthogonal (7, 9) wavelet transform, and implements field
independent sub-band coding. Sub-band coders transform two-
dimensional spatial video data into spatial frequency filtered
sub-bands. The quantization and entropy encoding processes
provide the ADV601’s data compression.
The wavelet theory, on which the ADV601 is based, is a new
mathematical apparatus first explicitly introduced by Morlet and
Grossman in their works on geophysics during the mid 80s.
This theory became very popular in theoretical physics and
applied math. The late 80s and 90s have seen a dramatic growth
in wavelet applications such as signal and image processing. For
more on wavelet theory by Morlet and Grossman, see Decompo-
sition of Hardy Functions into Square Integrable Wavelets of Con-
stant Shape (journal citation listed in References section).
ENCODE
PATH
DECODE
PATHFigure 2.Encode and Decode Paths
ReferencesFor more information on the terms, techniques and underlying
principles referred to in this data sheet, you may find the follow-
ing reference texts useful. A reference text for general digital
video principles is:
Jack, K., Video Demystified: A Handbook for the Digital Engineer
(High Text Publications, 1993) ISBN 1-878707-09-4
Three reference texts for wavelet transform background infor-
mation are:
Vetterli, M., Kovacevic, J., Wavelets And Sub-band Coding
(Prentice Hall, 1995) ISBN 0-13-097080-8
Benedetto, J., Frazier, M., Wavelets: Mathematics And Applica-
tions (CRC Press, 1994) ISBN 0-8493-8271-8
Grossman, A., Morlet, J., Decomposition of Hardy Functions into
Square Integrable Wavelets of Constant Shape, Siam. J. Math.
ADV601
THE WAVELET KERNELThis block contains a set of filters and decimators that work on
the image in both horizontal and vertical directions. Figure 6
illustrates the filter tree structure. The filters apply carefully
chosen wavelet basis functions that better correlate to the broad-
band nature of images than the sinusoidal waves used in Dis-
crete Cosine Transform (DCT) compression schemes (JPEG,
MPEG, and H261).
An advantage of wavelet-based compression is that the entire
image can be filtered without being broken into sub-blocks as
required in DCT compression schemes. This full image filtering
eliminates the block artifacts seen in DCT compression and
offers more graceful image degradation at high compression
ratios. The availability of full image sub-band data also makes
image processing, scaling, and a number of other system fea-
tures possible with little or no computational overhead.
The resultant filtered image is made up of components of the
original image as is shown in Figure 3 (a modified Mallat Tree).
Note that Figure 3 shows how a component of video would be
filtered, but in multiple component video luminance and color
components are filtered separately. In Figure 4 and Figure 5 an
actual image and the Mallat Tree (luminance only) equivalent is
shown. It is important to note that while the image has been
filtered or transformed into the frequency domain, no compres-
sion has occurred. With the image in its filtered state, it is now
ready for processing in the second block, the quantizer.
BLOCK A IS HIGH PASS IN X AND DECIMATED BY TWO.
BLOCK B IS HIGH PASS IN X, HIGH PASS IN Y, AND DECIMATED BY EIGHT.
BLOCK C IS HIGH PASS IN X, LOW PASS IN Y, AND DECIMATED BY EIGHT.
BLOCK D IS LOW PASS IN X, HIGH PASS IN Y, AND DECIMATED BY EIGHT.
BLOCK E IS HIGH PASS IN X, HIGH PASS IN Y, AND DECIMATED BY 32.
BLOCK F IS HIGH PASS IN X, LOW PASS IN Y, AND DECIMATED BY 32.
BLOCK G IS LOW PASS IN X, HIGH PASS IN Y, AND DECIMATED BY 32.
BLOCK H IS HIGH PASS IN X, HIGH PASS IN Y, AND DECIMATED BY 128.
BLOCK I IS HIGH PASS IN X, LOW PASS IN Y, AND DECIMATED BY 128.
BLOCK J IS LOW PASS IN X, HIGH PASS IN Y, AND DECIMATED BY 128.
BLOCK K IS HIGH PASS IN X, HIGH PASS IN Y, AND DECIMATED BY 512.
BLOCK L IS HIGH PASS IN X, LOW PASS IN Y, AND DECIMATED BY 512.
BLOCK M IS LOW PASS IN X, HIGH PASS IN Y, AND DECIMATED BY 512.
BLOCK N IS LOW PASS IN X, LOW PASS IN Y, AND DECIMATED BY 512.Figure 3.Modified Mallat Diagram (Block Letters Correspond to Those in Filter Tree)
Understanding the structure and function of the wavelet filters
and resultant product is the key to obtaining the highest perfor-
mance from the ADV601. Consider the following points:The data in all blocks (except N) for all components are high
pass filtered. Therefore, the mean pixel value in those blocks
is typically zero and a histogram of the pixel values in these
blocks will contain a single “hump” (Laplacian distribution).The data in most blocks is more likely to contain zeros or
strings of zeros than unfiltered image data.The human visual system is less sensitive to higher frequency
blocks than low ones.Attenuation of the selected blocks in luminance or color com-
ponents results in control over sharpness, brightness, contrast
and saturation.High quality filtered/decimated images can be extracted/created
without computational overhead.
Through leverage of these key points, the ADV601 not only
compresses video, but offers a host of application features. Please
see the Applying the ADV601 section for details on getting the
most out of the ADV601’s sub-band coding architecture in
different applications.
Figure 4.Unfiltered Original Image (Analog Devices Corporate Offices, Norwood, Massachusetts)
ADV601
STAGE 1INDICATES DECIMATE BY TWO IN X
INDICATES DECIMATE BY TWO IN Y
INDICATES
CORRESPONDING BLOCK
LETTER ON MALLAT
DIAGRAMY2AYBCDYYX2Y
STAGE 2
STAGE 3
STAGE 4
STAGE 5Figure 6.Wavelet Filter Tree Structure
THE PROGRAMMABLE QUANTIZERThis block quantizes the filtered image based on the response
profile of the human visual system. In general, the human eye
cannot resolve high frequencies in images to the same level of
accuracy as lower frequencies. Through intelligent “quantiza-
tion” of information contained within the filtered image, the
ADV601 achieves compression without compromising the visual
quality of the image. Figure 7 shows the encode and decode
data formats used by the quantizer.
Figure 8 shows how a typical quantization pattern applies over
Mallat block data. The high frequency blocks receive much larger
quantization (appear darker) than the low frequency blocks (appear
lighter). Looking at this figure, one sees some key point concerning
quantization: (1) quantization relates directly to frequency in
Mallat block data and (2) levels of quantization range widely from
high to low frequency block. (Note that the fill is based on a log
formula.) The relation between actual ADV601 bin width factors
and the Mallat block fill pattern in Figure 8 appears in Table II.
WAVELET
DATA
15.0 BIN
NUMBER
QUANTIZER - ENCODE MODE
QUANTIZER - DECODE MODE
WAVELET DATA9.7
WAVELET
DATA
15.0 BIN
NUMBERFigure 7.Programmable Quantizer Data Flow
Y COMPONENT
Cb COMPONENT
Cr COMPONENT
LOWHIGH
QUANTIZATION OF MALLAT BLOCKS
ADV601
Table II.ADV601 Typical Quantization of Mallat Data Block
Data1NOTEThe Mallat block numbers, Bin Width factors, and Reciprocal Bin Width
factors in Table II correspond to the shading per-cent fill) of Mallat blocks in
Figure 8.
THE RUN LENGTH CODER AND HUFFMAN CODERThis block contains two types of entropy coders that achieve
mathematically loss-less compression: run-length and Huffman.
The run-length coder looks for long strings of zeros and replaces
it with short hand symbols. Table III illustrates an example of
how compression is possible.
The Huffman coder is a digital compressor/decompressor that
can be used for compressing any type of digital data. Essentially,
an ideal Huffman coder creates a table of the most commonly
occurring code sequences (typically zero and small values near
zero) and then replaces those codes with some shorthand. The
ADV601 employs three fixed Huffman tables; it does not create
tables.
The filters and the quantizer increase the number of zeros and
strings of zeros, which improves the performance of the entropy
coders. The higher the selected compression ratio, the more
zeros and small value sequences the quantizer needs to generate.
The transformed image in Figure 5 shows that the filter bank
concentrates zeros and small values in the higher frequency
blocks.
Encoding vs. DecodingThe decoding of compressed video follows the exact path as
encoding but in reverse order. There is no need to calculate Bin
Widths during decode because the Bin Width is stored in the
compressed image during encode.
PROGRAMMER’S MODELA host device configures the ADV601 using the Host I/O Port.
The host reads from status registers and writes to control regis-
ters through the Host I/O Port.
An optional DSP can perform Bin Width calculations for the
ADV601. The ADV601 can transfer data from component
video statistics registers and receive data for Bin Width registers
as a packet I/O using the DSP I/O Port. Table IV illustrates the
format used to describe the ADV601’s read and write registers.
Table IV.Register Description Conventions
Register NameRegister Type (Indirect or Direct, Read or Write) and Address
Register Functional Description Text
Bit [#] orBit or Bit Field Name and Usage Description
Bit Range
[High:Low]Action or Indication When Bit Is Cleared (Equals 0)Action or Indication When Bit Is Set (Equals 1)
Table III.Uncompressed Versus Compressed Data Using Run-Length Coding0000000000000000000000000000000000000000000000000000000000000000000(uncompressed)
57 Zeros (Compressed)
0x10x880x7 – 0x7FUNDEF
0x00x0983
0x20x000
0x30x3FF
0x40x000
0x50x3FF
0x6UNDEF
0x100UNDEF
0x101UNDEF
0x152UNDEF
0x153UNDEF
0x80 – 0xA9UNDEF
0xABUNDEF
0xACUNDEF
0xADUNDEF
0xAEUNDEF
0xAAUNDEF
0xB2UNDEF
0xB1UNDEF
0xB0UNDEF
0xAFUNDEF
0xB3 – 0xFFUNDEF
0x0
0x4
0x8
0xC
BYTE 3BYTE 2BYTE 1
0x00
UNDEF
0x00
0x00
REGISTER
ADDRESS
DIRECT (EXTERNALLY ACCESSIBLE) REGISTERS
INDIRECT (INTERNALLY INDEXED) REGISTERS
{ACCESS THESE REGISTERS THROUGH THE
INDIRECT REGISTER ADDRESS AND
INDIRECT REGISTER DATA REGISTERS}
BYTE 0
RESET
VALUEFigure 9.Map of ADV601 Direct and Indirect Registers
ADV601
ADV601 REGISTER DESCRIPTIONS
Indirect Address RegisterDirect (Write) Register Byte Offset 0x00.
This register holds a 16-bit value (index) that selects the indirect register accessible to the host through the indirect data register. All
indirect write registers are 16-bits wide. The address in this register is auto-incremented on each subsequent access of the indirect
data register. This capability enhances I/O performance during modes of operation where the host is calculating Bin Width controls.
In 8-bit mode, auto-increment occurs after writing to Byte 1 (BE1 pin asserted) of the Indirect Data Register; always read or write
Byte 0 then Byte 1 when in 8-bit mode.
[15:0]Indirect Address Register, IAR[15:0]. Holds a 16-bit value (index) that selects the indirect register to read or write through
the indirect data register (undefined at reset)
[31:16]Reserved (undefined read/write zero)
Indirect Register DataDirect (Read/Write) Register Byte Offset 0x04
This register holds a 16-bit value read or written from or to the indirect register indexed by the Indirect Address Register. In 8-bit
mode, Byte 0 is read or written first followed by Byte 1. This ensures correct operation of auto-increment.
[15:0]Indirect Register Data, IRD[15:0]. A 16-bit value read or written to the indexed indirect register. Undefined at reset.
[31:16]Reserved (undefined read/write zero)
Compressed Data RegisterDirect (Read/Write) Register Byte Offset 0x08
This register holds a 32-bit sequence from the compressed video bit stream. This register is buffered by a 512 position, 32-bit FIFO.
Access bytes in the following order for correct auto-increment: Byte 0, Byte 1, Byte 2, then Byte 3. For Word (16-bit) accesses, ac-
cess Word0 (Byte 0 and Byte 1) then Word1 (Byte 2 and Byte 3). For a description of the data sequence, see the Compressed
Data Stream Definition section.
[31:0]Compressed Data Register, CDR[31:0]. 32-bit value containing compressed video stream data. At reset, contents undefined.
Interrupt Mask / Status RegisterDirect (Read/Write) Register Byte Offset 0x0C
This 16-bit register contains interrupt mask and status bits that control the state of the ADV601’s HIRQ pin. With the seven mask
bits (IE_LCODE, IE_STATSR, IE_FIFOSTP, IE_FIFOSRQ, IE_FIFOERR, IE_CCIRER, IE_MERR); select the conditions that
are ORed together to determine the output of the HIRQ pin.
Six of the status bits (LCODE, STATSR, FIFOSTP, MERR, FIFOERR, CCIRER) indicate active interrupt conditions and are
sticky bits that stay set until read. Because sticky status bits are cleared when read, and these bits are set on the positive edge of the
condition coming true, they cannot be read or tested for stable level true conditions multiple times.
The FIFOSRQ bit is not sticky. This bit can be polled to monitor for a FIFOSRQ true condition. Note: Enable this monitoring by
using the FIFOSRQ bit and correctly programming DSL and ESL fields within the FIFO control registers.
[0]CCIR-656 Error in CCIR-656 data stream, CCIRER. This read only status bit indicates the following:No CCIR-656 Error condition, reset valueUnrecoverable error in CCIR-656 data stream (missing sync codes)
[1]Statistics Ready, STATSR. This read only status bit indicates the following:No Statistics Ready condition, reset value (STATS_R pin LO)Statistics Ready for BW calculator (STATS_R pin HI)
[2]Last Code Read, LCODE. This read only status bit indicates the last compressed data word for field will be
retrieved from the FIFO on the next read from the host bus.No Last Code condition, reset value (LCODE pin LO)Next read retrieves last word for field in FIFO (LCODE pin HI)
[3]FIFO Service Request, FIFOSRQ. This read only status bit indicates the following:No FIFO Service Request condition, reset value (FIFO_SRQ pin LO)FIFO is nearly full (encode) or nearly empty (decode) (FIFO_SRQ pin HI)
[4]FIFO Error, FIFOERR. This condition indicates that the host has been unable to keep up with the ADV601’s compressed
data supply or demand requirements. If this condition occurs during encode, the data stream will not be corrupted until
MERR indicates that the DRAM is also overflowed. If this condition occurs during decode, the video output will be
corrupted. If the system overflows the FIFO (disregarding a FIFOSTP condition) with too many writes in decode mode,
FIFOERR is asserted. This read only status bit indicates the following:No FIFO Error condition, reset value (FIFO_ERR pin LO)FIFO overflow (encode) or underflow (decode) (FIFO_ERR pin HI)
[5]FIFO Stop, FIFOSTP. This condition indicates that the FIFO is full in decode mode and empty in encode mode.
In decode mode only, FIFOSTP status actually behaves more conservatively than this. In decode mode, even when
FIFOSTP is indicated, there are still 32 empty Dwords available in the FIFO and 32 more Dword writes can safely
be performed. This status bit indicates the following:No FIFO Stop condition, reset value (FIFO_STP pin LO)FIFO empty (encode) or full (decode) (FIFO_STP pin HI)
[6]Memory Error, MERR. This condition indicates that an error has occurred at the DRAM memory interface. This condition can
be caused by a defective DRAM, the inability of the Host to keep up with the ADV601 compressed data stream, or bit errors in
the data stream. Note that the ADV601 recovers from this condition without host intervention.No memory error condition, reset valueMemory error
[7]Reserved (always read/write zero)
[8]Interrupt Enable on CCIRER, IE_CCIRER. This mask bit selects the following:Disable CCIR-656 data error interrupt, reset valueEnable interrupt on error in CCIR-656 data
[9]Interrupt Enable on STATR, IE_STATR. This mask bit selects the following:Disable Statistics Ready interrupt, reset valueEnable interrupt on Statistics Ready
[10]Interrupt Enable on LCODE, IE_LCODE. This mask bit selects the following:Disable Last Code Read interrupt, reset valueEnable interrupt on Last Code Read from FIFO
[11]Interrupt Enable on FIFOSRQ, IE_FIFOSRQ. This mask bit selects the following:Disable FIFO Service Request interrupt, reset valueEnable interrupt on FIFO Service Request
[12]Interrupt Enable on FIFOERR, IE_FIFOERR. This mask bit selects the following:Disable FIFO Stop interrupt, reset valueEnable interrupt on FIFO Stop
[13]Interrupt Enable on FIFOSTP, IE_FIFOSTP. This mask bit selects the following:Disable FIFO Error interrupt, reset valueEnable interrupt on FIFO Error
[14]Interrupt Enable on MERR, IE_MERR. This mask bit selects the following:Disable memory error interrupt, reset valueEnable interrupt on memory error
[15]Reserved (always read/write zero)
Mode Control RegisterIndirect (Write Only) Register Index 0x00
This register holds configuration data for the ADV601’s video interface format and controls several other video interface features.
For more information on formats and modes, see the Video Interface section. Bits in this register have the following functions:
[3:0]Video Interface Format, VIF[3:0]. These bits select the interface format. Valid settings include the following (all
other values are reserved):
0x0CCIR-656
0x2MLTPX (Philips)
0x3Philips, reset value
ADV601[5]Video Interface Master/Slave Mode Select, M/S. This bit selects the following:Slave mode video interface (External control of video timing, HSYNC-VSYNC-FIELD are inputs), reset valueMaster mode video interface (ADV601 controls video timing, HSYNC-VSYNC are outputs)
[6]Video Interface 525/625 (NTSC/PAL) Mode Select, P/N. This bit selects the following:525 mode video interface, reset value625 mode video interface
[7]Video Interface Encode/Decode Mode Select, E/D. This bit selects the following:Decode mode video interface (compressed-to-raw)Encode mode video interface (raw-to-compressed), reset value
[8]Video Interface Square Pixel Mode Enable, SPE. This bit selects the following:Disable Square Pixel mode video interfaceEnable Square Pixel mode video interface, reset value
[9]Video Interface Bipolar/Unipolar Color Component Select, BUC. This bit selects the following:Bipolar color component mode video interface, reset valueUnipolar color component mode video interface
[10]External DSP Select for bin width calculations, DSP. This bit selects the following:Host provides bin width calculation, reset valueExternal DSP provides bin width calculation
[11]Video Interface Software Reset, SWR. This bit has the following effects on ADV601 operations:Normal operationSoftware Reset. This bit is set on hardware reset and must be cleared before the ADV601 can begin processing. (reset value)
When this bit is set during encode, the ADV601 completes processing the current field then suspends operation until the
SWR bit is cleared. When this bit is set during decode, the ADV601 suspends operation immediately and does not resume
operation until the SWR bit is cleared. Note that this bit must be set whenever any other bit in the Mode register is changed.
[12]HSYNC pin Polarity, PHSYNC. This bit has the following effects on ADV601 operations:HSYNC is HI during blanking, reset valueHSYNC is LO during blanking (HI during active)
[13]HIRQ pin Polarity, PHIRQ. This bit has the following effects on ADV601 operations:HIRQ is active LO, reset valueHIRQ is active HI
[15:14]Reserved (always write zero)
FIFO Control RegisterIndirect (Read/Write) Register Index 0x01
This register holds the service-request settings for the ADV601’s host interface FIFO, causing interrupts for the “nearly full” and
“nearly empty” levels. Because each register is four bits in size, and the FIFO is 512 positions, the 4-bit value must be multiplied by
32 (decimal) to determine the exact value for encode service level (nearly full) and decode service level (nearly empty). The ADV601
uses these setting to determine when to generate a FIFO Service Request related host interrupt (FIFOSRQ bit and FIFO_SRQ pin).
[3:0]Encode Service Level, ESL[3:0]. The value in this field determines when the FIFO is considered nearly full on encode; a condi-
tion that generates a FIFO service request condition in encode mode. Since this register is four bits (16 states), and the FIFO is
512 positions, the step size for each bit in this register is 32 positions. The following table summarizes sample states of the
register and their meaning.
ESLInterrupt When...
0000Disables service requests (FIFO_SRQ never goes HI during encode)
0001FIFO has only 32 positions filled (FIFO_SRQ when >= 32 positions are filled)
1000FIFO is 1/2 full, reset value
1111FIFO has only 32 positions empty (480 positions filled)
[7:4]Decode Service Level, DSL[7:4]. The value in this field determines when the FIFO is considered nearly empty in decode; a
condition that generates a FIFO service request in decode mode. Because this register is four bits (16 states), and the FIFO
is 512 positions, the step size for each bit in this register is 32 positions. The following table summarizes sample states of the
register and their meaning.
DSLInterrupt When...
0000Disables service requests (FIFO_SRQ never goes HI)
VIDEO AREA REGISTERSThe area defined by the HSTART, HEND, VSTART and VEND registers is the active area that the wavelet kernel processes. Video
data outside the active video area is set to minimum luminance and zero chrominance (black) by the ADV601. These registers allow
cropping of the input video during compression (encode only), but do not change the image size. Figure 10 shows how the video area
registers work together.
Figure 10.Video Area and Video Area Registers
HSTART RegisterIndirect (Write Only) Register Index 0x02
This register holds the setting for the horizontal start of the ADV601’s active video area. The value in this register is usually set to
zero, but in cases where you wish to crop incoming video it is possible to do so by changing HST.
[9:0]Horizontal Start, HST[9:0]. 10-bit value defining the start of the active video region. (0 at reset)
[15:10]Reserved (always write zero)
HEND RegisterIndirect (Write Only) Register Index 0x03
This register holds the setting for the horizontal end of the ADV601’s active video area. If the value is larger than the max size of the
selected video mode, the ADV601 uses the max size of the selected mode for HEND.
[9:0]Horizontal End, HEN[9:0].10-bit value defining the end of the active video region. (0x3FF at reset this value is larger than
the max size of the largest video mode)
[15:10]Reserved (always write zero)
VSTART RegisterIndirect (Write Only) Register Index 0x04
This register holds the setting for the vertical start of the ADV601’s active video area. The value in this register is usually set to zero
unless you want to crop the active video.
To vertically crop video while encoding, program the VSTART and VEND registers with actual video line numbers, which differ for
each field. The VSTART and VEND contents must be updated on each field. Perform this updating as part of the field-by-field BW regis-
ter update process. To perform this dynamic update correctly, the update software must keep track of which field is being processed next.
[9:0]Vertical Start, VST[9:0]. 10-bit value defining the starting line of the active video region, with line numbers from 1-to-625
in PAL and 1-to-525 in NTSC. (0 at reset)
[15:10]Reserved (always write zero)
VEND RegisterIndirect (Write Only) Register Index 0x05
This register holds the setting for the vertical end of the ADV601’s active video area. If the value is larger than the max size of the
selected video mode, the ADV601 uses the max size of the selected mode for VEND.
To vertically crop video while encoding, program the VSTART and VEND registers with actual video line numbers, which differ for
each field. The VSTART and VEND contents must be updated on each field. Perform this updating as part of the field-by-field BW
register update process. To perform this dynamic update correctly, the update software must keep track of which field is being pro-
ADV601
Compression Ratio RegisterIndirect (Write Only) Register Index 0x06
This register holds the value that is used by the DSP to control compression during encode mode. Note that this register should only
be used when a DSP is calculating Bin Widths.
[7:0]Compression Ratio, CRA[7:0]. Value passed to the DSP during encode operation. The 8-bit value in this field is sent to the
DSP through the serial interface during DSP-assisted encode operations. CRA values are zero-filled from the MSB and one
each is sent to the DSP as part of the packet of data on which the ratio is applied. The DSP software uses the CRA value
and other statistics to calculate BW controls for the ADV601’s quantizer. Note that the relationship between CRA and the
actual compression ratio is dependent on the BW control algorithm used in the DSP (undefined at reset).
[15:8]Reserved (always write zero)
Sum of Squares [0–41] RegistersIndirect (Read Only) Register Index 0x080 through 0x0A9
The Sum of Squares [0–41] registers hold values that correspond to the summation of values (squared) in corresponding Mallat
blocks [0–41]. These registers let the Host or DSP read sum of squares statistics from the ADV601; using these values (with the Sum
of Value, MIN Value, and MAX Value) the host or DSP can then calculate the BW and RBW values. The ADV601 indicates that
the sum of squares statistics have been updated by setting (1) the STATR bit and asserting the STAT_R pin. Read the statistics at
any time. The Host reads these values through the Host Interface or the DSP receives these values through the serial port.
[15:0]Sum of Squares, STS[15:0]. 16-bit values [0-41] for corresponding Mallat blocks [0-41] (undefined at reset). Sum of Square
values are 16-bit codes that represent the Most Significant Bits of values ranging from 40 bits for small blocks to 48 bits for
large blocks. The 16-bit codes have the following precision:
BlocksPrecisionSum of Squares Precision Description0–248.–3248.-bits wide, left shift code by 32-bits, and zero fill
3–1146.–3046.-bits wide, left shift code by 30-bits, and zero fill
12–2044.–2844.-bits wide, left shift code by 28-bits, and zero fill
21–2942.–2642.-bits wide, left shift code by 26-bits, and zero fill
30–4140.–2440.-bits wide, left shift code by 24-bits, and zero fill
If the Sum of Squares code were 0x0025 for block 10, the actual value would be 0x000940000000; if using that same
code, 0x0025, for block 30, the actual value would be 0x0025000000.
[31:0]Reserved (always read zero)
Sum of Luma Value RegisterIndirect (Read Only) Register Index 0x0AA
The Sum of Luma Value register lets the host or DSP read the sum of pixel values for the Luma component in block 39. The Host
reads these values through the Host Interface or the DSP receives these values through the serial port.
[15:0]Sum of Luma, SL[15:0]. 16-bit component pixel values (undefined at reset)
[31:0]Reserved (always read zero)
Sum of Cb Value RegisterIndirect (Read Only) Register Index 0x0AB
The Sum of Cb Value register lets the host or DSP read the sum of pixel values for the Cb component in block 40. The Host reads
these values through the Host Interface or the DSP receives these values through the serial port.
[15:0]Sum of Cb, SCB[15:0]. 16-bit component pixel values (undefined at reset)
[31:0]Reserved (always read zero)
Sum of Cr Value RegisterIndirect (Read Only) Register Index 0x0AC
The Sum of Cr Value register lets the host or DSP read the sum of pixel values for the Cr component in block 41. The Host reads
these values through the Host Interface or the DSP receives these values through the serial port.
[15:0]Sum of Cr, SCR[15:0]. 16-bit component pixel values (undefined at reset)
[31:0]Reserved (always read zero)
MIN Luma Value RegisterIndirect (Read Only) Register Index 0x0AD
The MIN Luma Value register lets the host or DSP read the minimum pixel value for the Luma component in the unprocessed
data. The Host reads these values through the Host Interface or the DSP receives these values through the serial port.
[15:0]Minimum Luma, MNL[15:0]. 16-bit component pixel value (undefined at reset)
[31:0]Reserved (always read zero)
MAX Luma Value RegisterIndirect (Read Only) Register Index 0x0AE
The MAX Luma Value register lets the host or DSP read the maximum pixel value for the Luma component in the unprocessed
data. The Host reads these values through the Host Interface or the DSP receives these values through the serial port.
[15:0]Maximum Luma, MXL[15:0]. 16-bit component pixel value (undefined at reset)
[31:0]Reserved (always read zero)
MIN Cb Value RegisterIndirect (Read Only) Register Index 0x0AF
The MIN Cb Value register lets the host or DSP read the minimum pixel value for the Cb component in the unprocessed data.
The Host reads these values through the Host Interface or the DSP receives these values through the serial port.
[15:0]Minimum Cb, MNCB[15:0], 16-bit component pixel value (undefined at reset)
[31:0]Reserved (always read zero)
MAX Cb Value RegisterIndirect (Read Only) Register Index 0x0B0
The MAX Cb Value register lets the host or DSP read the maximum pixel value for the Cb component in the unprocessed data.
The Host reads these values through the Host Interface or the DSP receives these values through the serial port.
[15:0]Maximum Cb, MXCB[15:0].16-bit component pixel value (undefined at reset)
[31:0]Reserved (always read zero)
MIN Cr Value RegisterIndirect (Read Only) Register Index 0x0B1
The MIN Cr Value register lets the host or DSP read the minimum pixel value for the Cr component in the unprocessed data.
The Host reads these values through the Host Interface or the DSP receives these values through the serial port.
[15:0]Minimum Cr, MNCR[15:0]. 16-bit component pixel value (undefined at reset)
[31:0]Reserved (always read zero)
MAX Cr Value RegisterIndirect (Read Only) Register Index 0x0B2
The MAX Cr Value register lets the host or DSP read the maximum pixel value for the Cr component in the unprocessed data.
The Host reads these values through the Host Interface or the DSP receives these values through the serial port.
[15:0]Maximum Cr, MXCR[15:0]. 16-bit component pixel value (undefined at reset)
[31:0]Reserved (always read zero)
Bin Width and Reciprocal Bin Width RegistersIndirect (Read/Write) Register Index 0x0100-0x0153
The RBW and BW values are calculated by the host or DSP from data in the Sum of Squares [0-41], Sum of Value, MIN Value, and
MAX Value registers; then are written to RBW and BW registers during encode mode to control the quantizer. The Host writes
these values through the Host Interface or the DSP transmits these values through the serial port.
These registers contain a 16-bit interleaved table of alternating RBW/BW (RBW-even addresses and BW-odd addresses) values
as indexed on writes by address register. Bin Widths are 8.8, unsigned, 16-bit, fixed-point values. Reciprocal Bin Widths are
6.10, unsigned, 16-bit, fixed-point values. Operation of this register is controlled by the host driver or the DSP (84 total entries)
ADV601
PIN FUNCTION DESCRIPTIONS
Clock Pins
Video Interface Pins
DRAM Interface Pins
Serial Port Pins and Timing
DSP Interface Pins
ADV601
DSP Interface Pins (Continued)
Host Interface PinsADR[1:0]
BE0–BE3
Host Interface Pins (Continued)
ADV601
Host Interface Pins (Continued)
Power Supply Pins
Video InterfaceThe ADV601 video interface supports a wide range of compo-
nent digital video (D1) interfaces in both compression (input)
and decompression (output) modes. These digital video inter-
faces include support for the following:Philips 4:2:2Multiplexed Philips 4:2:2CCIR-656/SMPTE125M - international standardClosed Captioning and VITC decode and encode
Video interface master and slave modes allow for the generation
or receiving of synchronization and blanking signals. Definitions
for the different formats can be found later in this section. For
recommended connections to popular video decoders and
encoders, see the Connecting The ADV601 To Popular Video
Decoders and Encoders section. A complete list of supported
video interfaces and sampling rates is included in Table V.
Table V.Component Digital Video InterfacesInternally, the video interface translates all video formats to one
consistent format to be passed to the wavelet kernel. This con-
sistent internal video standard is 4:2:2 at 16 bits accuracy.
VITC and Closed Captioning SupportThe video interface also supports the direct loss-less extraction
of 90-bit VITC codes during encode and the insertion of VITC
codes during decode. Closed Captioning data (found on active
Video Line 21) is handled just as normal active video on an
active scan line. As a result, no special dedicated support is
necessary for Closed Captioning. The data rates for Closed
Captioning data are low enough to ensure robust operation of
this mechanism at compression ratios of 50:1 and higher. Note
that you must include Video Line 21 in the ADV601’s defined
active video area for Closed Caption support.
27 MHz Nominal SamplingThere is one clock input (VCLK) to support all internal process-
ing elements. This is a 50% duty cycle signal and must be syn-
chronous to the video data. Internally this clock is doubled using
a phase locked loop to provide for a 54 MHz internal processing
clock. The clock interface is a two pin interface that allows a
crystal oscillator to be tied across the pins or a clock oscillator to
drive one pin. The nominal clock rate for the video interface is
27 MHz. Note that the ADV601 also supports pixel rates ranging
from 12.27 MHz to 14.75 MHz (VCLK rates from 24.54 MHz to
29.5 MHz).
Video Interface and ModesIn all, there are seven programmable features that configure the
video interface. These are:Encode-Decode Control
In addition to determining what functions the internal pro-
cessing elements must perform, this control determines the
direction of the video interface. In decode mode, the video
interface outputs data. In encode mode, the interface receives
data. The state of the control is reflected on the ENC pin.
This pin can be used as an enable input by external line driv-
ers. This control is maintained by the host processor.Master-Slave Control
This control determines whether the ADV601 generates or
receives the VSYNC, HSYNC, CREF, and FIELD signals. In
master mode, the ADV601 generates these signals for external
hardware synchronization. In slave mode, the ADV601 re-
ceives these signals. Note that some video formats require the
ADV601 to operate in slave mode only. This control is main-
tained by the host processor.525-625 (NTSC-PAL) Control
This control determines whether the ADV601 is operating on
525/NTSC video or 625/PAL video. This information is used
when the ADV601 is in master and decode modes so that the
ADV601 knows where and when to generate the HSYNC,
VSYNC, and FIELD Pulses as well as when to insert the SAV
and EAV time codes (for CCIR-656 only) in the data stream.
This control is maintained by the host processor. Table VI
shows how the 525-625 Control and Square Pixel Control in
the Mode Control register work together.
Table VI.Square Pixel Control, 525-625 Control, and
Video FormatsSquare Pixel Control
This control determines whether the ADV601 is operating on
square pixel video. For square pixel NTSC, the 525-625
Control is set to 525 and the Square Pixel Control is asserted.
For square pixel PAL, the 525-625 Control is set to 625 and
the Square Pixel Control is asserted. Also note that the VCLK
input differs for NTSC and PAL video.Bipolar/Unipolar Color Component
This mode determines whether offsets are used on color com-
ponents. In Philips mode, this control is usually set to Bipo-
lar, since the color components are normal twos-compliment
signed values. In CCIR-656 mode, this control is set to Uni-
polar, since the color components are offset by 128. Note that
it is likely the ADV601 will function if this control is in the
wrong state, but compression performance will be degraded.
It is important to set this bit correctly.
ADV601Active Area Control
Four registers HSTART (horizontal start), HEND (horizon-
tal end), VSTART (vertical start) and VEND (vertical end)
determine the active video area. The maximum active video
area is 768 by 288 pixels for a single field.Video Format
This control determines the video format that is supported. In
general, the goal of the various video formats is to support
glueless interfaces to the wide variety of video formats periph-
eral components expect. This control is maintained by the
host processor. Table VII shows a synopsis of the supported
video formats. Definitions of each format can be found later
in this section. For Video Interface pins descriptions, see the
Pin Function Descriptions.
Table VII.Component Digital Video Formats
Clocks and StrobesAll video data, whether 1 or 2 “lanes” of video are used, are
synchronous to the video clock (VCLK). The rising edge of
VCLK is used to clock all data into the ADV601.
Synchronization and Blanking PinsThree signals, which can be configured as inputs or outputs, are
used for video frame and field horizontal synchronization and
blanking. These signals are VSYNC, HSYNC, and FIELD.
VDATA Pins Functions With Differing Video Interface FormatsThe functionality of the Video Interface pins depends on the
current video format. Table VIII defines how Video data pins
are used for the various formats.
Table VIII.VDATA[0:19] Pin Functions Under CCIR-656, Multiplex Philips, Philips, and Gray Scale Video Interfaces1NOTEItalic font for an entry in this table indicates that the use of the pin is optional (i.e., bits per component greater than 8 ). Note that unused optional pins should be tied
through a resistor to ground. Also, N/C for an entry in this table indicates that the pin is never used for a particular video format. This nomenclature is consistent
with the Video Format Descriptions found later in this section. Note that Data0 is always the LSB for all formats.
Video Formats—CCIR-656The ADV601 supports a glueless video interface to CCIR-656
devices when the Video Format is programmed to CCIR-656
mode. CCIR-656 requires that 4:2:2 data (8 or 10 bits per com-
ponent) be multiplexed and transmitted over a single 8- or 10-bit
physical interface. A 27 MHz clock is transmitted along with the
data. This clock is synchronous with the data. The color space of
CCIR-656 is YCrCb.
When in master mode, the CCIR-656 mode does not require
any external synchronization or blanking signals to accompany
digital video. Instead, CCIR-656 includes special time codes in
the stream syntax that define horizontal blanking periods, verti-
cal blanking periods, and field synchronization (horizontal and
vertical synchronization information can be derived). These
time codes are called End-of-Active-Video (EAV) and Start-of-
Active-Video (SAV). Each line of video has one EAV and one
SAV time code. EAV and SAV have three bits of embedded
information to define HSYNC, VSYNC and Field information
as well as error detection and correction bits.
VCLK is driven with a 27 MHz, 50% duty cycle clock which is
synchronous with the video data. Video data is clocked on the
rising edge of the VCLK signal. When decoding, the VCLK
signal is typically transmitted along with video data in the
CCIR-656 physical interface.
Electrically, CCIR-656 specifies differential ECL levels to be
used for all interfaces. The ADV601, however, only supports
unipolar, TTL logic thresholds. Systems designs that interface
to strictly conforming CCIR-656 devices (especially when inter-
facing over long cable distances) must include ECL level shifters
and line drivers.
The functionality of HSYNC, VSYNC and FIELD Pins is
dependent on three programmable modes of the ADV601:
Master-Slave Control, Encode-Decode Control and 525-625
Control. Table IX summarizes the functionality of these pins in
various modes.
Table IX.CCIR-656 Master and Slave Modes HSYNC, VSYNC, and FIELD Functionality
Video Formats—Philips VideoPhilips video format requires 4:2:2 data (8 bits per component)
be transmitted over a two “lane” 16-bit physical interface. A
27 MHz clock is transmitted along with the data. This clock is
synchronous with the data and is running at twice the transfer
rate of the interface. The color space is YUV. VCLK is driven
with a 27 MHz 50% duty cycle clock, which is synchronous with
the video data. Philips video format requires external synchroni-
zation and blanking signals to accompany digital video. These
signals are VSYNC, HSYNC, CREF and FIELD. In general,
when the ADV601 is configured as an encoder, these signals will
all be inputs. When the ADV601 is configured as a decoder,
these signals will be outputs. There are special cases for this
described in Table X.
The functionality of HSYNC, VSYNC, and FIELD pins is depen-
dent on three programmable modes of the ADV601: Master-Slave
Control, Encode-Decode Control, and 525-625 Control. Table X
summarizes the functionality of these pins in various modes.
Table X.Philips Video Master and Slave Modes HSYNC, VSYNC and FIELD Functionality
ADV601
Video Formats — Multiplexed Philips VideoThe ADV601 supports a hybrid mode of operation that is a cross
between standard dual lane Philips and single lane CCIR-656. In
this mode, video data is multiplexed in the same fashion in CCIR-656,
but the values 0 and 255 are not reserved as signaling values. In-
stead, external HSYNC and VSYNC pins are used for signaling
and video synchronization. VCLK may range up to 29.5 MHz.
VCLK is driven with up to a 29.5 MHz 50% duty cycle clock
synchronous with the video data. Video data is clocked on the
rising edge of the VCLK signal. The functionality of HSYNC,
VSYNC, and FIELD pins is dependent on three programmable
modes of the ADV601: Master-Slave Control, Encode-Decode
Control, and 525-625 Control. Table XI summarizes the func-
tionality of these pins in various modes.
Table XI.Philips Multiplexed Video Master and Slave Modes HSYNC, VSYNC, and FIELD Functionality
Video Formats — Gray Scale VideoThe Gray Scale video format requires 4:0:0 data (up to 12 bits)
be transmitted over a one “lane” 8- to 12-bit physical interface.
A video clock (typically 27 MHz) is transmitted along with the
data. This clock is synchronous with the data and runs at twice
the transfer rate of the interface. The color space is Gray Scale.
Because the ADV601 internal processing is not dependent on
color space, Gray Scale data is processed in the same manner as
data in other color spaces.
VCLK is driven with a 24.54 MHz–29.5 MHz, 50% duty cycle
clock which is synchronous with the video data. Video data is
clocked on the second rising edge of the VCLK signal.
These video formats require external synchronization and
blanking signals to accompany digital video. These signals are
VSYNC, HSYNC, and FIELD. In general, when the ADV601
is configured as an encoder, these signals will all be inputs.
When the ADV601 is configured as a decoder, these signals will
be outputs. There are special cases for this format described in
Table XII.
Table XII.Gray Scale Video Master and Slave Modes HSYNC, VSYNC and FIELD Functionality
Video Formats—ReferencesFor more information on video interface standards, see the
following reference texts.For the definition of CCIR-601:
1992 – CCIR Recommendations RBT series Broadcasting Service
(Television) Rec. 601-3 Encoding Parameters of digital television
for studios, page 35, September 15, 1992.For the definition of CCIR-656:
1992 – CCIR Recommendations RBT series Broadcasting Service
(Television) Rec. 656-1 Interfaces for digital component video
signals in 525 and 626 line television systems operating at the
4:2:2 level of Rec. 601, page 46, September 15, 1992.
Host InterfaceThe ADV601 host interface is a high performance interface that
passes all command and real-time compressed video data be-
tween the host and codec. A 512 position by 32-bit wide, bidi-
rectional FIFO buffer passes compressed video data to and from
the host. The host interface is capable of burst transfer rates of
up to 132 million bytes per second (4 × 33 MHz). For host inter-
face pins descriptions, see the Pin Function Descriptions section.
For host interface timing information, see the Host Interface Timing
section.
DSP InterfaceThe DSP Interface is used to interface with an external DSP.
During encode, the DSP provides the ADV601 with Bin Width
calculation support (in applications where the host processor is
not providing Bin Width support). When the host provides Bin
Width calculation support, the DSP is not required. During
decode, the DSP is not needed. This interface is capable of
glueless connection with all of Analog Devices DSP serial ports.
The DSP interface passes the following information (in encode
only):Wavelet statistics calculated by the ADV601 output to the DSPCompression ratio output to the DSPQuantizer control information (i.e., Bin Width and Reciprocal
Bin Width factors) input from the DSP
Figure 11 shows how to connect and ADV601 with a DSP.
Other figures that describe ADV601-to-DSP connections in-
clude Figures 15 and 16.
Figure 11.ADV601-to-ADSP-2105 (DSP) Serial Interface
Connections
ADV601 Serial Transfer OverviewThe video statistics that the ADV601 calculates and sends to the
DSP for quantizer control calculations are as follows:Minimum pixel value per field per componentMaximum pixel value per field per componentSum of pixel values per field per componentSum of squares of pixel values per Mallat block per componentCompression Ratio (programmed by the host) per field
The ADV601 video codec can transmit video field statistics and
receive bin width values through its serial port when connected
to a DSP (an ADSP-21xx family DSP whose SPORT is set for
continuous Rx/Tx normal framing mode). This DSP-compatible
serial port has six pins: RXD, TXD, TCLK, TF, RF and DIRQ.
For DSP Interface pins descriptions, see Pin Function Descriptions.
ADV601 Serial Transfer ProcessOn a field by field basis, the ADV601 transfers video statistics to
the DSP and then receives bin widths from the DSP. The tim-
ing of the data flow appears in Figure 41. The steps for the data
flow are as follows:The ADV601 asserts DIRQ to alert the DSP that video sta-
tistics are ready for the first field.The ADV601 transfers the statistics packet of fifty-two 16-bit
words on the TXD pin using a pulse on TF to indicate the
beginning, most-significant-bit first, of each word.
The video statistics transfer for the first field occurs during
the first part of the next field. The address order of register
transfer is as follows: 0x06 (Compression Ratio), 0x80-0xA9
(Sum of Squares [0-41]), 0xAA (Sum of Luma), 0xAB (Sum
of Cb), 0xAC (Sum of Cr), 0xAD (Min Luma), 0xAE (Max
Luma), 0xAF (Min Cb), 0xB0 (Max Cb), 0xB1 (Min Cr),
and 0xB2 (Max Cr).The DSP calculates bin width and reciprocal bin width val-
ues for each Mallat block, using the video statistics.The DSP transfers the bin width and reciprocal bin width
packet of eighty-four 16-bit words on the ADV601’s RXD
pin using a pulse on the ADV601’s RF to indicate the begin-
ning, most-significant-bit first, of each word.
The bin width and reciprocal bin width transfer for the first
field occurs before the end of the next field. The address
order of register transfer is as follows: 0x100 (Reciprocal Bin
Width 0), 0x101 (Bin Width 0), ..., 0x152 (Reciprocal Bin
Width 41), 0x153 (Bin Width 41).The ADV601 de-asserts DIRQ after receiving the DSP’s bin
width and reciprocal bin width packet and keeps DIRQ de-
asserted until the video statistics packet for the next field is
ready for transfer.
ADV601 Serial Transfer ImplicationsThis serial I/O process between the ADV601 and the DSP con-
tinues for all fields of video. Some important implications that
stem from this process are as follows:Because the ADV601 asserts DIRQ near the beginning of
each video field, the signal can be useful for synchronizing
system wide operations that need to key on the beginning of
each video field.Because failures in serial I/O to the DSP are possible, the
DSP software times out if the video statistics packet does not
arrive within a specific time window and returns a default set
of bin width values to the ADV601.Because failures in serial I/O from the DSP are possible, the
ADV601 uses the bin width values from the previous field if
the DSP does not return new bin with values within a specific
time window.
ADV601
DRAM ManagerThe DRAM Manager provides a sorting and reordering func-
tion on the sub-band coded data between the Wavelet Kernel
and the Programmable Quantizer. The DRAM manager pro-
vides a pipeline delay stage to the ADV601. This pipeline lets
the ADV601 extract current field image statistics (min/max
pixel values, sum of pixel values, and sum of squares) used in
the calculation of Bin Widths and re-order wavelet transform
data. The use of current field statistics in the Bin Width calcula-
tion results in precise control over the compressed bit rate. The
DRAM manager manages the entire operation and refresh of the
DRAM.
The interface between the ADV601 DRAM manager and
DRAM is designed to be transparent to the user. The ADV601
DRAM pins should be connected to the DRAM as called out in
the Pin Function Descriptions section. The ADV601 requires
one 256K word by 16-bit, 60 ns DRAM. The following is a
selected list of manufacturers and part numbers. All parts can
be used with the ADV601 at all VCLK rates except where
noted. Any DRAM used with the ADV601 must meet the mini-
mum specifications outlined for the Hyper Mode DRAMs listed
in Table XIII. For DRAM Interface pins descriptions, see the
Pin Function Descriptions.
Table XIII.ADV601 Compatible DRAMs
Compressed Data-Stream DefinitionThrough its Host Interface the ADV601 outputs (during en-
code) and receives (during decode) compressed digital video
data. This stream of data passing between the ADV601 and the
host is hierarchically structured and broken up into blocks of
data as shown in Figure 12. Table IV shows pseudo code for a
video data transfer that matches the transfer order shown in
Figure 12 and uses the code names shown in Table XVI. The
blocks of data listed in Figure 12 correspond to wavelet com-
pressed sections of each field illustrated in Figure 13 as a modified
Mallat diagram.
Figure 12.Hierarchical Structure of Wavelet Compressed Frame Data (Data Block Order)
