ADV476KP35 ,CMOS Monolithic 256x18 Color Palette RAM-DACCHARACTERISTICS (V = +5 V 6 10%. All
ADV476KP50 ,CMOS Monolithic 256x18 Color Palette RAM-DACSpecifications T to T unless otherwise noted.)MIN MAXParameter All Versions Units Test Conditions/C ..
ADV476KP66 ,CMOS Monolithic 256x18 Color Palette RAM-DACFEATURESFUNCTIONAL BLOCK DIAGRAMPersonal System/2* and VGA* CompatiblePlug-in Replacement for INMOS ..
ADV478KP35 ,CMOS 80 MHz Monolithic 256 x 24(18) Color Palette RAM-DACsSpecifications u, to Tm2 unless otherwise noted.)
r-
Parameter All Versions Units Test Coriditi ..
ADV478KP50 ,CMOS 80 MHz Monolithic 256 x 24(18) Color Palette RAM-DACsGENERAL DESCRIPTION
The ADV478 (ADV@) and ADV471 are pin compatible and
software compatible RAM ..
ADV478KP66 ,CMOS 80 MHz Monolithic 256 x 24(18) Color Palette RAM-DACsSpecifications u, to Tm2 unless otherwise noted.)
r-
Parameter All Versions Units Test Coriditi ..
AM27C256-150DC , 256 Kilobit (32 K x 8-Bit) CMOS EPRO
AM27C256-150DE , 256 Kilobit (32 K x 8-Bit) CMOS EPRO
AM27C256-150DIB , 256 Kilobit (32 K x 8-Bit) CMOS EPRO
AM27C256-150JI , 256 Kilobit (32,768 x 8-Bit) CMOS EPROM
AM27C256-150JI , 256 Kilobit (32,768 x 8-Bit) CMOS EPROM
AM27C256-150PC , 256 Kilobit (32,768 x 8-Bit) CMOS EPROM
ADV476-ADV476KN35-ADV476KN50-ADV476KN66-ADV476KP35-ADV476KP50-ADV476KP66
CMOS Monolithic 256x18 Color Palette RAM-DAC
REV.B
CMOS Monolithic 256318
Color Palette RAM-DAC
FUNCTIONAL BLOCK DIAGRAMFEATURES
Personal System/2* and VGA* Compatible
Plug-in Replacement for INMOS 171/176
66 MHz Pipelined Operation
Three 6-Bit D/A Converters
256318 Color Palette RAM
RS-343A/RS-170 Compatible Outputs
Blank on All Three Channels
Standard MPU Interface
Asynchronous Access to All Internal Registers15 V CMOS Monolithic Construction
Low Power Dissipation
Standard 28-Pin, 0.6" DIP and 44-Pin PLCC
APPLICATIONS
High Resolution Color Graphics
CAE/CAD/CAM Applications
Image Processing
Instrumentation
Desktop Publishing
AVAILABLE CLOCK RATES
66 MHz
50 MHz
35 MHz
GENERAL DESCRIPTIONThe ADV476 (ADV®) is a pin compatible and software compat-
ible RAM-DAC designed specifically for VGA and Personal
System/2 color graphics.
The ADV476 is a complete analog output RAM-DAC on a
single monolithic chip. The part contains a 256318 color
lookup table, a pixel mask register as well as a triple 6-bit video
D/A converter. The ADV476 is capable of simultaneously dis-
playing up to 256 colors, from a total color palette of 262,144
addressable colors.
The on-chip asynchronous MPU bus allows access to the color
lookup table without affecting the input video data via the pixel
port. The pixel read mask register provides a convenient way of
altering the displayed colors without updating the color lookup
table. The ADV476 is capable of generating RGB video output
signals which are compatible with RS-343A and RS-170 video
standards, without requiring external buffering.
The ADV476 is fabricated in a +5 V CMOS process. Its mono-
lithic CMOS construction ensures greater functionality with low
power dissipation and small board area. The part is packaged in
a 0.6", 28-pin DIP and a 44-pin PLCC.
PRODUCT HIGHLIGHTSStandard video refresh rates, 35 MHz, 50 MHz and
66 MHz.Fully compatible with VGA and Personal System/2 color
graphics.Guaranteed monotonic. Integral and differential linearity
guaranteed to be a maximum of ±1 LSB.Low glitch energy, 75 pV secs.
*Personal System/2 and VGA are trademarks of International Business
Machines Corp.
ADV is a registered trademark of Analog Devices, Inc.
ADV476–SPECIFICATIONS
(VCC = +5 V 6 10%, IREF = 8.88 mA.
All Specifications TMIN to TMAX1 unless otherwise noted.)NOTESTemperature range (TMIN to TMAX); 0 to +70°C.Relative to the midpoint of the distribution of the three DACs measured at full scale.TTL input values are 0 to 3 volts, with input rise/fall times ≤3 ns, measured between the 10% and 90% points. Timing reference points at 50% for inputs and out-
puts. Analog output load ≤10 pF, 37.5 Ω. D0–D7 output load ≤50 pF. See timing notes in Figure 2.Clock and data feedthrough is a function of the amount of overshoot and undershoot on the digital inputs. For this test, the digital inputs have a 1 kΩ resistor to
ground and are driven by 74HC logic. Glitch impulse includes clock and data feedthrough, –3 dB test bandwidth = 2 3 clock rate.
Specifications subject to change without notice.
TIMING CHARACTERISTICS1NOTESTTL input values are 0 to 3 volts, with input rise/fall times ≤3 ns, measured between the 10% and 90% points. Timing reference points at 50% for inputs and
outputs. Analog output load ≤10 pF, 37.5 Ω. D0–D7 output load ≤50 pF. See timing notes in Figure 2.Temperature Range (TMIN to TMAX); 0 to +70°CSettling time does not include clock and data feedthrough. For this test, the digital inputs have a 1 kΩ resistor to ground and are driven by 74HC logic.
Specifications subject to change without notice.
Figure 1.MPU Read/Write Timing
(VCC = +5 V 6 10%. All Specifications TMIN to TMAX2)
ADV476
ABSOLUTE MAXIMUM RATINGS1VCC to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+7 V
Voltage on any Digital Pin . . . . .GND – 0.5 V to VCC + 0.5 V
Ambient Operating Temperature (TA) . . . . .–55°C to +125°C
Storage Temperature (TS) . . . . . . . . . . . . . .–65°C to +150°C
Junction Temperature (TJ) . . . . . . . . . . . . . . . . . . . .+150°C
Lead Temperature (Soldering, 10 secs) . . . . . . . . . . .+300°C
Vapor Phase Soldering (1 minute) . . . . . . . . . . . . . . .+220°C
Red, Green, Blue to GND2 . . . . . . . . . . . . . . . . . .0 V to VCC
NOTESStresses above those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those listed in the
operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.Analog output short circuit to any power supply or common can be of an indefinite
duration.
ORDERING GUIDE1, 2NOTESAll devices are specified for 0°C to +70°C operation.Devices are packaged in 0.6" 28-pin plastic DIPs (N-28), and 44-pin J-leaded
PLCC (P-44A).N = Plastic DIP; P = Plastic Leaded Chip Carrier.
RECOMMENDED OPERATING CONDITIONS
WARNING!
ESD SENSITIVE DEVICE
CAUTIONESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the ADV476 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
PIN CONFIGURATIONSPLCCDIPThe above pins allow the ADV476KP (44-Pin PLCC) to be al-
ternatively driven by a voltage reference. If it is desired to use a
voltage reference configuration instead of the current reference
PIN FUNCTION DESCRIPTION
TERMINOLOGY
Blanking LevelThe level separating the SYNC portion from the Video portion
of the waveform. Usually referred to as the Front Porch or Back
Porch. At 0 IRE Units, it is the level which will shut off the pic-
ture tube, resulting in the blackest possible picture.
Color Video (RGB)This usually refers to the technique of combining the three pri-
mary colors of Red, Green and Blue to produce color pictures
within the usual spectrum. In RGB monitors, three DACs are
required, one for each color.
Gray ScaleThe discrete levels of video signal between Reference Black and
Reference White levels. An 8-bit DAC contains 256 different
levels while a 6-bit DAC contains 64.
Raster ScanThe most basic method of sweeping a CRT one line at a time to
generate and display images.
Reference Black LevelThe maximum negative polarity amplitude of the video signal.
Reference White LevelThe maximum positive polarity amplitude of the video signal.
Video SignalThat portion of the composite video signal which varies in gray
scale levels between Reference White and Reference Black. Also
referred to as the picture signal, this is the portion which may be
visually observed.
ADV476
MPU InterfaceAs illustrated in the functional block diagram, the ADV476 sup-
ports a standard MPU bus interface, allowing the MPU direct
access to the color palette RAM.
The RS0 and RS1 control inputs specify whether the MPU is
accessing the address register or the color palette RAM, as
shown in Table I. The 8-bit address register is used to address
the color palette RAM, eliminating the requirement for external
address multiplexers.
Table I. Control Input Truth TableTo write color data, the MPU writes to the address register with
the 8-bit address of the color palette RAM location which is to
be modified. The MPU performs three successive write cycles
(six bits of red data, six bits of green data and six bits of blue
data). During the blue write cycle, the three bytes of color infor-
mation are concatenated into an 18-bit word and written to the
location specified by the address register. The address register
then automatically increments to the next location which the
MPU may modify by simply writing another sequence of red,
green and blue data.
To read back color data, the MPU loads the address register
with the address of the color palette RAM location to be read.
The MPU performs three successive read cycles (6 bits each of
red, green and blue data). Following the blue read cycle, the
address register increments to the next location which the MPU
may read by simply reading another sequence of red, green and
blue data.
This 6-bit color data is right justified, i.e., the lower six bits of
the data bus with D0 being the LSB and D5 the MSB. D6 and
D7 are ignored during a color write cycle and are set to zero
during a color read cycle.
During color palette RAM access, the address register resets to
00H following a blue read or write operation to RAM location
FFH.
The MPU interface operates asynchronously to the pixel clock.
Data transfers between the color palette RAM and the color
registers (R, G, and B in the block diagram) are synchronized by
internal logic, and occur in the period between MPU accesses.
Color (RGB) data is normally loaded to the color palette RAM
during video screen retrace, i.e., during the video waveform
blanking period, see Figure 5.
To keep track of the red, green and blue read/write cycles, the
address register has two additional bits (ADDRa, ADDRb) that
count modulo three, as shown in Table II. They are reset to
zero when the MPU writes to the address register, and are not
reset to zero when the MPU reads the address register. The
MPU does not have access to these bits. The other eight bits of
the address register, incremented following a blue read or write
cycle, (ADDR0–7) are accessible to the MPU, and are used to
address color palette RAM locations, as shown in Table III.
ADDR0 is the LSB when the MPU is accessing the RAM. The
MPU may read the address register at any time without modify-
ing its contents or the existing read/write mode.
Figure 1 illustrates the MPU read/write timing and Table III
shows the associated functional instructions.
Table II.Address Register (ADDR) Operation
Table III.Truth Table for Read/Write Operations
