ADV473KP80 ,CMOS 135 MHz True-Color Graphics Triple 8-Bit Video RAM-DACCHARACTERISTICSMIN MAX135 MHz 110 MHz 80 MHz 66 MHzParameter Version Version Version Version Units ..
ADV476 ,CMOS Monolithic 256x18 Color Palette RAM-DACAPPLICATIONSHigh Resolution Color GraphicsCAE/CAD/CAM
ADV476KN35 ,CMOS Monolithic 256x18 Color Palette RAM-DACCMOS Monolithic 256318aColor Palette RAM-DACADV476
ADV476KN50 ,CMOS Monolithic 256x18 Color Palette RAM-DACApplicationsImage ProcessingInstrumentationDesktop PublishingAVAILABLE CLOCK RATES66 MHz50 MHz35 MHz
ADV476KN50 ,CMOS Monolithic 256x18 Color Palette RAM-DACGENERAL DESCRIPTION The ADV476 is fabricated in a +5 V CMOS process. Its mono-®The ADV476 (ADV ) is ..
ADV476KN66 ,CMOS Monolithic 256x18 Color Palette RAM-DACSpecifications T to T )CC MIN MAXParameter 66 MHz Version 50 MHz Version 35 MHz Version Units Condi ..
AM27C256-120DC , 256 Kilobit (32 K x 8-Bit) CMOS EPRO
AM27C256-120DE , 256 Kilobit (32 K x 8-Bit) CMOS EPRO
AM27C256-120DI , 256 Kilobit (32 K x 8-Bit) CMOS EPRO
AM27C256-120DI , 256 Kilobit (32 K x 8-Bit) CMOS EPRO
AM27C256-120DIB , 256 Kilobit (32 K x 8-Bit) CMOS EPRO
AM27C256-150DC , 256 Kilobit (32 K x 8-Bit) CMOS EPRO
ADV473KP110-ADV473KP66-ADV473KP80
CMOS 135 MHz True-Color Graphics Triple 8-Bit Video RAM-DAC
REV.A
CMOS 135 MHz True-Color Graphics
Triple 8-Bit Video RAM-DAC
MODES
24-Bit True Color
8-Bit Pseudo Color
15-Bit True Color
8-Bit True Color
SPEED GRADES
135 MHz, 110 MHz
80 MHz, 66 MHz
GENERAL DESCRIPTIONThe ADV473 is a complete analog output, Video RAM-DAC
on a single CMOS monolithic chip. The part is specifically
designed for true-color computer graphics systems.
The ADV473 integrates a number of graphic functions onto one
device allowing 24-bit direct true-color operation at the maxi-
mum screen update rate of 135 MHz. It can also be used in
other modes, including 15-bit true color and 8-bit pseudo or in-
dexed color. The ADV473 is fully PS/2 and VGA register level
compatible. It is also capable of implementing IBM’s XGA
standard.
(Continued on page 4)
FEATURES
ADV478/ADV471 (ADV®) Register Level Compatible
IBM PS/2,* VGA*/XGA* Compatible
135 MHz Pipelined Operation
Triple 8-Bit D/A Converters
Triple 256 3 8 (256 3 24) Color Palette RAM
Three 15 3 8 Overlay Registers
On-Board Voltage Reference
RS-343A/RS-170 Compatible Analog Outputs
TTL Compatible Digital Inputs and Outputs
Sync on All Three Channels
Programmable Pedestal (0 or 7.5 IRE)
Standard MPU l/O Interface
+5 V CMOS Monolithic Construction
68-Pin PLCC Package
APPLICATIONS
High Resolution Color Graphics
True-Color Visualization
CAE/CAD/CAM
Image Processing
Desktop Publishing
FUNCTIONAL BLOCK DIAGRAM
ADV is a registered trademark of Analog Devices Inc.
*Personal System/2 and VGA are trademarks of International Business Machines Corp.
ADV473–SPECIFICATIONS
(VAA1 = 5 V; VREF = 1.235 V; RL = 37.5 Ω, CL = 10 pF; RSET = 140 Ω.
All specifications TMIN to TMAX2 unless otherwise noted.)NOTESVAA = 5 V ± 5%Temperature range (TMIN to TMAX); 0°C to +70°C; TJ (Silicon Junction Temperature) ≤ 100°C.Pixel Port is continuously clocked with data corresponding to a linear ramp.Clock and data feedthrough is a function of the amount of overshoot and undershoot on the digital inputs. Glitch impulse includes clock and data feedthrough.TTL input values are 0 to 3 volts, with input rise/fall times ≤ 3 ns, measured at the 10% and 90% points. Timing reference points at 50% for inputs and outputs.DAC to DAC Crosstalk is measured by holding one DAC high while the other two are making low to high and high to low transitions.
Specifications subject to change without notice.
TIMING CHARACTERISTICS1(VAA2 = 5 V; VREF = 1.235 V; RL = 37.5 Ω, CL = 10 pF; RSET = 140 Ω.
All specifications TMIN to TMAX3 unless otherwise noted.)NOTES
1TTL input values are 0 to 3 volts, with input rise/fall times ≤ 3 ns, measured between the 10% and 90% points. Timing reference points at 50% for inputs and
outputs. Analog output load ≤ 10 pF, D0-D7 output load ≤ 50 pF. See timing notes in Figure 2.
2VAA = 5 V ± 5%.
3Temperature range (TMIN to TMAX); 0°C to +70°C; TJ (Silicon Junction Temperature) ≤ 100°C .
4t3 and t4 are measured with the load circuit of Figure 3 and defined as the time required for an output to cross 0.4 V or 2.4 V.
5t5 and t6 are derived from the measured time taken by the data outputs to change by 0.5 V when loaded with the circuit of Figure 3. The measured number is
then extrapolated back to remove the effects of charging the 50 pF capacitor. This means that the times, t5 and t6, quoted in the timing characteristics are the
true values for the device and, as such, are independent of external bus loading capacitances.
6Settling time does not include clock and data feedthrough.
Specifications subject to change without notice.
Figure 1. MPU Read/Write Timing
ADV473
RECOMMENDED OPERATING CONDITIONS
CAUTIONESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000
accumulate on the human body and test equipment and can discharge without detection.
Although the ADV473 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
The ADV473 is capable of generating RGB video output sig-
nals, without requiring external buffering, and which are com-
patible with RS-343A and RS-170 video standards. All digital
inputs and outputs are TTL compatible.
The part can be driven by the on-board voltage reference or an
external voltage reference.
The part is packaged in a 68-pin Plastic Leaded Chip Carrier
(PLCC).
(Continued from page 1)
The device consists of three, high speed, 8-bit, video D/A con-
verters (RGB), a 256 3 24 RAM which can be configured as a
look-up table or a linearization RAM, a 24-bit wide parallel
pixel input port and three 15 3 8 overlay registers. The part is
controlled through the MPU port by the various on-board con-
trol/command registers.
The individual red, green and blue pixel input ports allow true-
color, image rendition. True-color image rendition, at speeds of
up to 135 MHz, is achieved through the 24-bit pixel input port.
The ADV473 is also capable of implementing 8-bit true color,
ABSOLUTE MAXIMUM RATINGS1VAA to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 V
Voltage on Any Digital Pin . . . .GND – 0.5 V to VAA + 0.5 V
Ambient Operating Temperature (TA) . . . . .–55°C to +125°C
Storage Temperature (TS) . . . . . . . . . . . . . .–65°C to +150°C
Junction Temperature (TJ) . . . . . . . . . . . . . . . . . . . .+150°C
Lead Temperature (Soldering, 10 secs) . . . . . . . . . . .+300°C
Vapor Phase Soldering (2 minutes) . . . . . . . . . . . . . .+220°C
IOR, IOG, IOB to GND2 . . . . . . . . . . . . .GND–0.5 V to VAA
NOTESStresses above those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those listed in the
operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.Analog output short circuit to any power supply or common can be of an indefinite
duration.
ORDERING GUIDENOTEAll devices are packaged in a 68-pin plastic leaded (J-lead) chip carrier.
PIN CONFIGURATION
68-Pin PLCC
PIN FUNCTION DESCRIPTIONBLANKComposite Blank Control Input (TTL Compatible). A logic zero drives the analog outputs to the blanking level.
It is latched on the rising edge of CLOCK. When BLANK is a logical zero, the pixel and overlay inputs are
ignored.
SYNCComposite SYNC Control Input (TTL Compatible). A logical zero on this input switches off a 40 IRE current
source on the analog outputs. SYNC does not override any other control or data input; therefore, it should be
asserted only during the blanking interval. It is latched on the rising edge of CLOCK. If sync information is not
required on the analog outputs, SYNC should be connected to ground.
CLOCKClock Input (TTL Compatible). The rising edge of CLOCK latches the R0–R7, G0–G7, B0–B7, S0, S1,
OL0–OL3, SYNC, and BLANK inputs. It is typically the pixel clock rate of the video system. It is
recommended that CLOCK be driven by a dedicated TTL buffer.
R0–R7Red, Green and Blue Select Inputs (TTL Compatible). These inputs specify, on a pixel basis, the color value to
B0–B7be written to the DACs. They are latched on the rising edge of CLOCK. R0, G0 and B0 are the LSBs. Unused
G0–G7inputs should be connected to GND.
S0, S1Color Mode Select Inputs (TTL Compatible). These inputs specify the mode of operation as shown in Table III.
They are latched on the rising edge of CLOCK.
OL0–OL3Overlay Select Inputs (TTL Compatible). These inputs specify which palette is to be used to provide color
information. When accessing the overlay palette, the R0–R7, G0–G7, B0–B7, S0 and S1 inputs are ignored. They
are latched on the rising edge of CLOCK. OL0 is the LSB. Unused inputs should be connected to GND.
IOR, IOG, IOBRed, Green, and Blue Current Outputs. These high impedance current sources are capable of directly driving a
doubly terminated 75 Ω coaxial cable.
RSETFull-Scale Adjust Resistor. A resistor (RSET) connected between this pin and GND controls the magnitude of the
full-scale video signal. The relationship between RSET and the full-scale output current on each output is:
RSET (Ω) = 3,195 × VREF (V)/IOUT (mA) SETUP = 7.5 IRE)
RSET (Ω) = 3,025 × VREF (V)/IOUT (mA) SETUP = 0 IRE)
COMPCompensation Pin. These pins should be connected together at the chip and connected through 0.1 μF ceramic
capacitor to VAA.
VREFINVoltage Reference Input. This input requires a 1.2 V reference voltage. This is achieved through the on-board
voltage reference generator by connecting VREFOUT to VREFIN. If an external reference is used, it must supply
this input with a 1.2 V (typical) reference.
VREFOUTVoltage Reference Output. This output delivers a 1.2 V reference voltage from the device’s on-board voltage
reference generator. It is normally connected directly to the VREFIN pin. If it is preferred to use an external
voltage reference, this pin may be left floating. Up to four ADV473s can be driven from VREFOUT.
VAAAnalog power. All VAA pins must be connected.
GNDAnalog Ground. All GND pins must be connected.Write Control Input (TTL Compatible). D0–D7 data is latched on the rising edge of WR, and RS0–RS2 are
latched on the falling edge of WR during MPU write operations. RD and WR should not be asserted
simultaneously.Read Control Input (TTL Compatible). To read data from the device, RD must be a logical zero. RS0–RS2 are
latched on the falling edge of RD during MPU read operations. RD and WR should not be asserted
simultaneously.
RS0, RS1, RS2Register Select Inputs (TTL Compatible). RS0–RS2 specify the type of read or write operation being performed.
D0–D7Data Bus (TTL Compatible). Data is transferred into and out of the device over this eight-bit bidirectional data
bus. D0 is the least significant bit.
CR0–CR7Control Outputs (TTL Compatible). These outputs are used to control application specific features. The output
values are determined by the contents of the command register (CR).
ADV473
CIRCUIT DESCRIPTION
MPU InterfaceThe ADV473 supports a standard MPU bus interface, allowing
the MPU direct access to the color palette RAM and overlay
color registers.
Three address decode lines, RS0–RS2, specify whether the
MPU is accessing the address register, the color palette RAM,
the overlay registers, or read mask register. These controls also
determine whether this access is a read or write function. Table
I illustrates this decoding. The 8-bit address register is used to
address the contents of the color palette RAM and overlay
registers.
Table I. Control Input Truth Table
Color Palette WritesThe MPU writes to the address register (selecting RAM write
mode, RS2 = 0, RS1 = 0 and RS0 = 0) with the address of the
color palette RAM location to be modified. The MPU performs
three successive write cycles (8 or 6 bits each of red, green, and
blue), using RS0–RS2 to select the color palette RAM (RS2 =
0, RS1 = 0, RS0 = 1). After the BLUE write cycle, the three
bytes of color information are concatenated into a 24-bit word
or an 18-bit word and written to the location specified by the
address register. The address register then increments to the
next location which the MPU may modify by simply writing an-
other sequence of red, green, and blue data. A complete set of
colors can be loaded into the palette by initially writing the start
address and then performing a sequence of RED, GREEN and
BLUE writes. The address automatically increments to the next
highest location after a BLUE write.
Color Palette ReadsThe MPU writes to the address register (selecting RAM read
mode, RS2 = 0, RS1 = 1 and RS0 = 1) with the address of the
color palette RAM location to be read back. The contents of the
palette RAM are copied to the RED, GREEN and BLUE regis-
ters and the address register increments to point to the next pal-
ette RAM location. The MPU then performs three successive
read cycles (8 or 6 bits each of red, green, and blue), using
RS0–RS2 to select the color palette RAM (RS2 = 0, RS1 = 0,
RS0 = 1). After the BLUE read cycle, the 24/18 bit contents of
the palette RAM at the location specified by the address register
is loaded into the RED, GREEN and BLUE registers. The ad-
dress register then increments to the next location which the
MPU can read back by simply reading another sequence of red,
green, and blue data. A complete set of colors can be read back
from the palette by initially writing the start address and then
TERMINOLOGY
BLANKING LEVELThe level separating the SYNC portion from the video portion
of the waveform. Usually referred to as the front porch or back
porch. At 0 IRE units, it is the level which will shut off the pic-
ture tube, resulting in the blackest possible picture.
COLOR VIDEO (RGB)This usually refers to the technique of combining the three pri-
mary colors of red, green and blue to produce color pictures
within the usual spectrum. In RGB monitors, three DACs are
required, one for each color.
COMPOSITE SYNC SIGNAL (SYNC)The position of the composite video signal which synchronizes
the scanning process.
COMPOSITE VIDEO SIGNALThe video signal with or without setup, plus the composite
SYNC signal.
GRAY SCALEThe discrete levels of video signal between reference black and
reference white levels. An 8-bit DAC contains 256 different lev-
els while a 6-bit DAC contains 64.
RASTER SCANThe most basic method of sweeping a CRT one line at a time to
generate and to display images.
REFERENCE BLACK LEVELThe maximum negative polarity amplitude of the video signal.
REFERENCE WHITE LEVELThe maximum positive polarity amplitude of the video signal.
SETUPThe difference between the reference black level and the blank-
ing level.
SYNC LEVELThe peak level of the composite SYNC signal.
VIDEO SIGNALThat portion of the composite video signal which varies in gray
scale levels between reference white and reference black. Also
referred to as the picture signal, this is the portion which may be
visually observed.
