ADV471KP50 ,CMOS 80 MHz Monolithic 256 x 24(18) Color Palette RAM-DACsApplications
Image Processing
Instrumentation
Desktop Publishing
AVAILABLE CLOCK RATES
80M ..
ADV471KP66 ,CMOS 80 MHz Monolithic 256 x 24(18) Color Palette RAM-DACsANALOG
DEVICES
CMOS 80MHz Monolithic 256 x 24(18)
Color Palette RAM-DACs
AlW478/NW471
ADV471KP80 ,CMOS 80 MHz Monolithic 256 x 24(18) Color Palette RAM-DACsSpecifications TmtoTMS.)
I
Parameter KPSO Version KP35 Version Units Conditions/Comments
80 ..
ADV473KP110 ,CMOS 135 MHz True-Color Graphics Triple 8-Bit Video RAM-DACspecifications T to T unless otherwise noted.)MIN MAXParameter All Versions Units Test Conditions/C ..
ADV473KP66 ,CMOS 135 MHz True-Color Graphics Triple 8-Bit Video RAM-DACAPPLICATIONSmum screen update rate of 135 MHz. It can also be used inHigh Resolution Color Graphics ..
ADV473KP80 ,CMOS 135 MHz True-Color Graphics Triple 8-Bit Video RAM-DACCHARACTERISTICSMIN MAX135 MHz 110 MHz 80 MHz 66 MHzParameter Version Version Version Version Units ..
AM27C256 , 256 Kilobit (32 K x 8-Bit) CMOS EPRO
AM27C256 , 256 Kilobit (32 K x 8-Bit) CMOS EPRO
AM27C256-120DC , 256 Kilobit (32 K x 8-Bit) CMOS EPRO
AM27C256-120DC , 256 Kilobit (32 K x 8-Bit) CMOS EPRO
AM27C256-120DC , 256 Kilobit (32 K x 8-Bit) CMOS EPRO
AM27C256-120DE , 256 Kilobit (32 K x 8-Bit) CMOS EPRO
ADV471KP35-ADV471KP50-ADV471KP66-ADV471KP80-ADV478KP35-ADV478KP50-ADV478KP66
CMOS 80 MHz Monolithic 256 x 24(18) Color Palette RAM-DACs
ANALOG
DEVICES
CMOS 80MHz Monolithic 256 x 24(18)
Color Palette RAM-DACs
AlW478/hiW471
FEATURES
Personal System/2* Compatible
80MHz Pipelined Operation
Triple 8-Bit (6-Bit) D/A Converters
256x 24(18) Color Palette RAM
15 x 24(18) Overlay Registers
RS-343A/RS-170 Compatible Outputs
Sync on All Three Channels
Programmable Pedestal (0 or 7.5 IRE)
External Voltage or Current Reference
Standard MPU Interface
+5V CMOS Monolithic Construction
44-Pin PLCC Package
Power Dissipation: 800mW
APPLICATIONS
High Resolution Color Graphics
CAE/CAD/CAM Applications
Image Processing
Instrumentation
Desktop Publishing
AVAILABLE CLOCK RATES
GENERAL DESCRIPTION
The ADV478 (ADV@) and ADV471 are pin compatible and
software compatible RAM-DACs designed specifically for Personal
System/2 compatible color graphics.
The ADV478 has a 256 X 24 color lookup table with triple 8-bit
video D/A converters. It may be configured for either 6 bits or
8 bits per color operation. The ADV471 has a 256 X 18 color
lookup table with triple 6-bit video D/A converters.
Options on both parts include a programmable pedestal (0 or
7.5 IRE) and use of an external voltage or current reference.
ADV is a registered trademark of Analog Devices, Inc.
*Personal System/2 is a trademark of International Business Machines
REV. B
Information furnished by Analog Devices is believed to be accurate and
reliable, However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
FUNCTIONAL BLOCK DIAGRAM
REFERENCE
AMPLIFIER
ADV478/ADV471
po C32," IOR
P7 CE J 'h'S, Tab 256x24(18) -v
a MASK COLOR PALETTF
SYNC o W REG W RAM -ra-, '06
LATCH -v
BLANK o --r 15x24(18) -r,
OL0 end *4 2x534 8(6) JOB
OL3 V, 24(18)
a SETUP
ADDRESS
REGISTER
8(6) 8(6) 8(6!
a eémcl
BUS CONTROL
R70 1ht-R R80 RS1 RS2
I NUMBERS IN PARENTHESIS INDICA'IE PIN NAMES FOR THE ADVAII
2. NC - NO CONNECT
Fifteen overlay registers provide for overlaying cursors, grids,
menus, EGA emulation, etc. Also supported is a pixel read
mask register and sync generation on all three channels.
The ADV478 and ADV471 generate RS-343A compatible video
signals into a doubly terminated 75n load, and RS-l70 compatible
video signals into a singly terminated 75n load, without requiring
external buffering. Differential and integral linearity errors are
guaranteed to be a maximum of t lLSB for the ADV478 and
: 1/4LSB for the ADV471 over the full temperature range.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700 Fax: 617/326-8703 wa: 710/394-6577
Telex: 924491 Cable: ANALOG NORWOODMASS
AlW478/NW471-SPEiyFltym0lllS
" = + 5ll, SEIUP = MI --b, hrs = +1.235V. itssr=147n.
All Specifications u, to TMZ unless thhemise noted.)
Parameter All Versions Units Test Conditions/Comments
STATIC PERFORMANCE
Resolution (Each DAC)3 8 (6) Bits
Accuracy (Each DAC)3
Integral Nonlinearity t 1 (1/4) LSB max
Differential Nonlinearity t 1 (1/4) LSB max Guaranteed Monotonic
Gray Scale Error t 5 % Gray Scale max
Coding Binary
DIGITAL INPUTS
Input High Voltage, Vom 2 V min
Input Low Voltage, VINL 0.8 V max
Input Current, Im. L 1 " max VIN = 0.4V or 2.4V
Input Capacitance, Cm pF max
DIGITAL OUTPUTS
Output High Voltage, Vos, 2.4 V min [SOURCE = 400WA
Output Low Voltage, V01. 0.4 V max [SINK = 3.2mA
Floating-State Leakage Current 50 " max
Floating-State Output Capacitance 7 pF max
ANALOG OUTPUTS
Gray Scale Current Range 20 mA max
Output Current
White Level Relative to Blank 17.69 mA min Typically 19.05mA
20.40 mA max
White Level Relative to Black 16.74 mA min Typically 17.62mA
18.50 mA max
Black Level Relative to Blank 0.95 mA min Typically 1.44mA
(SETUP=VAA) 1.90 mA max
Black Level Relative to Blank 0 WA min Typically 511A
(SETUP = GND) 50 WA max
Blank Level 6.29 mA min Typically 7.62mA
8.96 mA max
Sync Level 0 WA min Typically SLLA
50 uA max
LSB Size3 . 69.1 (279.68) " typ 8/6 = Logical l for ADV478
DAC to DAC Matching 5 % max Typically 2%
Output Compliance, Voc - 1 V min
+ 1.5 V max
Output Impedance, Rom 10 kfl typ
Output Capacitance, Com- 30 pF max 10111: OmA
VOLTAGE REFERENCE
Voltage Reference Range, VREF l . 14/ 1 .26 V min/V max
Input Current, IVREF 10 pA typ Tested in Voltage Reference
Configuration with VREF = 1.235V
POWER SUPPLY
Supply Voltage, VAA 4. 75/5.25 V min/V max 80MHz and 66MHz Parts
4.50/5.50 V min/V max 50MHz and 35MHz Parts
Supply Current, [M 220 mA max Typically 180mA
Power Supply Rejection Ratio 0.5 %/% max f= lkHz, COMP = 0.lwF
Power Dissipation 1100 mW max Typically 900mW, V A A = 5V
DYNAMIC PERFORMANCE
Clock and Data Feedthrough''5 - 30 dB typ
Glitch Impulse" 75 pV secs typ
DAC to DAC Crosstalk" - 23 dB typ
I t 5% for SOMHZ and 66MHz parts; i 10% for SOMHZ and 35MHz parts.
"Temperature Range (Tmu, to Tmax); 0 to + 70°C.
'Numbers in parentheses indicate ADV471 parameter value.
'Clock and data feedthrough is a function of the amount of overshoot and undershoot on the digital inputs. For this test, the digital inputs have a
lkn resistor to ground and are driven by 74HC logic. Glitch impulse includes clock and data feedthrough, - 3dB test bandwidth - 2 X clock rate.
'TTL input values are 0 to 3 volts, with input rise/fall times s3ns, measured between the 10% and 90% points. Timing reference points at 50%
for inputs and outputs. Analog output load SlOpF, D0 - D7 output load SSOpF. See timing notes in Figure 2.
6DAC to DAC crosstalk is measured by holding one DAC high while the other two are making low to high and high to low transitions.
Specifications subject to change without notice.
REV. B
ADV473/ADV471
TIMING iyatNnEItgmtsl (ll 2= +stsmP--M--uhrr--1235v.itw--14mnMpeeiiieaiitmsut0Tma,'.)
Parameter KP80 Version KP66 Version KPSO Version KP35 Version Units Conditions/Comments
fmax 80 66 50 3 5 MHz Clock Rate
tr 10 10 10 10 ns min RSO - RS2 Setup Time
t2 10 10 10 10 ns min RSO - R82 Hold Time
ts S 5 5 5 ns min W Asserted to Data Bus Driven
t4 40 40 40 40 ns max E Asserted to Data Valid
ts 20 20 20 20 ns max E Negated to Data Bus 3-Stated
ts 10 10 10 10 ns min Write Data Setup Time
ty 10 10 10 10 ns min Write Data Hold Time
ts 50 50 50 50 ns min E, W Pulse Width Low
te 6>
tlo 3 3 3 3 ns min Pixel and Control Setup Time
I, 1 3 3 3 3 ns min Pixel and Control Hold Time
[12 12.5 15.3 20 28 ns min Clock Cycle Time
113 4 5 6 7 ns min Clock Pulse Width High Time
ts 4 5 6 9 ns min Clock Pulse Width Low Time
tcs 30 30 30 30 ns max Analog Output Delay
Inc, 3 3 3 3 ns typ Analog Output Rise/Fall Time
tn“ 13 15.3 20 28 ns typ Analog Output Settling Time
rm 2 2 2 2 ns max Analog Output Skew
tpD 4xtl, 4>'TTL input values are 0 to 3 volts, with input rise/fall times s3ns, measured between the 10% and 90% points. Timing reference
points at 50% for inputs and outputs. Analog output load sl0pF, 37.59. D0 - D7 output load <50pF. See timing notes in Figure 2.
3: 5% for 80MHz and 66MHz parts; t 5% for 50MHz and 35MHz parts.
'Temperature Range (Tmin to Tmax); 0 to + 70°C.
'Settling time does not include clock and data feedthrough. For this test, the digital inputs have a Ikft resistor to ground and are
driven by 7411C logic.
Specifications subject to change without notice
TIMING DIAGRAMS
RSO, RSI, RS2
T6.fiim
READ (DO - D7)
WRITE (DO - D7)
Figure I. MPU Head Write Timing
tlit -
t1: tsa--
CLOCK (-Nc,p,_/''-'xsc_,
P0 - P7 0L0 - 0L3
'''-''"" ' DATA EYSSSE
SYNC. BLANK S
tur- " trs
t,, t17
IOR, IOG, IOB
1. OUTPUT DELAY (M5) MEASURED FROM THE 50% POINT OF THE RISING EDGE OF CLOCK TO
THE 50°/o POINT OF FULL SCALE TRANSITION.
2. SETTLING TIME (tn) MEASURED FROM THE 50% POINT OF FULL SCALE TRANSITION TO THE
OUTPUT REMAINING WITHIN ttLSB (ADV478) OR I1/4LSB (ADV471).
3. OUTPUT RISE/FALL TIMEit,s)MEASURED BETWEEN THE10% AND 90% POINTS OF FULL SCALE
TRANSITION.
Figure 2. Video Input Output Timing
REV. B -3-
hlM78/h0ll471
RECOMMENDED OPERATING CONDITIONS
Parameter Symbol Min Typ Max Units
Power Supply V AA
80MHz, 66MHz Parts 4.75 5.00 5.25 Volts
50, 35MHz Parts 4.5 5.00 5.5 Volts
Ambient Operating Temperature TA 0 + 70 °C
Output Load Ru 37.5 n
Voltage Reference Configuration
Reference Voltage VREF 1.14 1.235 1.26 Volts
Current Reference Configuration
Reference Current IREF - 3 - 10 mA
CAUTION
ESD (electrostatic discharge) sensitive device. The digital control inputs are diode protected;
however, permanent damage may occur on unconnected devices subject to high energy electro-
static fields. Unused devices must be stored in conductive foam or shunts. The protective foam
should be discharged to the destination socket before devices are removed.
ESD SENSITIVE DEVICE
ABSOLUTE MAXIMUM RATINGS' PLCC PIN CONFIGURATION
VAA to GND ....................... + 7V 0 g 6
Voltage on Any Digital Pin . . . GND -0.5V to VAA +0.5V R ii s t '2 g [is', 2 8 g 'i,'
Ambient Operating Temperature (TA) . . - 55°C to + 125°C mmmm 2 mmmm-W
Storage Temperature (Ts) .......... - 65°C to + 150°C o 0
Lead Temperature (Soldering, 10 secs) ........ + 300°C BLANK Ei P7
Junction Temperature (Tl) .............. + 150°C Do 3 P6
Vapor Phase Soldering (1 minute) ............ 220°C
IOR, IOB, IOG to GND1 .............. 0V to VAA
ADV478/ADV471
TOP VIEW
(Not to Scale) E P2
'Stresses above those listed under "Absolute Maximum Ratings" may
cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above
those listed in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.
'Analog output short circuit to any power supply or common can be of an
indefinite duration.
aazafflfilflflflfl
[£113]
RSO E E] COMP
k l1rll1-sllyellsyj1ell:ellellelleltiefle)
§ tfo, 5 E 5 , , , 8 3 ,
l, NUMBERS IN PARENTHESIS INDICATE PIN NAMES FOR THE ADV47I.
2. NC = N0 CONNECT
ORDERING GUIDE
Temperature Color Palette Package
Model Range RAM Speed Option'
ADV471KP8O 0°C to + 70°C 256 X 18 80MHz P-44A
ADV471KP66 0°C to + 70°C 256 x 18 66MHz P-44A
ADV471KP50 0°C to + 70°C 256 X 18 50MHz P-44A
ADV471KP35 0°C to + 70°C 256 X 18 35MHz P-44A
ADV478KP80 0°C to + 70°C 256 x 24 80MHz P-44A
ADV478KP66 0°C to + 70°C 256 A 24 66MHz P-44A
ADV478KP50 0°C to +70°C 256 y; 24 50MHz P-44A
ADV478KP35 0°C to + 70°C 256 x 24 35MHz P-44A
*P = Plastic Leaded Chip Carrier (PLCC).
REV. B
hml478/hml471
Mnemonic
PIN FUNCTION DESCRIPTION
F unction
OL0 - 0L3
IOR, IOG, IOB
Composite blank control input (TTL compatible). A logic zero drives the analog outputs to the blanking level
as illustrated in Tables IV and V. It is latched on the rising edge of CLOCK. When BLANK is a logical zero,
the pixel and overlay inputs are ignored
Setup control input. Used to specify either a O IRE (SETUP-- GND) or 7.5 IRE (SETUP-- VAA)
blanking pedestal.
Composite sync control input (TTL compatible). A logical zero on this input switches off a 40 IRE current
source on the analog outputs (see Figures 3 and 4). SYNC does not override any other control or data input,
as shown in Tables IV and V; therefore, it should be asserted only during the blanking interval. It is latched
on the rising edge of CLOCK.
Clock input (TTL compatible). The rising edge of CLOCK latches the P0 - P7, 0L0 - 0L3, SYNC, and
BLANK inputs. It is typically the pixel clock rate of the video system. It is recommended that CLOCK be
driven by a dedicated TTL buffer.
Pixel select inputs (TTL compatible). These inputs specify, on a pixel basis, which one of the 256 entries in
the color palette RAM is to be used to provide color information. They are latched on the rising edge of CLOCK.
P0 is the LSB. Unused inputs should be connected to GND.
Overlay select inputs (TTL compatible). These inputs specify which palette is to be used to provide color
information, as illustrated in Table 111. When accessing the overlay palette, the P0 - P7 inputs are ignored.
They are latched on the rising edge of CLOCK. 0L0 is the LSB. Unused inputs should be connected to
Red, green, and blue current outputs. These high impedance current sources are capable of directly driving a
doubly terminated 75n coaxial cable (Figures 5 and 6).
Full-scale adjust control. Note that the IRE relationships in Figures 3 and 4 are maintained, regardless of the
full-scale output current.
When using an external voltage reference (Figure 5), a resistor (R557) connected between this pin and GND
controls the magnitude of the full-scale video signal. The relationship between Rse-r and the full-scale output
current on each output is:
RSET (n)-- K * 1,000 * VREF (V)/10UT (IDA)
K is defined in the table below, along with corresponding RSET values for doubly terminated 75ft loads.
When using an external current reference (Figure 6), the relationship between IRE]: and the full-scale output
current on each output is:
IREF (mA) = Iotrr (mA)/K
Mode Pedestal K Rsrrr (n)
6-Bit 7.51RE 3.170 147
8-Bit 7.51RE 3.195 147
6-Bit 0 IRE 3.000 147
8-Bit 0 IRE 3.025 147
Compensation pin. If an external voltage reference is used (Figure 5), this pin should be connected to OPA. If
an external current reference is used, this pin should be connected to IREF. A 0.1p.F ceramic capacitor must
always be used to bypass this pin to VAA.
Voltage reference input. If an external voltage reference is used (Figure 5), it must supply this input with a
1.2V (typical) reference. If an external current reference is used (Figure 6), this pin should be left floating,
except for the bypass capacitor. A 0.1wF ceramic capacitor must always be used to decouple this input to
VAA as shown in Figures 5 and 6.
Reference amplifier output. If an external voltage reference is used (Figure 5), this pin must be connected to
COMP. When using an external current reference (Figure 6), this pin should be left floating.
Analog power. All VAA pins must be connected to the Analog Power Plane.
Analog ground. All GND pins must be connected to the Ground Plane.
Write control input (TTL comp_atible). D0 - D7 data is latched on the rising edge of W, and R30 - RS2 are
latched on the falling edge of WR during MPU write operations. See Figure l.
REV. B
