ADV202BBC-150 ,JPEG 2000 Video CODECApplications.... 34 SPI Port Timing .. 18 Encode—Multichip Mode... 34 Pin BGA Assignments and Funct ..
ADV202BBCZ-115 ,JPEG2000 Video CodecAPPLICATIONS Complete single-chip JPEG2000 compression and Networked video and image distribution s ..
ADV202BBCZ-115 ,JPEG2000 Video Codecapplications. Flexible asynchronous SRAM-style host interface allows glueless connection to most 1 ..
ADV202BBCZ-150 ,JPEG 2000 Video CODECSpecifications... 5 JDATA Mode....... 27 Normal Host Mode—Read Operation .. 6 External DMA Engine ..
ADV212BBCZ-115 , JPEG 2000 Video Codec
ADV212BBCZ-150 , Wavescale Video Codec
AM27C128-90DC , 112dB 192kHz 24-BIT SCH DAC
AM27C128-90DE , 112dB 192kHz 24-BIT SCH DAC
AM27C2048 , 2 Megabit (128 K x 16-Bit) CMOS EPROM
AM27C256 , 256 Kilobit (32 K x 8-Bit) CMOS EPRO
AM27C256 , 256 Kilobit (32 K x 8-Bit) CMOS EPRO
AM27C256-120DC , 256 Kilobit (32 K x 8-Bit) CMOS EPRO
ADV202BBC-115-ADV202BBC-135-ADV202BBC-150-ADV202BBCZ-150
JPEG 2000 Video CODEC
JPEG2000 Video CodecRev. 0
FEATURES
Complete single-chip JPEG2000 compression and
decompression solution for video and still images
Patented SURF™ (spatial ultraefficient recursive filtering)
technology enables low power and low cost wavelet based
compression
Supports both 9/7 and 5/3 wavelet transforms with up to
6 levels of transform
Programmable tile/image size with widths up to 2048 pixels
in 3-component 4:2:2 interleaved mode, and up to
4096 pixels in single-component mode
Maximum tile/image height: 4096 pixels
Video interface directly supporting ITU.R-BT656,
SMPTE125M PAL/ NTSC, SMPTE274M, SMPTE293M (525p),
ITU.R-BT1358 (625p) or any video format with a maximum
input rate of 65 MSPS for irreversible mode or 40 MSPS for
reversible mode
Two or more ADV202s can be combined to support full-
frame SMPTE274M HDTV (1080i) or SMPTE296M (720p)
Interlaces temporally coherent frame-based SD video
sources for improved performance
Flexible asynchronous SRAM-style host interface allows
glueless connection to most 16-/32-bit microcontrollers
and ASICs
2.5 V to 3.3 V I/O and 1.5 V core supply
12 mm × 12 mm 121-lead CSPBGA, speed grade 115 MHz, or
13 mm × 13 mm 144-lead CSPBGA, speed grade 150 MHz
APPLICATIONS
Networked video and image distribution systems
Wireless video and image distribution
Image archival/retrieval
Digital CCTV and surveillance systems
Digital cinema systems
Professional video editing and recording
Digital still cameras
Digital camcorders
GENERAL DESCRIPTION The ADV202 is a single-chip JPEG2000 codec targeted for
video and high bandwidth image compression applications that
can benefit from the enhanced quality and feature set provided
by the JPEG2000 (J2K)—ISO/IEC15444-1 image compression
standard. The part implements the computationally intensive
operations of the JPEG2000 image compression standard as
well as providing fully compliant code-stream generation for
most applications.
The ADV202’s dedicated video port provides glueless
connection to common digital video standards such as ITU.R-
BT656, SMPTE125M, SMPTE293M [525p], ITU.R-BT1358
[625p], SMPTE274M[1080i], or SMPTE296M[720p]. A variety
of other high speed synchronous pixel and video formats can
also be supported using the programmable framing and
validation signals.
(continued on Page 3)
FUNCTIONAL BLOCK DIAGRAM PIXEL I/F
HOST I/F
Figure 1.
TABLE OF CONTENTS General Description.........................................................................3
JPEG2000 Feature Support..........................................................3
Specificatons......................................................................................4
Supply Voltages and Current.......................................................4
Input/Output Specifications........................................................4
Clock and RESET Specifications................................................5
Normal Host Mode—Read Operation......................................6
Normal Host Mode—Write Operation.....................................7
DREQ/DACK DMA Mode—Single FIFO Write Operation..8
DREQ/DACK DMA Mode—Single FIFO Read Operation.10
External DMA Mode—FIFO Write, Burst Mode...................12
External DMA Mode—FIFO Read, Burst Mode....................13
Streaming Mode (JDATA)—FIFO Read/Write......................15
VDATA Mode Timing...............................................................15
Raw Pixel Mode Timing............................................................17
SPI Port Timing..........................................................................18
Pin BGA Assignments and Function Descriptions....................19
Pin BGA Assignments...............................................................19
Pin Function Descriptions........................................................22
Theory of Operation......................................................................25
Wavelet Engine...........................................................................25
Entropy Codecs...........................................................................25
Embedded Processor System....................................................25
Memory System..........................................................................25
Internal DMA Engine................................................................25
ADV202 Interface...........................................................................26
Video Interface (VDATA Bus)..................................................26
Host Interface (HDATA Bus)...................................................26
Direct and Indirect Registers....................................................26
Control Access Registers...........................................................27
Pin Configuration and Bus Sizes/Modes................................27
Stage Register..............................................................................27
JDATA Mode...............................................................................27
External DMA Engine...............................................................27
SPI Port........................................................................................27
Internal Registers............................................................................28
Direct Registers...........................................................................28
Indirect Registers........................................................................29
PLL...............................................................................................30
Hardware Boot............................................................................31
Video Input Formats......................................................................32
Applications.....................................................................................34
Encode—Multichip Mode.........................................................34
Decode—Multichip Master/Slave............................................35
Digital Still Camera/Camcorder..............................................35
Encode/Decode SDTV Video Application..............................36
ASIC Application (32-Bit Host/32-Bit ASIC).........................37
HIPI (Host Interface—Pixel Interface)...................................38
JDATA Interface.........................................................................38
Outline Dimensions.......................................................................39
Ordering Guide..........................................................................40
REVISION HISTORY
7/04—Revision 0: Initial Version GENERAL DESCRIPTION (continued from Page 1)
The ADV202 can process images at a rate of 40MSPS in
reversible mode and at higher rates when used in irreversible
mode. The ADV202 contains a dedicated wavelet transform
engine, three entropy codecs, an on-board memory system, and
an embedded RISC processor that can provide a complete
JPEG2000 compression/decompression solution.
The wavelet processor supports the 9/7 irreversible wavelet
transform and the 5/3 wavelet transform in reversible and
irreversible modes. The entropy codecs support all features in
the JPEG2000 Part 1 specification, except Maxshift ROI.
The ADV202 operates on a rectangular array of pixel samples
called a tile. A tile can contain a complete image, up to the
maximum supported size, or some portion of an image. The
maximum horizontal tile size supported depends on the wavelet
transform selected and the number of samples in the tile.
Images larger than the ADV202’s maximum tile size can be
broken into individual tiles and then sent sequentially to the
chip while still maintaining a single, fully compliant JPEG2000
code stream for the entire image.
JPEG2000 FEATURE SUPPORT The ADV202 supports a broad set of features that are included
in Part 1 of the JPEG2000 standard (ISO/IEC 15444). See
Getting Started with ADV202 for information on the JPEG2000
features that the ADV202 currently supports.
Depending on the particular application requirements, the
ADV202 can provide varying levels of JPEG2000 compression
support. It can provide raw code-block and attribute data
output, which allows the host software to have complete control
over the generation of the JPEG2000 code stream and other
aspects of the compression process such as bit-rate control.
Otherwise, the ADV202 can create a complete, fully compliant
JPEG2000 code stream (.j2c) and enhanced file formats such as
.jp2, .jpx, and .mj2 (Motion JPEG2000). See Getting Started with
ADV202 for information on the formats that the ADV202
currently supports.
SPECIFICATONS
SUPPLY VOLTAGES AND CURRENT
Table 1. 1 No clock or I/O activity. ADV202-150 only.
INPUT/OUTPUT SPECIFICATIONS
Table 2. CLOCK AND RESET SPECIFICATIONS
Table 3. For a definition of MCLK, see the section. PLL
MCLK
VCLK
tMCLK
tMCLKHtMCLKL
Figure 2. Input Clock
NORMAL HOST MODE—READ OPERATION
Table 4. For a definition of JCLK, see the section. PLL
ADDR
tRH
ACK
Figure 3. Normal Host Mode—Read Operation
NORMAL HOST MODE—WRITE OPERATION
Table 5. For a definition of JCLK, see the section. PLL
ADDR
tWH
ACK
Figure 4. Normal Host Mode—Write Operation
DREQ/DACK DMA MODE—SINGLE FIFO WRITE OPERATION
Table 6. 1 Applies to assigned DMA channel, if EDMOD0 or EDMOD1 <14:11> is programmed to a value that is not 0. Pulse width depends on the value programmed. For a definition of JCLK, see the PLL section.
DACK
DREQ
tDREQ
tWEHD
Figure 5. Single Write for DREQ/DACK DMA Mode for Assigned DMA Channel
(EDMOD0/EDMOD1 <14:11> NOT Programmed to a Value of 0000)
DACK
DREQ
tWEHD
Figure 6. Single Write for DREQ/DACK DMA Mode for Assigned DMA Channel
(EDMOD0/EDMOD1 <14:11> Programmed to a Value of 0000)
WEFB
DACK
DREQ
tDREQ
tWEHD
Figure 7. Fly-By DMA Mode —Single Write Cycle (DREQ Pulse Width Is Programmable)
FSRQ0
FSC0
HDATA
NOT WRITTEN TO FIFO
Figure 8. DCS DMA Mode—Single Write Access (Rev. 0.1 and Higher)
DREQ/DACK DMA MODE—SINGLE FIFO READ OPERATION
Table 7. 1 Applies to assigned DMA channel, if EDMOD0 or EDMOD1 <14:11> is programmed to a nonzero value. For a definition of JCLK, see the section. PLL
DACK
DREQ
tDREQtRDHD
Figure 9. Single Read for DREQ/DACK DMA Mode for Assigned DMA Channel
(EDMOD0/EDMOD1 <14:11> NOT Programmed to a Value of 0000)
DACK
DREQtRDHD
Figure 10. Single Read forDREQ/DACK DMA Mode for Assigned DMA Channel
(EDMOD0/EDMOD1 <14:11> Programmed to a Value of 0000)
RDFB
DACK
DREQ
tDREQtRDHD
Figure 11. Fly-By DMA Mode—Single Read Cycle
(DREQ Pulse Width Is Programmable)
FSRQ0
FCS0
Figure 12. DCS DMA Mode—Single Read Access (Rev. 0.1 and Higher)
EXTERNAL DMA MODE—FIFO WRITE, BURST MODE
Table 8. Applies to assigned DMA channel, if EDMOD0 or EDMOD1 <14:11> is programmed to a value that is NOT 0. Pulse width depends on the value programmed.
2 For a definition of JCLK, see the section. PLL If sufficient space is available in FIFO.
DREQ
DACK
WEHIWELOtDACKSU
tDREQWAIT
Figure 13. Burst Write Cycle forDREQ/DMA Mode for Assigned DMA Channel
(EDMOD0/EDMOD1 <14:11> NOT Programmed to a Value of 0000)
DREQ
DACK
Figure 14. Burst Write Cycle for DREQ/DMA Mode for Assigned DMA Channel
(EDMOD0/EDMOD1 <14:11> Programmed to a Value of 0000)
DREQ
DACK
WEFB
WEHIWELOtDACKSU
Figure 15. Burst Write Cycle for Fly-By DMA Mode
(DREQ Pulse Width Is Programmable)
EXTERNAL DMA MODE—FIFO READ, BURST MODE
Table 9. Applies to assigned DMA channel, if EDMOD0 or EDMOD1 <14:11> is programmed to a value that is not 0. Pulse width depends on the value programmed.
2 For a definition of JCLK, see the section. PLL If sufficient data is available in FIFO.
DREQ
DACK
RDHIRDLO
Figure 16. Burst Read Cycle for DREQ/DACK DMA Mode for Assigned DMA Channel
(EMOD0/EDMOD1 <14:11> NOT Programmed to a Value of 0
DREQ
DACK
Figure 17. Burst Read Cycle for DREQ/DACK DMA Mode for Assigned DMA Channel
( EMOD0/EDMOD1 <14:11> Programmed to a Value of 0000)
DREQ
DACK
RDFB
Figure 18. Burst Read Cycle, Fly-By DMA Mode
(DREQ Pulse Width Is Programmable)
STREAMING MODE (JDATA)—FIFO READ/WRITE
Table 10. For a definition of JCLK, see the section. PLL
MCLK
JDATA
VALID
HOLD
Figure 19. Streaming Mode Timing—Encode Mode JDATA Output
MCLK
JDATA
VALID
HOLD
Figure 20. Streaming Mode Timing—Decode Mode JDATA Input
VDATA MODE TIMING
Table 11.
VCLK
VDATA(IN)
ENCODE CCIR-656 LINE
VCLK
VDATA(OUT)
VDATA(OUT)
DECODE MASTER CCIR-656 LINE
VCLK
VDATA(OUT)
VDATATD
*HSYNC AND VSYNC DO NOT HAVE TO BE APPLIED SIMULTANEOUSLY
VCLK
VDATA(IN)
HSYNC
VSYNC
ENCODE HVF MODE
DECODE SLAVE CCIR-656 LINE
VCLK
HSYNC
VSYNC
DECODE SLAVE HVF MODE
Figure 21. Video Mode Timing
RAW PIXEL MODE TIMING
Table 12. VCLK
VCLK
PIXEL
DATA(IN)
PIXEL
DATA
VFRM(IN)
VRDY
VSTRB
VRFMTD
VDATATD
Figure 22. Raw Pixel Mode Timing
SPI PORT TIMING
Table 13. S_CLK
S_MO
S_MI
S_CSEL
Figure 23. SPI Port—Input Timing
PIN BGA ASSIGNMENTS AND FUNCTION DESCRIPTIONS
PIN BGA ASSIGNMENTS
Table 14. Pin BGA Assignments for 121-Lead Package
Table 15. Pin BGA Assignments for 144-Lead Package
