ADUC847BS32-5 ,MicroConverter Multichannel 24-/16-Bit ADCs with Embedded 62 kB Flash and Single-Cycle MCUFEATURES High resolution Σ-∆ ADCs Normal: 4.8 mA max @ 3.6 V (core CLK = 1.57 MHz) Two independent ..
ADUC847BS62-3 ,MicroConverter Multichannel 24-/16-Bit ADCs with Embedded 62 kB Flash and Single-Cycle MCUAPPLICATIONS Multichannel sensor monitoring Memory Industrial/environmental instrumentation 62-kby ..
ADUC847BS8-5 ,MicroConverter Multichannel 24-/16-Bit ADCs with Embedded 62 kB Flash and Single-Cycle MCUFEATURES High resolution Σ-∆ ADCs Normal: 4.8 mA max @ 3.6 V (core CLK = 1.57 MHz) Two independent ..
ADUC847BSZ62-5 , MicroConverter® Multichannel 24-/16-Bit ADCs with Embedded 62 kB Flash and Single-Cycle MCU
ADUC848BCPZ62-5 , MicroConverter® Multichannel 24-/16-Bit ADCs with Embedded 62 kB Flash and Single-Cycle MCU
ADUC848BCPZ8-5 , MicroConverter® Multichannel 24-/16-Bit ADCs with Embedded 62 kB Flash and Single-Cycle MCU
AM27C010 , 1 Megabit ( 128 K x 8-Bit ) CMOS EPROM Speed options as fast as 45 ns
AM27C010-120DC , 1 Megabit ( 128 K x 8-Bit ) CMOS EPROM Speed options as fast as 45 ns
AM27C010-120DC , 1 Megabit ( 128 K x 8-Bit ) CMOS EPROM Speed options as fast as 45 ns
AM27C010-120DE , 1 Megabit ( 128 K x 8-Bit ) CMOS EPROM Speed options as fast as 45 ns
AM27C010-120DI , 1 Megabit ( 128 K x 8-Bit ) CMOS EPROM Speed options as fast as 45 ns
AM27C010-120JC , 1 Megabit ( 128 K x 8-Bit ) CMOS EPROM Speed options as fast as 45 ns
ADUC845BS62-3-ADuC845BS62-5-ADUC845BS8-3-ADUC847BCP8-5-ADUC847BS32-5-ADUC847BS8-5-ADUC848BS32-3-ADUC848BS62-3-ADUC848BS8-5
MicroConverter Multichannel 24-/16-Bit ADCs with Embedded 62 kB Flash and Single-Cycle MCU
MicroConverter® Multichannel
24-/16-Bit ADCs with Embedded 62 kB
Flash and Single-Cycle MCU
Rev. A
FEATURES
High resolution Σ-∆ ADCs
Two independent 24-bit ADCs on the ADuC845
Single 24-bit ADC on the ADuC847 and
single 16-bit ADC on the ADuC848
Up to 10 ADC input channels on all parts
24-bit no missing codes
22-bit rms (19.5 bit p-p) effective resolution
Offset drift 10 nV/°C, gain drift 0.5 ppm/°C chop enabled
Memory
62-kbyte on-chip Flash/EE program memory
4-kbyte on-chip Flash/EE data memory
Flash/EE, 100 year retention, 100 kcycle endurance
3 levels of Flash/EE program memory security
In-circuit serial download (no external hardware)
High speed user download (5 seconds)
2304 bytes on-chip data RAM
8051-based core
8051-compatible instruction set
High performance single-cycle core
32 kHz external crystal
On-chip programmable PLL (12.58 MHz max)
3 × 16-bit timer/counter
24 programmable I/O lines, plus 8 analog or
digital input lines
11 interrupt sources, two priority levels
Dual data pointer, extended 11-bit stack pointer
On-chip peripherals
Internal power-on reset circuit
12-bit voltage output DAC
Dual 16-bit Σ-∆ DACs
On-chip temperature sensor (ADuC845 only)
Dual excitation current sources (200 µA)
Time interval counter (wake-up/RTC timer)
UART, SPI®, and I2C® serial I/O
High speed dedicated baud rate generator (incl 115,200)
Watchdog timer (WDT)
Power supply monitor (PSM)
Power
Normal: 4.8 mA max @ 3.6 V (core CLK = 1.57 MHz)
Power-down: 20 µA max with wake-up timer running
Specified for 3 V and 5 V operation
Package and temperature range:
52-lead MQFP (14 mm × 14 mm), −40°C to +125°C
56-lead CSP (8 mm × 8 mm), −40°C to +85°C
APPLICATIONS
Multichannel sensor monitoring
Industrial/environmental instrumentation
Weigh scales, pressure sensors, temperature monitoring
Portable instrumentation, battery-powered systems
Data logging, precision system monitoring
FUNCTIONAL BLOCK DIAGRAM
AIN0
AIN9
AINCOM
RESET
DVDD
DGNDXTAL2XTAL1
REFIN+
REFIN–
REFIN2–
REFIN2+
Figure 1. ADuC845 Functional Block Diagram
TABLE OF CONTENTS Specifications.....................................................................................4
Abosolute Maximum Ratings.......................................................10
ESD Caution................................................................................10
Pin Configuration and Function Descriptions...........................11
General Description.......................................................................15
8052 Instruction Set...................................................................18
Timer Operation.........................................................................18
ALE...............................................................................................18
External Memory Access...........................................................18
Complete SFR Map....................................................................19
Functional Description..................................................................20
8051 Instruction Set...................................................................20
Memory Organization...............................................................22
Special Function Registers (SFRs)............................................24
ADC Circuit Information..........................................................26
Auxiliary ADC (ADuC845 Only)............................................32
Reference Inputs.........................................................................32
Burnout Current Sources..........................................................32
Reference Detect Circuit...........................................................33
Sinc Filter Register (SF).............................................................33
Σ-∆ Modulator............................................................................33
Digital Filter................................................................................33
ADC Chopping...........................................................................34
Calibration...................................................................................34
Programmable Gain Amplifier.................................................35
Bipolar/Unipolar Configuration..............................................35
Data Output Coding..................................................................36
Excitation Currents....................................................................36
ADC Power-On..........................................................................36
Typical Performance Characteristics...........................................37
ADC SFR Interface.....................................................................39
ADCSTAT (ADC Status Register)...........................................40
ADCMODE (ADC Mode Register).........................................41
ADC0CON1 (Primary ADC Control Register).....................43
ADC0CON2 (Primary ADC Channel Select Register)........44
SF (ADC Sinc Filter Control Register)....................................46
ICON (Excitation Current Sources Control Register)..........47
Nonvolatile Flash/EE Memory Overview...............................48
Flash/EE Program Memory......................................................49
User Download Mode (ULOAD).............................................50
Using Flash/EE Data Memory..................................................51
Flash/EE Memory Timing........................................................52
DAC Circuit Information..........................................................53
Pulse-Width Modulator (PWM)..............................................55
On-Chip PLL (PLLCON)..........................................................60 2C Serial Interface.....................................................................61
SPI Serial Interface.....................................................................64
Using the SPI Interface..............................................................66
Dual Data Pointers.....................................................................67
Power Supply Monitor...............................................................68
Watchdog Timer.........................................................................69
Time Interval Counter (TIC)....................................................70
8052 Compatible On-Chip Peripherals...................................73
Timers/Counters........................................................................75
UART Serial Interface................................................................80
Interrupt System.........................................................................85
Interrupt Priority........................................................................86
Interrupt Vectors........................................................................86
Hardware Design Considerations................................................87
External Memory Interface.......................................................87
Power-On Reset Operation........................................................88
Power Consumption...................................................................88
Power-Saving Modes..................................................................88
Grounding and Board Layout Recommendations.................89
Other Hardware Considerations...............................................90
QuickStart Development System..................................................94
QuickStart-PLUS Development System..................................94
Timing Specifications.....................................................................95
Outline Dimensions......................................................................104
Ordering Guide.........................................................................105
REVISION HISTORY
6/04—Changed from Rev. 0 to Rev. A Changes to Figure 5.........................................................................17
Changes to Figure 6.........................................................................18
Changes to Figure 7.........................................................................19
Changes to Table 5..........................................................................24
Changes to Table 24........................................................................41
Changes to Table 25........................................................................43
Changes to Table 26........................................................................44
Changes to Table 27........................................................................45
Changes to User Download Mode Section..................................50
Added Figure 51 and Renumbered Subsequent Figures............50
Edits to the DACH/DACL Data Registers Section.....................53
Changes to Table 34........................................................................56
Added SPIDAT: SPI Data Register Section..................................65
Changes to Table 42........................................................................67
Changes to Table 43........................................................................68
Changes to Table 44........................................................................69
Changes to Table 45........................................................................71
Changes to Table 50........................................................................75
Changes to Timer/Counter 0 and 1 Data Registers Section......76
Changes to Table 54........................................................................80
Added the SBUF—UART Serial Port Data Register Section.....80
Addition to the Timer 3 Generated Baud Rates Section............83
Added Table 57 and Renumbered Subsequent Tables................84
Changes to Table 61........................................................................86
4/04—Revision 0: Initial Version SPECIFICATIONS1 AVDD = 2.7 V to 3.6 V or 4.75 V to 5.25 V, DVDD = 2.7 V to 3.6 V or 4.75 V to 5.25 V, REFIN(+) = 2.5 V, REFIN(–) = AGND; AGND =
DGND = 0 V; XTAL1/XTAL2 = 32.768 kHz crystal; all specifications TMIN to TMAX, unless otherwise noted. Input buffer on for primary
ADC, unless otherwise noted. Core speed = 1.57 MHz (default CD = 3), unless otherwise noted.
Table 1. Footnotes at end of table.
