ADT7518ARQZ-REEL ,SPI/I2C Compatible, Temperature Sensor, 4-Channel ADC and Quad Voltage Output DACSPECIFICATIONS Table 1. Temperature range is as follows: A version: –40°C to +120°C. VDD = 2.7 V t ..
ADT7519ARQ ,SPI/I2C Compatible, Temperature Sensor, 4-Channel ADC and Quad Voltage Output DACCharacteristics........ 6 Function Description—Voltage Output....... 20 Functional Block Diagram .. ..
ADT7519ARQZ ,SPI/I2C Compatible, Temperature Sensor, 4-Channel ADC and Quad Voltage Output DACapplications, including personal The ADT7516/ADT7517/ADT7519 provide two serial interface computers ..
ADT7519ARQZ-REEL ,SPI/I2C Compatible, Temperature Sensor, 4-Channel ADC and Quad Voltage Output DACSpecifications subject to change without notice. No license is granted by implication www.analog.c ..
ADT7519ARQZ-REEL7 ,SPI/I2C Compatible, Temperature Sensor, 4-Channel ADC and Quad Voltage Output DACCharacteristics ....... 13 SMBus Alert Response 43 Theory of Operation ....... 19 Outline Dimension ..
ADT75ARMZ-REEL , -1°C Accurate, 12-Bit Digital Temperature Sensor
AM2716B , 2048 X 8 - BIT / 4096 X 8 - BIT EPROM
AM2716B-100DC , 2048 X 8 - BIT / 4096 X 8 - BIT EPROM
AM2716B-100DI , 2048 X 8 - BIT / 4096 X 8 - BIT EPROM
AM2716B-105DC , 2048 X 8 - BIT / 4096 X 8 - BIT EPROM
AM2716B-105DI , 2048 X 8 - BIT / 4096 X 8 - BIT EPROM
AM2716B-150DC , 2048 X 8 - BIT / 4096 X 8 - BIT EPROM
ADT7518ARQZ-REEL
SPI/I2C Compatible, Temperature Sensor, 4-Channel ADC and Quad Voltage Output DAC
SPI/I2C Compatible, Temperature Sensor,
4-Channel ADC and Quad Voltage Output DAC
Rev. A
FEATURES
Four 8-bit DACs
Buffered voltage output
Guaranteed monotonic by design over all codes
10-bit temperature-to-digital converter
10-bit 4-channel ADC
DC input bandwidth
Input range: 0 V to 2.25 V
Temperature range: –40°C to +120°C
Temperature sensor accuracy of typ: ±0.5°C
Supply range: 2.7 V to 5.5 V
DAC output range: 0 V to 2 VREF
Power-down current: 1 µA
Internal 2.25 VREF option
Double-buffered input logic
Buffered reference input
Power-on reset to 0 V DAC output
Simultaneous update of outputs (LDAC function)
On-chip rail-to-rail output buffer amplifier
SPI®
, I2C®
, QSPI™, MICROWIRE™, and DSP-compatible
4-wire serial interface
SMBus packet error checking (PEC)-compatible
16-lead QSOP package
APPLICATIONS
Portable battery-powered instruments
Personal computers
Smart battery chargers
Telecommunications systems
Electronic text equipment
Domestic appliances
Process control
PIN CONFIGURATION
VOUT-BVOUT-C
VOUT-AVOUT-D
VREF-INAIN4SCL/SCLK
GNDSDA/DIN
VDDDOUT/ADD
D+/AIN1INT/INT
D–/AIN2LDAC/AIN304879-001
Figure 1.
GENERAL DESCRIPTION The ADT75181 combines a 10-bit temperature-to-digital
converter, a 10-bit 4-channel ADC, and a quad 8-bit DAC, in a
16-lead QSOP package. The part also includes a band gap
temperature sensor and a 10-bit ADC to monitor and digitize
the temperature reading to a resolution of 0.25°C.
The ADT7518 operates from a single 2.7 V to 5.5 V supply. The
input voltage range on the ADC channels is 0 V to 2.25 V, and
the input bandwidth is dc. The reference for the ADC channels
is derived internally. The output voltage of the DAC ranges
from 0 V to VDD, with an output voltage settling time of 7 ms
typical.
The ADT7518 provides two serial interface options: a 4-wire
serial interface that is compatible with SPI, QSPI, MICROWIRE,
and DSP interface standards, and a 2-wire SMBus/I2C interface.
It features a standby mode that is controlled through the serial
interface.
The reference for the four DACs is derived either internally or
from a reference pin. The outputs of all DACs may be updated
simultaneously using the software LDAC function or the exter-
nal LDAC pin. The ADT7518 incorporates a power-on reset
circuit, which ensures that the DAC output powers up to 0 V
and remains there until a valid write takes place.
The ADT7518’s wide supply voltage range, low supply current,
and SPI-/I2C-compatible interface make it ideal for a variety of
applications, including personal computers, office equipment,
and domestic appliances.
It is recommended that new designs use the ADT7519 rather
than the ADT7518. The ADT7518’s internal and external temp-
erature accuracy spec is only valid when not using the internal
reference for the on-chip DAC. The ADT7519 does not have
this limitation.
1 Protected by the following U.S. Patent Numbers: 6,169,442; 5,867,012;
5,764174. Other patents pending.
TABLE OF CONTENTS Specifications.....................................................................................3
DAC AC Characteristics..............................................................6
Functional Block Diagram..............................................................7
Absolute Maximum Ratings............................................................8
ESD Caution..................................................................................8
Pin Configuration and Functional Descriptions..........................9
Terminology....................................................................................10
Typical Performance Characteristics...........................................12
Theory of Operation......................................................................17
Power-Up Calibration................................................................17
Conversion Speed.......................................................................17
Function Description—Voltage Output..................................18
Functional Description—Analog Inputs.................................20
ADC Transfer Function.............................................................21
Functional Description—Measurement..................................22
ADT7518 Registers....................................................................25
Serial Interface............................................................................33
SMBus Alert Response...............................................................38
Outline Dimensions.......................................................................40
Ordering Guide..........................................................................40
REVISION HISTORY
8/04—Data Sheet Changed from Rev. 0 to Rev. A Updated Format......................................................................Universal
Separate ADT7518 from
ADT7516/ADT7517/ADT7518 Data Sheet........................Universal
Change to Equation.............................................................................25
7/03—Revision 0: Initial Version SPECIFICATIONS
Table 1. Temperature range is as follows: A version: –40°C to +120°C. VDD = 2.7 V to 5.5 V, GND = 0 V, REFIN = 2.25 V, unless
otherwise noted.
See the section. Terminology
2 DC specifications are tested with the outputs unloaded. Linearity is tested using a reduced code range: ADT7518 (Code 8 to 255).
4 Guaranteed by design and characterization, not production tested. Round robin is the continuous sequential measurement of the following channels: VDD, internal temperature, external temperature (AIN1, AIN2), AIN3, and AIN4.
6 The temperature accuracy specifications are valid when the internal reference is not being used by the on-chip DAC. For new designs, the ADT7519 is recommended
as it does not have this limitation.
7 For the amplifier output to reach its minimum voltage, the offset error must be negative. For the amplifier output to reach its maximum voltage (VREF = VDD), the offset
plus gain error must be positive.
8 The SDA and SCL timing is measured with the input filters turned on to meet the fast-mode I2C specification. Switching off the input filters improves the transfer rate
but has a negative effect on the EMC behavior of the part.
9 Guaranteed by design, not production tested. All input signals are specified with tr = tf = 5 ns (10% to 90% of VDD), and timed from a voltage level of 1.6 V.
11 Measured with the load circuit shown in Figure 4. The IDD specification is valid for all DAC codes and full-scale analog input voltages. Interface inactive. All DACs and ADCs active. Load currents excluded.
DAC AC CHARACTERISTICS1
Table 2. VDD = 2.7 V to 5.5 V, RL = 4.7 kΩ to GND; CL = 200 pF to GND; 4.7 kΩ to VDD; all specifications TMIN to TMAX, unless
otherwise noted. Guaranteed by design and characterization, not production tested.
2 See the section. Terminology @ 25°C.
SCL
SDADATA IN04879-002
Figure 2. I2C Bus Timing Diagram
SCLK
DIN
DOUT04879-003
Figure 3. SPI Bus Timing Diagram
200µAIOH
1.6VTO OUTPUT
PINCL
50pF
200µAIOL04879-004
Figure 4. Load Circuit for Access Time and Bus Relinquish Time
VDD
TO DAC
FUNCTIONAL BLOCK DIAGRAM D+/AIN1D–/AIN2LDAC/AIN3AIN4
SDA
SCL
GND
VDD
ADD
LDAC/AIN3
VREF-IN
VOUT-A
VOUT-B
VOUT-C
VOUT-D
INT/INTFigure 6.
ABSOLUTE MAXIMUM RATINGS
Table 3.
Table 4. I2C Address Selection Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
1 Values relate to package being used on a 4-layer board. Junction-to-case resistance is applicable to components featuring a
preferential flow direction, e.g., components mounted on a heat sink.
Junction-to-ambient resistance is more useful for air cooled PCB-mounted
components.
ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
PIN CONFIGURATION AND FUNCTIONAL DESCRIPTIONS
VOUT-BVOUT-C
VOUT-AVOUT-D
VREF-INAIN4SCL/SCLK
GNDSDA/DIN
VDDDOUT/ADD
D+/AIN1INT/INT
D–/AIN2LDAC/AIN304879-007
Figure 7. Pin Configuration QSOP
Table 5. Pin Function Descriptions TERMINOLOGY
Relative Accuracy Relative accuracy or integral nonlinearity (INL) is a measure of
the maximum deviation, in LSBs, from a straight line passing
through the endpoints of the transfer function. Typical INL
versus code plots can be seen in Figure 10, Figure 11, and
Figure 12.
Differential Nonlinearity Differential nonlinearity (DNL) is the difference between the
measured change and the ideal 1 LSB change between any two
adjacent codes. A specified differential nonlinearity of ±0.9 LSB
maximum ensures monotonicity. Typical DAC DNL versus code
plots can be seen in Figure 13, Figure 14, and Figure 15.
Total Unadjusted Error (TUE) Total unadjusted error is a comprehensive specification that
includes the sum of the relative accuracy error, gain error, and
offset error under a specified set of conditions.
Offset Error This is a measure of the offset error of the DAC and the output
amplifier (see Figure 8 and Figure 9). It can be negative or
positive, and it is expressed in mV.
Offset Error Match This is the difference in offset error between any two channels.
Gain Error This is a measure of the span error of the DAC. It is the
deviation in slope of the actual DAC transfer characteristic
from the ideal expressed as a percentage of the full-scale range.
Gain Error Match This is the difference in gain error between any two channels.
Offset Error Drift This is a measure of the change in offset error with changes in
temperature. It is expressed in (ppm of full-scale range)/°C.
Gain Error Drift This is a measure of the change in gain error with changes in
temperature. It is expressed in (ppm of full-scale range)/°C.
Long Term Temperature Drift This is a measure of the change in temperature error over time.
It is expressed in °C. The concept of long-term stability has been
used for many years to describe the amount an IC’s parameter
shifts during its lifetime. This is a concept that has typically
been applied to both voltage references and monolithic temp-
erature sensors. Unfortunately, integrated circuits cannot be
evaluated at room temperature (25°C) for 10 years or so to
determine this shift. Manufacturers perform accelerated lifetime
testing of integrated circuits by operating ICs at elevated temp-
eratures (between 125°C and 150°C) over a shorter period
increase in rates of reaction within the semiconductor material.
DC Power Supply Rejection Ratio (PSRR) This indicates how the output of the DAC is affected by changes
in the supply voltage. PSRR is the ratio of the change in VOUT to
a change in VDD for full-scale output of the DAC. It is measured
in dB. VREF is held at 2 V and VDD is varied ±10%.
DC Crosstalk This is the dc change in the output level of one DAC in response
to a change in the output of another DAC. It is measured with a
full-scale output change on one DAC while monitoring another
DAC. It is expressed in µV.
Reference Feedthrough This is the ratio of the amplitude of the signal at the DAC out-
put to the reference input when the DAC output is not being
updated (i.e., LDAC is high). It is expressed in dB.
Channel-to-Channel Isolation This is the ratio of the amplitude of the signal at the output of
one DAC to a sine wave on the reference input of another DAC.
It is measured in dB.
Major-Code Transition Glitch Energy Major-code transition glitch energy is the energy of the impulse
injected into the analog output when the code in the DAC
register changes state. It is normally specified as the area of the
glitch in nV-s and is measured when the digital code is changed
by 1 LSB at the major carry transition (011...1 to 100...00 or
100...00 to 011...11).
Digital Feedthrough Digital feedthrough is a measure of the impulse injected into
the analog output of a DAC from the digital input pins of the
device but is measured when the DAC is not being written to. It
is specified in nV-s and is measured with a full-scale change on
the digital input pins, i.e., from all 0s to all 1s or vice versa.
Digital Crosstalk This is the glitch impulse transferred to the output of one DAC
at midscale in response to a full-scale code change (all 0s to all
1s and vice versa) in the input register of another DAC. It is
measured in standalone mode and is expressed in nV-s.
Analog Crosstalk This is the glitch impulse transferred to the output of one DAC
due to a change in the output of another DAC. It is measured by
loading one of the input registers with a full-scale code change
(all 0s to all 1s and vice versa) while keeping LDAC high. Then
pulse LDAC low and monitor the output of the DAC whose
digital code was not changed. The area of the glitch is expressed
in nV-s.
DAC-to-DAC Crosstalk This is the glitch impulse transferred to the output of one DAC
due to a digital code change and subsequent output change of
another DAC. This includes both digital and analog crosstalk. It
is measured by loading one of the DACs with a full-scale code
change (all 0s to all 1s and vice versa) with LDAC low and
monitoring the output of another DAC. The energy of the glitch
is expressed in nV-s.
Multiplying Bandwidth The amplifiers within the DAC have a finite bandwidth. The
multiplying bandwidth is a measure of this. A sine wave on the
reference (with full-scale code loaded to the DAC) appears on
the output. The multiplying bandwidth is the frequency at
which the output amplitude falls to 3 dB below the input.
Total Harmonic Distortion This is the difference between an ideal sine wave and its atten-
uated version using the DAC. The sine wave is used as the
reference for the DAC, and the THD is a measure of the
harmonics present on the DAC output, expressed in dB.
Round Robin This term is used to describe the ADT7518 cycling through the
available measurement channels in sequence, taking a measure-
ment on each channel.
DAC Output Settling Time This is the time required, following a prescribed data change, for
the output of a DAC to reach and remain within ±0.5 LSB of the
final value. A typical prescribed change is from 1/4 scale to
3/4 scale.
AMPLIFIERFOOTROOM
NEGATIVEOFFSETERROR+
OUTPUTVOLTAGE
NEGATIVEOFFSETERROR
IDEAL04879-008
Figure 8. DAC Transfer Function with Negative Offset
+OUTPUTVOLTAGE
POSITIVEOFFSETERRORDAC CODEFULL SCALE04879-009
Figure 9. DAC Transfer Function with Positive Offset (VREF = VDD)
TYPICAL PERFORMANCE CHARACTERISTICS
INL E
RROR (LS
DAC CODEFigure 10. ADT7518 Typical DAC INL Plot
DNL E
RROR (LS50100150200250
DAC CODEFigure 11. ADT7518 Typical DAC DNL Plot
VREF (V)
RROR (LS
0.25Figure 12. ADT7518 DAC INL and DNL Error vs, VREF
TEMPERATURE (°C)
RROR (LS
0.12Figure 13. ADT7518 DAC INL Error and DNL Error vs. Temperature
TEMPERATURE (°C)
RROR (LS
–0.2Figure 14. DAC Offset Error and Gain Error vs. Temperature
RROR (LS
VDD (V)
4.55.05.5Figure 15. DAC Offset Error and Gain Error vs. VDD
DAC OUTP
UT (V
CURRENT (mA)6Figure 16. DAC VOUT Source and Sink Current Capability
TEMPERATURE (°C)
RROR (LS
–0.2Figure 17. Supply Current vs. DAC Code
VCC (V)
(mA)
1.95
Figure 18. Supply Current vs. Supply Voltage @ 25°C
VCC (V)
(mA)
Figure 19. Power-Down Current vs. Supply Voltage @ 25°C
TIME (µs)
DAC OUTP
UT (V
3.5Figure 20. DAC Half-Scale Settling (1/4 to 3/4 Scale Code Change)
DAC OUTP
UT (V
TIME (µs)
0.2Figure 21. Exiting Power-Down to Midscale
TIME (µs)
DAC OUTP
UT (V
0.4695Figure 22. ADT7518 DAC Major Code Transition Glitch Energy;
0...11 to 100...00
TIME (µs)
DAC OUTP
UT (V
0.4725Figure 23. ADT7518 DAC Major Code Transition Glitch Energy;
100…00 to 011…11
FULL-S
CALE
RROR (mV
VREF (V)Figure 24. DAC Full-Scale Error vs. VREF
TIME (µs)
2.328DAC OUTP
UT (V
Figure 25. DAC-to-DAC Crosstalk
ADC CODE
INL E
RROR (LS
0.8
Figure 26. ADC INL with Ref = VDD (3.3 V)
AC P
RR (dB)
FREQUENCY (kHz)
Figure 27. PSRR vs. Supply Ripple Frequency
TEMPERATURE (°C)
RATURE
RROR (
1.0Figure 28. Internal Temperature Error @ 3.3 V and 5 V
RROR (LS
TEMPERATURE (°C)406080100120
Figure 29. ADC Offset Error and Gain Error vs. Temperature
VDD (V)
RROR (LS
2.73.13.53.94.34.75.15.5
Figure 30. ADC Offset Error and Gain Error vs. VDD
RATURE
RROR (
PCB LEAKAGE RESISTANCE (MΩ)405060708090100Figure 31. External Temperature Error vs. PCB Leakage Resistance
RATURE
RROR (
CAPACITANCE (nF)35404550Figure 32. External Temperature Error vs. Capacitance between D+ and D–
RATURE
RROR (
°C)
NOISE FREQUENCY (Hz)100200300400500600Figure 33. External Temperature Error vs. Common-Mode Noise Frequency
RATURE
RROR (
NOISE FREQUENCY (MHz)
300400500600Figure 34. External Temperature Error vs. Differential-Mode Noise Frequency
NOISE FREQUENCY (Hz)100200300400500600
TEMPERATURE ERROR (
°C)
–0.6Figure 35. Internal Temperature Error vs. Power Supply Noise Frequency
RATURE
°C)
TIME (s)4050060Figure 36. Temperature Sensor Response to Thermal Shock
ATTE
NUATION (dB)
–10101001k10k100k1M10M
FREQUENCY (Hz)Figure 37. DAC Multiplying Bandwidth (Small Signal Frequency Response)
THEORY OF OPERATIONDirectly after the power-up calibration routine, the ADT7518
goes into idle mode. In this mode, the device is not performing
any measurements and is fully powered up. All four DAC
outputs are at 0 V.
To begin monitoring, write to the Control Configuration 1
register (Address 18h) and set Bit C0 = 1. The ADT7518 goes
into its power-up default measurement mode, which is round
robin. The device then to take measurements on the VDD chan-
nel, internal temperature sensor channel, external temperature
sensor channel, or AIN1 and AIN2, AIN3, and finally AIN4.
Once it finishes taking measurements on the AIN4 channel, the
device immediately loops back to start taking measurements on
the VDD channel and repeats the same cycle as before. This loop
continues until the monitoring is stopped by resetting Bit C0 of
the Control Configuration 1 register to 0. It is also possible to
continue monitoring as well as switching to single-channel
mode by writing to the Control Configuration 2 register
(Address 19h) and setting Bit C4 = 1. Further explanation of
the single-channel and round robin measurement modes is
given in later sections.
All measurement channels have averaging enabled on them on
power-up. Averaging forces the device to take an average of 16
readings before giving a final measured result. To disable aver-
aging and consequently decrease the conversion time by a factor
of 16, set Bit C5 = 1 in the Control Configuration 2 register.
There are four single-ended analog input channels on the
ADT7518: AIN1 to AIN4. AIN1 and AIN2 are multiplexed with
the external temperature sensor terminals D+ and D–. Bits C1
and C2 of the Control Configuration 1 register (Address 18h)
are used to select between AIN1/AIN2 and the external
temperature sensor. The input range on the analog input
channels is dependent on whether the ADC reference used is
the internal VREF or VDD. To meet linearity specifications, it is
recommended that the maximum VDD value is 5 V. Bit C4 of the
Control Configuration 3 register is used to select between the
internal reference or VDD as the analog inputs’ ADC reference.
Controlling the DAC outputs can be done by writing to the
DACs’ MSB and LSB registers (Addresses 10h to 17h). The
power-up default setting is to have a low going pulse on the
LDAC pin (Pin 9) controlling the updating of the DAC outputs
from the DAC registers. Alternatively, one can configure the
updating of the DAC outputs to be controlled by means other
than the LDAC pin by setting Bit C3 = 1 of the Control Config-
uration 3 register (Address 1Ah). The DAC Configuration
register (Address 1Bh) and the LDAC Configuration register
(Address 1Ch) can now be used to control the DAC updating.
and DAC B outputs can be configured to give a voltage output
proportional to the temperature of the internal and external
temperature sensors, respectively.
The dual serial interface defaults to the I2C protocol on power-
up. To select and lock in the SPI protocol, follow the selection
process as described in the Serial Interface Selection section.
The I2C protocol cannot be locked in, while the SPI protocol is
automatically locked in on selection. The interface can be
switched back to be I2C on selection when the device is powered
off and on. When using I2C, the CS pin should be tied to either
VDD or GND.
There are a number of different operating modes on the
ADT7518 devices and all of them can be controlled by the
configuration registers. These features consist of enabling and
disabling interrupts, polarity of the INT/INT pin, enabling and
disabling the averaging on the measurement channels SMBus
timeout and software reset.
POWER-UP CALIBRATION It is recommended that no communication to the part be ini-
tiated until approximately 5 ms after VDD has settled to within
10% of its final value. It is generally accepted that most systems
take a maximum of 50 ms to power up. Power-up time is
directly related to the amount of decoupling on the voltage
supply line.
During the 5 ms after VDD has settled, the part is performing a
calibration routine. Any communication to the device during
calibration will interrupt this routine, and could cause erro-
neous temperature measurements. If it is not possible to have
VDD at its nominal value by the time 50 ms has elapsed or if
communication to the device has started prior to VDD settling, it
is recommended that a measurement be taken on the VDD chan-
nel before a temperature measurement is taken. The VDD
measurement is used to calibrate out any temperature measure-
ment error due to different supply voltage values.
CONVERSION SPEED The internal oscillator circuit used by the ADC has the capa-
bility to output two different clock frequencies. This means that
the ADC is capable of running at two different speeds when
doing a conversion on a measurement channel. Thus, the time
taken to perform a conversion on a channel can be reduced by
setting Bit C0 of the Control Configuration 3 register (Address
1Ah). This increases the ADC clock speed from 1.4 kHz to 22
kHz. At the higher clock speed, the analog filters on the D+ and
D– input pins (external temperature sensor) are switched off.
This is why the power-up default setting is to have the ADC
working at the slow speed. The typical times for fast and slow
The ADT7518 powers up with averaging on. This means every
channel is measured 16 times and internally averaged to reduce
noise. The conversion time can also be sped up by turning off
the averaging. This is done by setting Bit C5 of the Control
Configuration 2 register (Address 19h) to 1.
FUNCTION DESCRIPTION—VOLTAGE OUTPUT
Digital-to-Analog Converters The ADT7518 has four resistor string DACs fabricated on a
CMOS process with resolutions of 12, 10, and 8 bits, respec-
tively. They contain four output buffer amplifiers and are
written to via I2C serial interface or SPI serial interface. See
the Serial Interface section for more information.
The ADT7518 operates from a single supply of 2.7 V to 5.5 V,
and the output buffer amplifiers provide rail-to-rail output
swing with a slew rate of 0.7 V/µs. All four DACs share a com-
mon reference input, VREF-IN. The reference input is buffered to
draw virtually no current from the reference source because it
offers the source a high impedance input. The devices have a
power-down mode in which all DACs may be turned off
completely with a high impedance output.
Each DAC output will not be updated until it receives the
LDAC command. Therefore, while the DAC registers would
have been written to with a new value, this value will not be
represented by a voltage output until the DACs have received
the LDAC command. Reading back from any DAC register
prior to issuing an LDAC command will result in the digital
value that corresponds to the DAC output voltage. Thus, the
digital value written to the DAC register cannot be read back
until after the LDAC command has been initiated. This LDAC
command can be given by either pulling the LDAC pin low
(falling edge loads DACs), setting up Bits D4 and D5 of the
DAC configuration register (Address 1Bh), or using the LDAC
register (Address 1Ch).
When using the LDAC pin to control the DAC register loading,
the low going pulse width should be 20 ns minimum. The
LDAC pin has to go high and low again before the DAC
registers can be reloaded.
Digital-to-Analog Section The architecture of one DAC channel consists of a resistor
string DAC followed by an output buffer amplifier. The voltage
at the VREF-IN pin or the on-chip reference of 2.25 V provides
the reference voltage for the corresponding DAC. Figure 38
shows a block diagram of the DAC architecture. Since the input
coding to the DAC is straight binary, the ideal output voltage is
given by
REF
OUTVV2=
where:
D = decimal equivalent of the binary code that is loaded to the
DAC register:
0 to 255 for ADT7518 (8 bits)
N = DAC resolution
Resistor String The resistor string section is shown in Figure 39. It is simply a
string of resistors, each of approximately 603 Ω. The digital
code loaded to the DAC register determines at which node on
the string the voltage is tapped off to be fed into the output
amplifier. The voltage is tapped off by closing one of the
switches connecting the string to the amplifier. Because it is a
string of resistors, it is guaranteed monotonic.
OUTPUT BUFFERAMPLIFIER
GAIN MODE(GAIN = 1 OR 2)
REFERENCEBUFFER
INT VREF
VREF-IN04879-038
Figure 38. Single DAC Channel Architecture
TO OUTPUTAMPLIFIER04879-039
Figure 39. Resistor String
2.25VINTERNAL VREF
VREF-IN04879-040
DAC Reference Inputs VREF and this can be increased to 0 V to 2 VREF. Increasing the
output voltage span to 2 VREF can be done by setting D0 = 1 for
DAC A (internal temperature sensor) and D1 = 1 for DAC B
(external temperature sensor) in the DAC configuration register
(Address 1Bh).
There is an input reference pin for the DACs. This reference
input is buffered (see Figure 40).
The advantage with the buffered input is the high impedance it
presents to the voltage source driving it. The user can have an
external reference voltage as low as 1 V and as high as VDD. The
restriction of 1 V is due to the footroom of the reference buffer.
The output voltage is capable of tracking a maximum temp-
erature range of –128°C to +127°C, but the default setting is
–40°C to +127°C. If the output voltage range is 0 V to VREF-IN
(VREF-IN = 2.25 V), then this corresponds to 0 V representing
–40°C, and 1.48 V representing +127°C. This, of course, will
give an upper deadband between 1.48 V and VREF.
The LDAC configuration register controls the option to select
between internal and external voltage references. The default
setting is for external reference selected.
Output Amplifier The internal and external analog temperature offset registers
can be used to vary this upper deadband and, consequently, the
temperature that 0 V corresponds to. Table 6 and Table 7 give
examples of how this is done using a DAC output voltage span
of VREF and 2 VREF, respectively. Simply write in the temperature
value, in twos complement format, at which 0 V is to start. For
example, if using the DAC A output and 0 V to start at –40°C,
program D8h into the internal analog temperature offset reg-
ister (Address 21h). This is an 8-bit register and has a temp-
erature offset resolution of only 1°C for all device models. Use
the formulas following the tables to determine the value to
program into the offset registers.
The output buffer amplifier can generate output voltages to
within 1 mV of either rail. Its actual range depends on the value
of VREF, gain, and offset error.
If a gain of 1 is selected (Bits 0 to 3 of the DAC configuration
register = 0), the output range is 0.001 V to VREF.
If a gain of 2 is selected (Bits 0 to 3 of the DAC configuration
register = 1), the output range is 0.001 V to 2 VREF. Because of
clamping, however, the maximum output is limited to VDD −
0.001 V.
The output amplifier can drive a load of 4.7 kΩ to GND or VDD,
in parallel with 200 pF to GND or VDD (see Figure 5). The
source and sink capabilities of the output amplifier can be seen
in the plot of Figure 16.
Table 6. Thermal Voltage Output (0 V to VREF) The slew rate is 0.7 V/µs with a half-scale settling time to
±0.5 LSB (at 8 bits) of 6 µs.
Thermal Voltage Output The ADT7518 can output voltages that are proportional to
temperature. DAC A output can be configured to represent the
temperature of the internal sensor while DAC B output can be
configured to represent the external temperature sensor. Bits C5
and C6 of the Control Configuration 3 register select the temp-
erature proportional output voltage. Each time a temperature
measurement is taken, the DAC output is updated. The output
resolution for the ADT7518 is 8 bits with a 1°C change corres-
ponding to 1 LSB change. The default output range is 0 V to
∗ Upper deadband has been reached. DAC output is not capable of
increasing. See Fig. ure 9
VOUT+
VOUT–
REMOTESENSINGTRANSISTOR(2N3906)
OPTIONAL CAPACITOR, UP TO3nF MAX. CAN BE ADDED TOIMPROVE HIGH FREQUENCYNOISE REJECTION IN NOISYENVIRONMENTS04879-041
DIODEINTERNALSENSETRANSISTORVDD
VOUT+
VOUT–04879-042
Figure 42. Top Level Structure of Internal Temperature Sensor
Table 7. Thermal Voltage Output (0 V to 2 VREF) * Upper deadband has been reached. DAC output is not capable of increasing.
See Figure 9.
Negative temperatures: 128Re=TempVdCodegisterOffset
where:
D7 of Offset Register Code is set to 1 for negative temperatures.
Example: ()58h d8812840Re==+−=CodegisterOffset
Since a negative temperature has been inserted into the
equation, DB7 (MSB) of the offset register code is set to 1.
Therefore 58h becomes D8h.
58h + DB7(1) = D8h
Positive temperatures:
Example:
Offset Register Code (d) = 10d = 0Ah
The following equation is used to work out the various
temperatures for the corresponding 8-bit DAC output: TempVLSBPOTempBit-1/8+
For example, if the output is 1.5 V, VREF-IN = 2.25 V, 8-bit DAC
has an LSB size = 2.25 V/256 = 8.79 x 10–3, and 0 V temperature
is at –128°C, then the resultant temperature is ()C°+=−+×÷−431281079.85.3
Figure 43 shows a graph of the DAC output versus temperature
for a VREF-IN = 2.25 V.
TEMPERATURE (°C)
DAC OUTP
UT (V
2.25Figure 43. DAC Output vs. Temperature VREF-IN = 2.25 V
FUNCTIONAL DESCRIPTION—ANALOG INPUTS
Single-Ended Inputs The ADT7518 offers four single-ended analog input channels.
The analog input range is from 0 V to 2.25 V, or 0 V to VDD. To
maintain the linearity specification, it is recommended that the
maximum VDD value be set at 5 V. Selection between the two
input ranges is done by Bit C4 of the Control Configuration 3
register (Address 1Ah). Setting this bit to 0 sets up the analog
input ADC reference to be sourced from the internal voltage
