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ADT7463ARQZ-R7 , dB COOL™ Remote Thermal Controller and Voltage Monitor
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ADT7463ARQ-ADT7463ARQ-REEL-ADT7463ARQ-REEL7-ADT7463ARQZ-ADT7463ARQZ-REEL
dBCOOL™ Thermal Management Controller and Voltage Monitor
COOL™ Remote ThermalController and Voltage Monitor
REV.C
FEATURES
Monitors up to 5 Supply Voltages
Controls and Monitors up to 4 Fan Speeds
1 On-Chip and 2 Remote Temperature Sensors
Monitors up to 6 Processor VID Bits
Dynamic TMIN Control Mode Optimizes System
Acoustics Intelligently
Automatic Fan Speed Control Mode Controls System
Cooling Based on Measured Temperature
Enhanced Acoustic Mode Dramatically Reduces User
Perception of Changing Fan Speeds
Thermal Protection Feature via THERM Output
Monitors Performance Impact of Intel® Pentium® 4
Processor Thermal Control Circuit via THERM Input
2-Wire and 3-Wire Fan Speed Measurement
Limit Comparison of All Monitored Values
Meets SMBus 2.0 Electrical Specifications
(Fully SMBus 1.1 Compliant)
APPLICATIONS
Low Acoustic Noise PCs
Networking and Telecommunications Equipment
FUNCTIONAL BLOCK DIAGRAM
GENERAL DESCRIPTION
The ADT7463 dBCOOL controller is a complete systems
monitor and multiple PWM fan controller for noise-sensitive
applications requiring active system cooling. It can monitor
12 V, 5 V, and 2.5 V CPU supply voltages, plus its own supply
voltage. It can monitor the temperature of up to two remote
sensor diodes, plus its own internal temperature. It can measure
and control the speed of up to four fans so that they operate at the
lowest possible speed for minimum acoustic noise. The automatic
fan speed control loop optimizes fan speed for a given temperature.
A unique dynamic TMIN control mode enables the system
thermals/acoustics to be intelligently managed. The effectiveness
of the system’s thermal solution can be monitored using the
THERM input. The ADT7463 also provides critical thermal
protection to the system using the bidirectional THERM pin
as an output to prevent system or component overheating.
*. Patent Nos. 6,188,189; 6,169,442; 6,097,239; 5,982,221; and 5,867,012. Other patents pending.
ADT7463–SPECIFICATIONS1, 2, 3, 4(TA = TMIN to TMAX, VCC = VMIN to VMAX, unless otherwise noted.)
ANALOG-TO-DIGITAL CONVERTER
(INCLUDING MUX AND ATTENUATORS)
ADT7463
DIGITAL INPUT CURRENT
SERIAL BUS TIMING
NOTESAll voltages are measured with respect to GND, unless otherwise specified.Typicals are at TA = 25°C and represent the most likely parametric norm.Logic inputs accept input high voltages up to VMAX even when the device is operating down to VMIN.Timing specifications are tested at logic levels of VIL = 0.8 V for a falling edge and VIH = 2.0 V for a rising edge.Guaranteed by design, not production tested.
Specifications subject to change without notice.
Figure 1. Diagram for Serial Bus Timing
ADT7463
ABSOLUTE MAXIMUM RATINGS*
Positive Supply Voltage (VCC) . . . . . . . . . . . . . . . . . . . . . 6.5 V
Voltage on +12VIN Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 V
Voltage on Any Other Input or Output Pin . . . . –0.3 V to +6.5 V
Input Current at Any Pin . . . . . . . . . . . . . . . . . . . . . . . ±5 mA
Package Input Current . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
Maximum Junction Temperature (TJ max) . . . . . . . . . . 150°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Lead Temperature, Soldering
IR Reflow Peak Temperature . . . . . . . . . . . . . . . . . . . 220°C
IR Reflow Peak Temperature for Pb-free . . . . . . . . . . 260°C
Lead Temperature (soldering 10 sec) . . . . . . . . . . . . . 300°C
ESD Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1500 V
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
THERMAL CHARACTERISTICS
24-Lead QSOP Package:
θJA = 105°C/W, θJC = 39°C/W.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection. Although the
ADT7463 features proprietary ESD protection circuitry, permanent damage may occur on devices
subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended
to avoid performance degradation or loss of functionality.
PIN CONFIGURATION
ORDERING GUIDE
*Z = Pb-free part.
PIN FUNCTION DESCRIPTIONS
4VCC
ADT7463
FUNCTIONAL DESCRIPTION
General Description
The ADT7463 is a complete systems monitor and multiple fan
controller for any system requiring monitoring and cooling. The
device communicates with the system via a serial system
management bus. The serial bus controller has an optional
address line for device selection (Pin 14), a serial data line
for reading and writing addresses and data (Pin 1), and an input
line for the serial clock (Pin 2). All control and programming
functions of the ADT7463 are performed over the serial bus. In
addition, two of the pins can be reconfigured as an SMBALERT
output to indicate out-of-limit conditions.
Measurement Inputs
The device has six measurement inputs, four for voltage and
two for temperature. It can also measure its own supply voltage
and can measure ambient temperature with its on-chip tempera-
ture sensor.
Pins 20 through 23 are analog inputs with on-chip attenuators,
configured to monitor 5 V, 12 V, 2.5 V, and the processor core
voltage (2.25 V input), respectively.
Power is supplied to the chip via Pin 4, and the system also
monitors VCC through this pin. In PCs, this pin is normally
connected to a 3.3 V standby supply. This pin can, however, be
connected to a 5 V supply and monitor it without overranging.
Remote temperature sensing is provided by the D1� and D2�
inputs, to which diode-connected, external temperature-sensing
transistors, such as a 2N3904 or CPU thermal diode, may be
connected.
The ADC also accepts input from an on-chip band gap tem-
perature sensor that monitors system ambient temperature.
Sequential Measurement
When the ADT7463 monitoring sequence is started, it cycles
sequentially through the measurement of analog inputs and the
temperature sensors. Measured values from these inputs are
stored in value registers. These can be read out over the serial
bus or can be compared with programmed limits stored in the
limit registers. The results of out-of-limit comparisons are stored
in the status registers, which can be read over the serial bus to
flag out-of-limit conditions.
Processor Voltage ID
Five digital inputs (VID0 to VID5—Pins 5 to 8, 19, and 21) read
the processor voltage ID code and store it in the VID register,
from which it can be read out by the management system over
the serial bus. The VID code monitoring function is compatible
with both VRM9.x and future VRM10 solutions. Additionally,
an SMBALERT can be generated to flag a change in VID code.
ADT7463 Address Selection
Pin 13 is the dual-function PWM3/ADDRESS ENABLE pin.Pin 13 is pulled low on power-up, the ADT7463 reads the
state of Pin 14 (TACH4/ADDRESS SELECT/ THERM pin) to
determine the ADT7463’s slave address. If Pin 13 is high on
power-up, then the ADT7463 defaults to the SMBus slave
Address 0x2E. This function is described in more detail later.
INTERNAL REGISTERS OF THE ADT7463
A brief description of the ADT7463’s principal internal registers
is given below. More detailed information on the function of
each register is given in Tables IV to XLII.
Configuration Registers
The configuration registers provide control and configuration of
the ADT7463, including alternate pinout functionality.
Address Pointer Register
This register contains the address that selects one of the other
internal registers. When writing to the ADT7463, the first byte
of data is always a register address, which is written to the
address pointer register.
Status Registers
These registers provide the status of each limit comparison and
are used to signal out-of-limit conditions on the temperature,
voltage, or fan speed channels. If Pin 10 or Pin 22 is con-
figured as SMBALERT, then this pin asserts low whenever a
status bit gets set.
Interrupt Mask Registers
These registers allow each interrupt status event to be masked
when Pin 10 or Pin 22 is configured as an SMBALERT output.
VID Register
The status of the VID0 to VID5 pins of the processor can read
from this register. VID code changes can also generate
SMBALERT interrupts.
Value and Limit Registers
The results of analog voltage inputs, temperature, and fan speed
measurements are stored in these registers, along with their
limit values.
Offset Registers
These registers allow each temperature channel reading to be
offset by a twos complement value written to these registers.
TMIN Registers
These registers program the starting temperature for each fan
under automatic fan speed control.
TRANGE Registers
These registers program the temperature-to-fan speed control
slope in automatic fan speed control mode for each PWM output.
Operating Point Registers
These registers define the target operating temperatures for each
thermal zone when running under dynamic TMIN control. This
function allows the cooling solution to adjust dynamically in
response to measured temperature and system performance.
Enhance Acoustics Registers
These registers allow each PWM output controlling fan to be
tweaked to enhance the system’s acoustics.
TPC 1.Remote Temperature Error
vs. Leakage Resistance
TPC 4.Local Temperature Error
vs. Actual Temperature
TPC 7.Supply Voltage vs.
Supply Current
TPC 2.Remote Temperature Error
vs. Capacitance between D+ and D–
TPC 5.Remote Temperature Error
vs. Power Supply Noise Frequency
TPC 8.Remote Temperature Error vs.
Differential Mode Noise Frequency
TPC 3.Remote Temperature Error
vs. Actual Temperature
TPC 6.Local Temperature Error vs.
Power Supply Noise Frequency
TPC 9.Remote Temperature Error vs.
Common-Mode Noise Frequency
ADT7463
Figure 2. Recommended Implementation
RECOMMENDED IMPLEMENTATION
Configuring the ADT7463 as in Figure 2 allows the systems
designer the following features:Six VID inputs (VID0 to VID5) for VRM10 support.Two PWM outputs for fan control of up to three fans
(the front and rear chassis fans are connected in parallel).Three TACH fan speed measurement inputs.VCC measured internally through Pin 4.CPU core voltage measurement (VCORE).2.5 V measurement input used to monitor CPU current
(connected to VCOMP output of ADP316x VRM controller).
This is used to determine CPU power consumption.5 V measurement input.VRM temperature uses local temperature sensor.CPU temperature measured using Remote 1 temperature
channel.Ambient temperature measured through Remote 2 temperature
channel.If not using VID5, this pin can be reconfigured as the 12V
monitoring input.Bidirectional THERM pin. Allows Intel Pentium 4 PROCHOT
monitoring and can function as an overtemperature THERM
output.SMBALERT system interrupt output.
See the AN-612 ADT7463 Configuration application note for more
information and register settings for all possible configurations
(/UploadedFiles/Application_Notes/408599520AN612_0.pdf).
SERIAL BUS INTERFACE
Control of the ADT7463 is carried out using the serial system
management bus (SMBus). The ADT7463 is connected to this
bus as a slave device, under the control of a master controller.
The ADT7463 has a 7-bit serial bus address. When the device
is powered up with Pin 13 (PWM3/ADDRESS ENABLE) high,
the ADT7463 has a default SMBus address of 0101110 or
0x2E. The read/write bit must be added to get the 8-bit address. If
more than one ADT7463 is used in a system, then each ADT7463
should be placed in address select mode by strapping Pin 13 low on
power-up. The logic state of Pin 14 then determines the device’s
SMBus address. The logic of these pins is sampled upon power-up.
The device address is sampled and latched on the first valid
SMBus transaction, more precisely on the low-to-high transition
at the beginning of the 8th SCL pulse, when the serial bus address
byte matches the selected slave address. The selected slave address
is chosen using the address enable/address select pins. Any
attempted changes in the address will have no effect after this.
Table I. Address Select Mode
Figure 3. Default SMBus Address = 0x2E
Figure 4. SMBus Address = 0x2C (Pin 14 = 0)
The ability to make hardwired changes to the SMBus slave
address allows the user to avoid conflicts with other devices sharing
the same serial bus, for example, if more than one ADT7463 is
used in a system.
The serial bus protocol operates as follows:The master initiates data transfer by establishing a START
condition, defined as a high-to-low transition on the serial
data line SDA while the serial clock line SCL remains high.
This indicates that an address/data stream will follow. All
slave peripherals connected to the serial bus respond to the
START condition and shift in the next eight bits, consisting
of a 7-bit address (MSB first) plus a R/W bit, which deter-
mines the direction of the data transfer, i.e., whether data
will be written to or read from the slave device.
Figure 5. SMBus Address = 0x2D (Pin 14 = 1)
Figure 6. Unpredictable SMBus Address if Pin 13
Is Unconnected
The peripheral whose address corresponds to the transmitted
address responds by pulling the data line low during the low
period before the ninth clock pulse, known as the Acknowl-
edge Bit. All other devices on the bus now remain idle while
the selected device waits for data to be read from or written
to it. If the R/W bit is a 0, then the master writes to the
slave device. If the R/W bit is a 1, the master reads from
the slave device.
ADT7463
Figure 7. Writing a Register Address to the Address Pointer Register, Then Writing Data to the Selected RegisterData is sent over the serial bus in sequences of nine clock
pulses, eight bits of data followed by an Acknowledge Bit
from the slave device. Transitions on the data line must
occur during the low period of the clock signal and remain
stable during the high period, as a low-to-high transition
when the clock is high may be interpreted as a STOP signal.
The number of data bytes that can be transmitted over the
serial bus in a single READ or WRITE operation is limited
only by what the master and slave devices can handle.When all data bytes have been read or written, stop conditions
are established. In WRITE mode, the master pulls the data line
high during the tenth clock pulse to assert a STOP condition.
In READ mode, the master device overrides the acknowledge
bit by pulling the data line high during the low period before
the ninth clock pulse. This is known as NoAcknowledge.
The master then takes the data line low during the low pe-
riod before the 10th clock pulse, and then high during the
10th clock pulse to assert a STOP condition.
Any number of bytes of data can be transferred over the serial
bus in one operation, but it is not possible to mix read and write
in one operation because the type of operation is determined at
the beginning and cannot subsequently be changed without
starting a new operation.
In the case of the ADT7463, write operations contain either one
or two bytes, and read operations contain one byte and perform
the following functions.
To write data to one of the device data registers or read data from
it, the address pointer register must be set so that the correct data
register is addressed, then data can be written into that register
or read from it. The first byte of a write operation always contains
an address that is stored in the address pointer register. If data
is to be written to the device, then the write operation containssecond data byte that is written to the register selected by the
address pointer register.
This is illustrated in Figure 7. The device address is sent over
the bus followed by R/W being set to 0. This is followed by two
data bytes. The first data byte is the address of the internal data
register to be written to, which is stored in the address pointer
register. The second data byte is the data to be written to the
internal data register.
When reading data from a register, there are two possibilities:If the ADT7463’s address pointer register value is unknown
or not the desired value, it is first necessary to set it to the
correct value before data can be read from the desired data
register. This is done by performing a write to the ADT7463
as before, however, only the data byte is sent and this con-
tains the register address. This is shown in Figure 8.
A read operation is then performed consisting of the serial
bus address, R/W bit set to 1, followed by the data byte read
from the data register. This is shown in Figure 9.If the address pointer register is already at the desired address,
data can be read from the corresponding data register without
first writing to the address pointer register, so Figure 8 can
be omitted.
NotesIt is possible to read a data byte from a data register without
first writing to the address pointer register if the address
pointer register is already at the correct value. However, it is
not possible to write data to a register without writing to the
address pointer register because the first data byte of a write
is always written to the address pointer register.In Figures 7 to 9, the serial bus address is shown as the
default value 01011(A1)(A0), where A1 and A0 are set by
the address select mode function previously defined.In addition to supporting the Send Byte and Receive Byte
protocols, the ADT7463 also supports the Read Byte protocol
(see System Management Bus specifications Rev. 2.0 for
more information).If it is required to perform several read or write operations in
succession, the master can send a repeat start condition
instead of a stop condition to begin a new operation.
Figure 8. Writing to the Address Pointer Register Only
SCL
SDA
NO ACK. BY
MASTER
STOP BY
MASTER
START BY
MASTERFRAME 1
SERIAL BUS ADDRESS
BYTE
FRAME 2
DATA BYTE FROM ADT7463 1
ACK. BY
ADT7463
Figure 9. Reading Data from a Previously Selected Register
ADT7463
ADT7463 WRITE OPERATIONS
The SMBus specification defines several protocols for different
types of read and write operations. The ones used in the ADT7463
are discussed below. The following abbreviations are used in the
diagrams:
S – STARTSTOPREAD
W –WRITEACKNOWLEDGE–NO ACKNOWLEDGE
The ADT7463 uses the following SMBus write protocols.
Send Byte
In this operation, the master device sends a single command
byte to a slave device as follows:The master device asserts a start condition on SDA.The master sends the 7-bit slave address followed by the
write bit (low).The addressed slave device asserts ACK on SDA.The master sends a command code.The slave asserts ACK on SDA.The master asserts a stop condition on SDA and the
transaction ends.
For the ADT7463, the send byte protocol is used to write a
register address to RAM for a subsequent single byte read from
the same address. This is illustrated in Figure 10.
Figure 10. Setting a Register Address for Subsequent Read
If it is required to read data from the register immediately after
setting up the address, the master can assert a repeat start con-
dition immediately after the final ACK and carry out a single
byte read without asserting an intermediate stop condition.
Write Byte
In this operation, the master device sends a command byte and
one data byte to the slave device as follows:The master device asserts a start condition on SDA.The master sends the 7-bit slave address followed by the
write bit (low).The addressed slave device asserts ACK on SDA.The master sends a command code.The slave asserts ACK on SDA.The master sends a data byte.The slave asserts ACK on SDA.The master asserts a stop condition on SDA to end the
transaction.
This is illustrated in Figure 11.
Figure 11. Single Byte Write to a Register
ADT7463 READ OPERATIONS
The ADT7463 uses the following SMBus read protocols.
Receive Byte
This is useful when repeatedly reading a single register. The
register address needs to have been set up previously. In this
operation, the master device receives a single byte from a slave
device as follows:The master device asserts a start condition on SDA.The master sends the 7-bit slave address followed by the
read bit (high).The addressed slave device asserts ACK on SDA.The master receives a data byte.The master asserts NO ACK on SDA.The master asserts a stop condition on SDA and the trans-
action ends.
In the ADT7463, the receive byte protocol is used to read a
single byte of data from a register whose address has previously
been set by a send byte or write byte operation.
Figure 12. Single Byte Read from a Register
ALERT RESPONSE ADDRESS
Alert response address (ARA) is a feature of SMBus devices that
allows an interrupting device to identify itself to the host when
multiple devices exist on the same bus.
The SMBALERT output can be used as an interrupt output or
can be used as an SMBALERT. One or more outputs can be
connected to a common SMBALERT line connected to the
master. If a device’s SMBALERT line goes low, the following
procedure occurs:SMBALERT is pulled low.Master initiates a read operation and sends the alert response
address (ARA = 0001 100). This is a general call address
that must not be used as a specific device address.The device whose SMBALERT output is low responds to
the alert response address, and the master reads its device
address. The address of the device is now known and it can
be interrogated in the usual way.If more than one device’s SMBALERT output is low, the one
with the lowest device address will have priority in accordance
with normal SMBus arbitration.Once the ADT7463 has responded to the alert response
address, the master must read the status registers and the
SMBALERT will only be cleared if the error condition has
gone away.
SMBUS TIMEOUT
The ADT7463 includes an SMBus timeout feature. If there is
no SMBus activity for 35 ms, the ADT7463 assumes that the bus
is locked and releases the bus. This prevents the device from
locking or holding the SMBus expecting data. Some SMBus
controllers cannot handle the SMBus timeout feature, so it
can be disabled.
VOLTAGE MEASUREMENT INPUTS
The ADT7463 has four external voltage measurement channels.
It can also measure its own supply voltage, VCC.
Pins 20 to 23 are dedicated to measuring 5 V, 12 V, and 2.5 V
supplies and the processor core voltage VCCP (0 V to 3 V input).
The VCC supply voltage measurement is carried out through
the VCC pin (Pin 4). Setting Bit 7 of Configuration Register 1
(Reg. 0x40) allows a 5 V supply to power the ADT7463 and be
measured without overranging the VCC measurement channel.
The 2.5 V input can be used to monitor a chipset supply voltage
in computer systems.
ANALOG-TO-DIGITAL CONVERTER (ADC)
All analog inputs are multiplexed into the on-chip, successive
approximation, ADC. This has a resolution of 10 bits. The basic
input range is 0 V to 2.25 V, but the inputs have built-in attenu-
ators to allow measurement of 2.5 V, 3.3V, 5 V, 12 V, and the
processor core voltage VCCP without any external components. To
allow for the tolerance of these supply voltages, the ADC pro-
duces an output of 3/4 full scale (decimal 768 or 300 hex) for
the nominal input voltage and so has adequate headroom to
cope with overvoltages.
INPUT CIRCUITRY
The internal structure for the analog inputs is shown in Figure13.
Each input circuit consists of an input protection diode, an
attenuator, plus a capacitor to form a first-order, low-pass filter
that gives the input immunity to high frequency noise.
VOLTAGE MEASUREMENT REGISTERS
Reg. 0x20 2.5 V Reading = 0x00 Default
Reg. 0x21 VCCP Reading = 0x00 Default
Reg. 0x22 VCC Reading = 0x00 Default
Reg. 0x23 5 V Reading = 0x00 Default
Reg. 0x24 12 V Reading = 0x00 Default
VOLTAGE MEASUREMENT LIMIT REGISTERS
Associated with each voltage measurement channel are high and
low limit registers. Exceeding the programmed high or low limit
causes the appropriate status bit to be set. Exceeding either limit
can also generate SMBALERT interrupts.
Reg. 0x44 2.5 V Low Limit = 0x00 Default
Reg. 0x45 2.5 V High Limit = 0xFF Default
Reg. 0x46 VCCP Low Limit = 0x00 Default
Reg. 0x47 VCCP High Limit = 0xFF Default
Reg. 0x48 VCC Low Limit = 0x00 Default
Reg. 0x49 VCC High Limit = 0xFF Default
Reg. 0x4A 5 V Low Limit = 0x00 Default
Reg. 0x4B 5 V High Limit = 0xFF Default
Reg. 0x4C 12 V Low Limit = 0x00 Default
Reg. 0x4D 12 V High Limit = 0xFF Default
Figure 13. Structure of Analog Inputs
Table II shows the input ranges of the analog inputs and output
codes of the 10-bit ADC.
When the ADC is running, it samples and converts a voltage
input in 711 µs and averages 16 conversions to reduce noise;measurement on each input takes nominally 11.38 ms.
ADT7463
Table II. 10-Bit A/D Output Code vs. VIN
*The VCC output codes listed assume that VCC is 3.3 V. If VCC input is reconfigured for 5 V operation (by setting Bit 7 of Configuration Register 1), then the VCC
output codes are the same as for the +5VIN column.
VID CODE MONITORING
The ADT7463 has five dedicated voltage ID (VID code) inputs.
These are digital inputs that can be read back through the
VID register (Reg. 0x43) to determine the processor voltage
required/being used in the system. Five VID code inputs support
VRM9.x solutions. In addition, Pin 21 (12 V input) can be recon-
figured as a sixth VID input to satisfy future VRM requirements.
VID CODE REGISTER – Register 0x43
<0> = VID0 (reflects logic state of Pin 5)
<1> = VID1 (reflects logic state of Pin 6)
<2> = VID2 (reflects logic state of Pin 7)
<3> = VID3 (reflects logic state of Pin 8)
<4> = VID4 (reflects logic state of Pin 19)
<5> = VID5 (reconfigurable 12 V input). This bit reads 0 when
Pin 21 is configured as the 12 V input. This bit reflects the logic
state of Pin 21 when the pin is configured as VID5.
VID CODE INPUT THRESHOLD VOLTAGE
The switching threshold for the VID code inputs is approximately
1 V. To enable future compatibility, it is possible to reduce the
VID code input threshold to 0.6 V. Bit 6 (THLD) of VID register
(Reg. 0x43) controls the VID input threshold voltage.
VID CODE REGISTER – Register 0x43
<6> THLD = 0; VID Switching Threshold = 1 V,
VOL < 0.8 V, VIH > 1.7 V, VMAX = 3.3 V
THLD = 1; VID Switching Threshold = 0.6 V,
VOL < 0.4 V, VIH > 0.8 V, VMAX = 3.3 V
RECONFIGURING PIN 21 (+12V/VID5) AS VID5 INPUT
Pin 21 can be reconfigured as a sixth VID code input (VID5)
for VRM10-compatible systems. Since the pin is configured as
VID5, it is no longer possible to monitor a 12 V supply.
Bit 7 of the VID register (Reg. 0x43) determines the function of
Pin 21. System or BIOS software can read the state of Bit 7 to
determine whether the system is designed to monitor 12 V or is
monitoring a sixth VID input.
VID CODE REGISTER – Register 0x43
<7> VIDSEL = 0; Pin 21 functions as a 12 V measurement
input. Software can read this bit to determine that there are five
VID inputs being monitored. Bit 5 of Register 0x43 (VID5)
always reads back 0. Bit 0 of Status Register 2 (Reg. 0x42)
reflects 12 V out-of-limit measurements.
VIDSEL = 1; Pin 21 functions as the sixth VID code input
(VID5). Software can read this bit to determine that there are
six VID inputs being monitored. Bit 5 of Register 0x43 reflects
the logic state of Pin 21. Bit 0 of Status Register 2 (Reg. 0x42)
reflects VID code changes.
VID CODE CHANGE DETECT FUNCTION
The ADT7463 has a VID code change detect function. When
Pin 21 is configured as the VID5 input, VID code changes can
be detected and reported back by the ADT7463. Bit 0 of Status
Register 2 (Reg. 0x42) is the 12V/VC bit and denotes a VID
change when set. The VID code change bit gets set when the
logic states on the VID inputs are different than they were 11µs
previously. The change of VID code can be used to generate
an SMBALERT interrupt. If an SMBALERT interrupt is
notrequired, Bit 0 of Interrupt Mask Register 2 (Reg. 0x75),
when set, prevents SMBALERTs from occurring on VIDcode
changes.
STATUS REGISTER 2 – Register 0x42
<0> 12V/VC = 0; If Pin 21 is configured as VID5, then a
Logic 0 denotes no change in VID code within last 11 µs.
<0> 12V/VC = 1; If Pin 21 is configured as VID5, then a Logic 1
means that a change has occurred on the VID code inputs within
the last 11 µs. An SMBALERT generates if this function is en-
abled.
ADDITIONAL ADC FUNCTIONS
A number of other functions are available on the ADT7463 to
offer the systems designer increased flexibility, including:
Turn-Off Averaging
For each voltage measurement read from a value register,readings have actually been made internally and the results
averaged before being placed into the value register. There may
be an instance where you would like to speed up conversions.
Setting Bit 4 of Configuration Register 2 (Reg. 0x73) turns
averaging off. This effectively gives a reading 16 times faster
(711µs), but the reading may be noisier.
Bypass Voltage Input Attenuators
Setting Bit 5 of Configuration Register 2 (Reg 0x73) removes
the attenuation circuitry from the 2.5 V, VCCP, VCC, 5 V, and
12 V inputs. This allows the user to directly connect external
sensors or rescale the analog voltage measurement inputs for
other applications. The input range of the ADC without the
attenuators is 0 V to 2.25 V.
Single-Channel ADC Conversion
Setting Bit 6 of Configuration Register 2 (Reg. 0x73) places the
ADT7463 into single-channel ADC conversion mode. In this mode,
the ADT7463 can be made to read a single voltage channel
only. If the internal ADT7463 clock is used, the selected input
is read every 711 µs. The appropriate ADC channel is selected
by writing to Bits <7:5> of the TACH1 Minimum High Byte
Register (0x55).
Bits <7:5>Channel
Reg 0x55Selected
0002.5 V
001VCCP
010VCC
0115 V
10012 V
Configuration Register 2 (Reg. 0x73)
<4> = 1 Averaging Off
<5> = 1 Bypass Input Attenuators
<6> = 1 Single-Channel Convert Mode
TACH1 Minimum High Byte (Reg. 0x55)
<7:5> Selects ADC Channel for Single-Channel Convert Mode
ADT7463
Figure 14. Signal Conditioning for Remote Diode Temperature Sensors
TEMPERATURE MEASUREMENT SYSTEM
Local Temperature Measurement
The ADT7463 contains an on-chip band gap temperature sensor
whose output is digitized by the on-chip 10-bit ADC. The 8-bit
MSB temperature data is stored in the local temperature register
(Address 26h). As both positive and negative temperatures can be
measured, the temperature data is stored in twos complement
format, as shown in Table III. Theoretically, the temperature sensor
and ADC can measure temperatures from –128�C to +127�C
with a resolution of 0.25�C. However, this exceeds the operating
temperature range of the device, so local temperature measure-
ments outside this range are not possible.
Remote Temperature Measurement
The ADT7463 can measure the temperature of two remote diode
sensors or diode-connected transistors connected to Pins 15 and
16, or 17 and 18.
The forward voltage of a diode or diode-connected transistor
operated at a constant current exhibits a negative temperature
coefficient of about –2 mV/�C. Unfortunately, the absolute
value of VBE varies from device to device and individual calibra-
tion is required to null this out, so the technique is unsuitable
for mass production. The technique used in the ADT7463 is to
measure the change in VBE when the device is operated at two
different currents.
This is given by
where:
K is Boltzmann’s constant.
q is the charge on the carrier.
T is the absolute temperature in Kelvins.
N is the ratio of the two currents.
Figure 14 shows the input signal conditioning used to measure
the output of a remote temperature sensor. This figure shows the
external sensor as a substrate transistor, provided for temperature
monitoring on some microprocessors. It could equally well be a
discrete transistor, such as a 2N3904.
If a discrete transistor is used, the collector will not be grounded
and should be linked to the base. If a PNP transistor is used, the
base is connected to the D– input and the emitter to the D+
input. If an NPN transistor is used, the emitter is connected to
the D– input and the base to the D+ input. Figures 15a and 15b
show how to connect the ADT7463 to an NPN or PNP transis-
tor for temperature measurement. To prevent ground noise from
interfering with the measurement, the more negative terminal of
the sensor is not referenced to ground but is biased above ground
by an internal diode at the D– input.
To measure ∆VBE, the sensor is switched between operating currents
of I and N � I. The resulting waveform is passed through akHz low-pass filter to remove noise and to a chopper-stabilized
amplifier that performs the functions of amplification and recti-
fication of the waveform to produce a dc voltage proportional to
∆VBE. This voltage is measured by the ADC to give a tempera-
ture output in 10-bit, twos complement format. To further reduce
the effects of noise, digital filtering is performed by averaging
the results of 16 measurement cycles. A remote temperature
measurement takes nominally 25.5 ms. The results of remote
temperature measurements are stored in 10-bit, twos complement
format, as illustrated in Table III. The extra resolution for the
temperature measurements is held in the Extended Resolution
Register 2 (Reg. 0x77). This gives temperature readings with a
resolution of 0.25�C.
Table III.Temperature Data Format
*Bold denotes 2 LSBs of measurement in Extended
Resolution Register 2 (Reg. 0x77) with 0.25�C resolution.
Figure 15a. Measuring Temperature Using an
NPN Transistor
Figure 15b. Measuring Temperature Using a PNP
Transistor
Nulling Out Temperature Errors
As CPUs run faster, it is getting more difficult to avoid high
frequency clocks when routing the D+, D– traces around a
system board. Even when recommended layout guidelines are
followed, there may still be temperature errors attributed to
noise being coupled onto the D+/D– lines. High frequency noise
generally has the effect of giving temperature measurements that are
too high by a constant amount. The ADT7463 has temperature
offset registers at Addresses 0x70, 0x72 for the Remote 1 and
Remote 2 temperature channels. By doing a one-time calibration
of the system, one can determine the offset caused by system
board noise and null it out using the offset registers. The offset
registers automatically add a twos complement 8-bit reading to
every temperature measurement. The LSBs add 0.25°C offset to
the temperature reading so the 8-bit register effectively allows
temperature offsets of up to �32�C with a resolution of 0.25�C.
This ensures that the readings in the temperature measurement
registers are as accurate as possible.
Temperature Offset Registers
Reg. 0x70 Remote 1 Temperature Offset = 0x00 (0°C Default)
Reg. 0x71 Local Temperature Offset = 0x00 (0°C Default)
Reg. 0x72 Remote 2 Temperature Offset = 0x00 (0°C Default)
ADT7463
Temperature Measurement Registers
Reg. 0x25 Remote 1 Temperature = 0x80 Default
Reg. 0x26 Local Temperature = 0x80 Default
Reg. 0x27 Remote 2 Temperature = 0x80 Default
Reg. 0x77 Extended Resolution 2 = 0x00 Default
<7:6> TDM2 = Remote 2 Temperature LSBs
<5:4> LTMP = Local Temperature LSBs
<3:2> TDM1 = Remote 1 Temperature LSBs
Temperature Measurement Limit Registers
Associated with each temperature measurement channel are
high and low limit registers. Exceeding the programmed high or
low limit causes the appropriate status bit to be set. Exceeding
either limit can also generate SMBALERT interrupts.
Reg. 0x4E Remote 1 Temp Low Limit = 0x81 Default
Reg. 0x4F Remote 1 Temp High Limit = 0x7F Default
Reg. 0x50 Local Temp Low Limit = 0x81 Default
Reg. 0x51 Local Temp High Limit = 0x7F Default
Reg. 0x52 Remote 2 Temp Low Limit = 0x81 Default
Reg. 0x53 Remote 2 Temp High Limit = 0x7F Default
Reading Temperature from the ADT7463
It is important to note that temperature can be read from the
ADT7463 as an 8-bit value (with 1°C resolution) or as a 10-bit
value (with 0.25°C resolution). If only 1°C resolution is required,
the temperature readings can be read back at any time and in no
particular order.
If the 10-bit measurement is required, this involves a 2-register
read for each measurement. The extended resolution register
(Reg. 0x77) should be read first. This causes all temperature
reading registers to be frozen until all temperature reading regis-
ters have been read from. This prevents an MSB reading from
being updated while its 2 LSBs are being read and vice versa.
ADDITIONAL ADC FUNCTIONS
A number of other functions are available on the ADT7463 to
offer the systems designer increased flexibility.
Turn-Off Averaging
For each temperature measurement read from a value register,
16 readings have actually been made internally and the results
averaged before being placed into the value register. Sometimes
it may be necessary to take a very fast measurement, e.g., of CPU
temperature. Setting Bit 4 of Configuration Register 2 (Reg. 0x73)
turns averaging off. This takes a reading every 13 ms. The mea-
surement itself takes 4 ms.
Single-Channel ADC Conversions
Setting Bit 6 of Configuration Register 2 (Reg. 0x73) places the
ADT7463 into single-channel ADC conversion mode. In this
mode, the ADT7463 can be made to read a single temperature
channel only. If the internal ADT7463 clock is used, the
selected input is read every 1.4 ms. The appropriate ADC chan-
nel is selected by writing to Bits <7:5> of TACH1 Minimum
High Byte Register (0x55).
Bits <7:5> Reg 0x55Channel Selected
101Remote 1 Temperature
110Local Temperature
111Remote 2 Temperature
Configuration Register 2 (Reg. 0x73)
<4> = 1 Averaging Off
<6> = 1 Single-Channel Convert Mode
TACH1 Minimum High Byte (Reg. 0x55)
<7:5> Selects ADC Channel for Single-Channel Convert Mode
Overtemperature Events
Overtemperature events on any of the temperature channels can
be detected and dealt with automatically in automatic fan speed
control mode. Registers 0x6A to 0x6C are the THERM limits.
When a temperature exceeds its THERM limit, all fans run at
100% duty cycle. The fans stay running at 100% until the
temperature drops below THERM – Hysteresis (this can be
disabled by setting the boost bit in Configuration Register3,
Bit 2, Register 0x78). The hysteresis value for that THERM
limit is the value programmed into Registers 0x6D, 0x6E
(hysteresis registers). The default hysteresis value is 4°C.
Figure 16. THERM Limit Operation
LIMITS, STATUS REGISTERS, AND INTERRUPTS
Limit Values
Associated with each measurement channel on the ADT7463
are high and low limits. These can form the basis of system
status monitoring: a status bit can be set for any out-of-limit
condition and detected by polling the device. Alternatively,
SMBALERT interrupts can be generated to flag a processor or
microcontroller of out-of-limit conditions.
8-Bit Limits
The following is a list of 8-bit limits on the ADT7463.
Voltage Limit Registers
Reg. 0x44 2.5 V Low Limit = 0x00 Default
Reg. 0x45 2.5 V High Limit = 0xFF Default
Reg. 0x46 VCCP Low Limit = 0x00 Default
Reg. 0x47 VCCP High Limit = 0xFF Default
Reg. 0x48 VCC Low Limit = 0x00 Default
Reg. 0x49 VCC High Limit = 0xFF Default
Reg. 0x4A 5 V Low Limit = 0x00 Default
Reg. 0x4B 5 V High Limit = 0xFF Default
Reg. 0x4C 12 V Low Limit = 0x00 Default
Reg. 0x4D 12 V High Limit = 0xFF Default
Temperature Limit Registers
Reg. 0x4E Remote 1 Temp Low Limit = 0x81 Default
Reg. 0x4F Remote 1 Temp High Limit = 0x7F Default
Reg. 0x6A Remote 1 THERMTHERMTHERMTHERMTHERM Limit = 0x64 Default
Reg. 0x50 Local Temp Low Limit = 0x81 Default
Reg. 0x51 Local Temp High Limit = 0x7F Default
Reg. 0x6B Local THERMTHERMTHERMTHERMTHERM Limit = 0x64 Default
Reg. 0x52 Remote 2 Temp Low Limit = 0x81 Default
Reg. 0x53 Remote 2 Temp High Limit = 0x7F Default
Reg. 0x6C Remote 2 THERMTHERMTHERMTHERMTHERM Limit = 0x64 Default
THERM Limit Register
Reg. 0x7A THERMTHERMTHERMTHERMTHERM Limit = 0x00 Default
16-Bit Limits
The fan TACH measurements are 16-bit results. The fan TACH
limits are also 16 bits, consisting of a high byte and low byte.
Since fans running under speed or stalled are normally the only
conditions of interest, only high limits exist for fan TACHs. Since
fan TACH period is actually being measured, exceeding the limit
indicates a slow or stalled fan.
Fan Limit Registers
Reg. 0x54 TACH1 Minimum Low Byte = 0xFF Default
Reg. 0x55 TACH1 Minimum High Byte = 0xFF Default
Reg. 0x56 TACH2 Minimum Low Byte = 0xFF Default
Reg. 0x57 TACH2 Minimum High Byte = 0xFF Default
Reg. 0x58 TACH3 Minimum Low Byte = 0xFF Default
Reg. 0x59 TACH3 Minimum High Byte = 0xFF Default
Reg. 0x5A TACH4 Minimum Low Byte = 0xFF Default
Reg. 0x5B TACH4 Minimum High Byte = 0xFF Default
Out-of-Limit Comparisons
Once all limits are programmed, the ADT7463 can be enabled
for monitoring. The ADT7463 measures all parameters in
round-robin format and sets the appropriate status bit for out-
of-limit conditions. Comparisons are done differently depending
on whether the measured value is being compared to a high or
low limit.
Figure 17. Temperature > Low Limit: No INT
ADT7463
Figure 18. Temperature = Low Limit: INT Occurs
Figure 19. Temperature = High Limit: No INT
HIGH LIMIT
Figure 20. Temperature > High Limit: INT Occurs
Analog Monitoring Cycle Time
The analog monitoring cycle begins when a 1 is written to the
start bit (Bit 0) of Configuration Register 1 (Reg. 0x40). The ADC
measures each analog input in turn and as each measurement is
completed, the result is automatically stored in the appropriate
value register. This round-robin monitoring cycle continues
unless disabled by writing a 0 to Bit 0 of Configuration Register1.
Because the ADC is normally left to free-run in this manner, the
time taken to monitor all the analog inputs is normally not of
interest, since the most recently measured value of any input
can be read out at any time.
For applications where the monitoring cycle time is important,
it is easily calculated.
The total number of channels measured is:Four dedicated supply voltage inputs3.3 VSTBY or 5 V supply (VCC pin)Local temperatureTwo remote temperatures
As mentioned previously, the ADC performs round-robin
conversions and takes 11.38 ms for each voltage measurement,ms for a local temperature reading, and 25.5 ms for each remote
temperature reading.
The total monitoring cycle time for averaged voltage and tempera-
ture monitoring is therefore nominally
Fan TACH measurements are made in parallel and are not
synchronized with the analog measurements in any way.
Status Registers
The results of limit comparisons are stored in Status Registers 1
and 2. The status register bit for each channel reflects the status
of the last measurement and limit comparison on that channel.
If a measurement is within limits, the corresponding status register
bit is cleared to 0. If the measurement is out-of-limits, the corre-
sponding status register bit is set to 1.
The state of the various measurement channels may be polled
by reading the status registers over the serial bus. In Bit 7 (OOL)
of Status Register 1 (Reg. 0x41), 1 means that an out-of-limit
event has been flagged in Status Register 2. This means that a
user need only read Status Register 2 when this bit is set. Alter-
natively, Pin 10 or Pin 22 can be configured as an SMBALERT
output. This automatically notifies the system supervisor of an
out-of-limit condition. Reading the status registers clears the
appropriate status bit as long as the error condition that caused
the interrupt has cleared. Status register bits are “sticky.” When-
ever a status bit gets set, indicating an out-of-limit condition,remains set even if the event that caused it has gone away
(until read). The only way to clear the status bit is to read the
status register after the event has gone away. Interrupt status
mask registers (Reg. 0x74, 0x75) allow individual interrupt
sources to be masked from causing an SMBALERT. However,
if one of these masked interrupt sources goes out-of-limit, its
associated status bit gets set in the interrupt status registers.
Figure 21. Status Register 1
Status Register 1 (Reg. 0x41)
Bit 7 (OOL) = 1, denotes a bit in Status Register 2 is set and
Status Register 2 should be read.
Bit 6 (R2T) = 1, Remote 2 Temperature High or Low Limit
has been exceeded.
Bit 5 (LT) = 1, Local Temperature High or Low Limit has
been exceeded.
Bit 4 (R1T) = 1, Remote 1 Temperature High or Low Limit
has been exceeded.
Bit 3 (5V) = 1, 5 V High or Low Limit has been exceeded.
Bit 2 (VCC) = 1, VCC High or Low Limit has been exceeded.
Bit 1 (VCCP) = 1, VCCP High or Low Limit has been exceeded.
Bit 0 (2.5V) = 1, 2.5 V High or Low Limit has been exceeded.
Figure 22. Status Register 2
Status Register 2 (Reg. 0x42)
Bit 7 (D2) = 1, indicates an open or short on D2+/D2– inputs.
Bit 6 (D1) = 1, indicates an open or short on D2+/D2– inputs.
Bit 5 (F4P) = 1, indicates Fan 4 has dropped below minimum
speed. Alternatively, indicates that THERM limit has been
exceeded if the THERM function is used.
Bit 4 (FAN3) = 1, indicates Fan 3 has dropped below mini-
mum speed.
Bit 3 (FAN2) = 1, indicates Fan 2 has dropped below minimum
speed.
Bit 2 (FAN1) = 1, indicates Fan 1 has dropped below mini-
mum speed.
Bit 1 (OVT) = 1, indicates that a THERM overtemperature
limit has been exceeded.
Bit 0 (12V/VC) = 1, 12 V High or Low Limit has been
exceeded. If the VID code change function is used, this bit
indicates a change in VID code on the VID0 to VID5 inputs.
SMBALERT Interrupt Behavior
The ADT7463 can be polled for status, or an SMBALERT
interrupt can be generated for out-of-limit conditions. It is
important to note how the SMBALERT output and status bits
TEMPERATURE
Figure 23. SMBALERT and Status Bit Behavior
Figure 23 shows how the SMBALERT output and “sticky” status
bits behave. Once a limit is exceeded, the corresponding status
bit gets set to 1. The status bit remains set until the error condi-
tion subsides and the status register gets read. The status bits are
referred to as sticky since they remain set until read by software.
This ensures that an out-of-limit event cannot be missed if software
is polling the device periodically. Note that the SMBALERT
output remains low for the entire duration that a reading is
out-of-limit and until the status register has been read. This
has implications on how software handles the interrupt.
HANDLING SMBALERT INTERRUPTS
To prevent the system from being tied up servicing interrupts, it
is recommend to handle the SMBALERT interrupt as follows:Detect the SMBALERT assertion.Enter the interrupt handler.Read the status registers to identify the interrupt source.Mask the interrupt source by setting the appropriate mask
bit in the interrupt mask registers (Reg. 0x74, 0x75).Take the appropriate action for a given interrupt source.Exit the Interrupt Handler.Periodically poll the status registers. If the interrupt status bit
has cleared, reset the corresponding interrupt mask bit to 0.
This causes the SMBALERT output and status bits to be-
have as shown in Figure 24.
Figure 24. How Masking the Interrupt Source Affects
SMBALERT Output
ADT7463
Masking Interrupt Sources
Interrupt Mask Registers 1 and 2 are located at Addresses
0x74 and 0x75. These allow individual interrupt sources to be
masked out to prevent SMBALERT interrupts. Note that
masking an interrupt source only prevents the SMBALERT
output from being asserted; the appropriate status bit gets set
as normal.
Interrupt Mask Register 1 (Reg. 0x74)
Bit 7 (OOL) = 1, masks SMBALERT for any alert condition
flagged in Status Register 2.
Bit 6 (R2T) = 1, masks SMBALERT for Remote 2 Temperature.
Bit 5 (LT) = 1, masks SMBALERT for Local Temperature.
Bit 4 (R1T) = 1, masks SMBALERT for Remote 1 Temperature.
Bit 3 (5V) = 1, masks SMBALERT for 5 V channel.
Bit 2 (VCC) = 1, masks SMBALERT for VCC channel.
Bit 1 (VCCP) = 1, masks SMBALERT for VCCP channel.
Bit 0 (2.5V) = 1, masks SMBALERT for 2.5 V channel.
Interrupt Mask Register 2 (Reg. 0x75)
Bit 7 (D2) = 1, masks SMBALERT for Diode 2 errors.
Bit 6 (D1) = 1, masks SMBALERT for Diode 1 errors.
Bit 5 (FAN4) = 1, masks SMBALERT for Fan 4 failure. If the
TACH4 pin is being used as the THERM input, this bit masks
SMBALERT for a THERM event.
Bit 4 (FAN3) = 1, masks SMBALERT for Fan 3.
Bit 3 (FAN2) = 1, masks SMBALERT for Fan 2.
Bit 2 (FAN1) = 1, masks SMBALERT for Fan 1.
Bit 1 (OVT) = 1, masks SMBALERT for overtemperature
(exceeding THERM limits).
Bit 0 (12V/VC) = 1, masks SMBALERT for 12 V channel or
for a VID code change, depending on the function used.
Enabling the SMBALERT Interrupt Output
The SMBALERT interrupt function is disabled by default.
Pin 10 or Pin 22 can be reconfigured as an SMBALERT output
to signal out-of-limit conditions.
CONFIGURING PIN 22 AS SMBALERT OUTPUT
REGISTERBIT SETTING
Config Reg 3 (Reg. 0x78)<0> ALERT = 1
CONFIGURING PIN 22 AS SMBALERT OUTPUT
REGISTERBIT SETTING
Config Reg 4 (Reg. 0x7D)<0> AL2.5V = 1
To Assign THERM Functionality to a Pin
Pin 14 or Pin 20 can be configured as the THERM pin on the
ADT7463.
To enable the THERM functionality, users must first set the
THERM enable bit. The TH5V bit then determines which pin
the THERM functionality is enabled on (i.e., users cannot enable
THERM on two pins at once).
To configure Pin 20 as the THERM pin:Set the TH5V bit (Bit 1) in the Configuration Register4
(Address = 0x7D) = 1.Set the THERM Enable Bit (Bit 1) in Configuration
Register3 (Address = 0x78) = 1.
To configure Pin 14 as the THERM pin:Set the TH5V bit (Bit 1) in the Configuration Register4
(Address = 0x7D) = 0.Set the THERM Enable Bit (Bit 1) in Configuration
Register 3 (Address = 0x78) = 1.
THERM as an Input
When configured as an input, the user can time assertions on
the THERM pin. This can be useful for connecting to the
PROCHOT output of a CPU to gauge system performance.
See this data sheet for more information on timing THERM
assertions and generating ALERTs based on THERM.
The user can also setup the ADT7463 so when the THERM pin
is driven low externally the fans run at 100%. The fans run at
100% for the duration of the THERM pin being pulled low.
This is done by setting the BOOST bit (Bit 2) in Configuration
Register 3 (Address = 0x78) to 1. This only works if the fan is
already running, for example, in manual mode when the
current duty cycle is above 0x00 or in automatic mode when
the temperature is above TMIN. If the temperature is below
TMIN or if the duty cycle in manual mode is set to 0x00, then
pulling the THERM low externally has no effect. See Figure25
for more information.
Figure 25. Asserting THERM Low as an Input in
Automatic Fan Speed Control Mode
THERM TIMER
The ADT7463 has an internal timer to measure THERM asser-
tion time. For example, the THERM input may be connected
to the PROCHOT output of a Pentium 4 CPU and measure
system performance. The THERM input may also be connected
to the output of a trip point temperature sensor.
The timer is started on the assertion of the ADT7463’s
THERM input and stopped on the negation of the pin. The
timer counts THERM times cumulatively, i.e., the timer
resumes counting on the next THERM assertion. The THERM
timer continues to accumulate THERM assertion times until
the timer is read (it is cleared on read) or until it reaches full
scale. If the counter reaches full scale, it stops at that reading
until cleared.
The 8-bit THERM timer register (Reg. 0x79) is designed such
that Bit 0 gets set to 1 on the first THERM assertion. Once the
cumulative THERM assertion time has exceeded 45.52 ms, Bit
1 of the THERM timer gets set and Bit 0 now becomes the LSB
of the timer with a resolution of 22.76 ms.
Figure 26. Understanding the THERM Timer
Figure 26 illustrates how the THERM timer behaves as the
THERM input is asserted and negated. Bit 0 gets set on the first
THERM assertion detected. This bit remains set until such time
as the cumulative THERM assertions exceed 45.52 ms. At this
time, Bit 1 of the THERM timer gets set, and Bit 0 is cleared.
Bit 0 now reflects timer readings with a resolution of 22.76 ms.
When using the THERM timer, be aware of the following:
After a THERM timer read (Reg. 0x79):
a) The contents of the timer get cleared on read.
b) The F4P bit (Bit 5) of Status Register 2 needs to be cleared
(assuming the THERM limit has been exceeded).
If the THERM timer is read during a THERM assertion, then
the following will happen:
a) The contents of the timer are cleared.
b) Bit 0 of the THERM timer is set to 1 (since a THERM
assertion is occurring).
c) The THERM timer increments from zero.
d) If the THERM limit (Reg. 0x7A) = 0x00, then the F4P bit
gets set.
Generating SMBALERT Interrupts from THERM Events
The ADT7463 can generate SMBALERTs when a programmable
THERM limit has been exceeded. This allows the systems
designer to ignore brief, infrequent THERM assertions, while
capturing longer THERM events. Register 0x7A is the THERM
Limit Register. This 8-bit register allows a limit from 0 seconds
(first THERM assertion) to 5.825 seconds to be set before an
SMBALERT is generated. The THERM timer value is compared
with the contents of the THERM limit register. If the THERM
timer value exceeds the THERM limit value, then the F4P bit
(Bit 5) of Status Register 2 gets set, and an SMBALERT is
generated. Note that the F4P bit (Bit 5) of Mask Register2
(Reg. 0x75) masks out SMBALERTs if this bit is set to 1, al-
though the F4P bit of Interrupt Status Register 2 still gets set if
the THERM limit is exceeded.
Figure 27 is a Functional Block Diagram of the THERM timer,
limit, and associated circuitry. Writing a value of 0x00 to the
THERM limit register (Reg. 0x7A) causes SMBALERT to
be generated on the first THERM assertion. A THERM limit
value of 0x01 generates an SMBALERT once cumulative THERM
assertions exceed 45.52 ms.
ADT7463
Figure 27. Functional Diagram of ADT7463’s THERM Monitoring Circuitry
Configuring the Desired THERM BehaviorConfigure the desired pin as the THERM input.
Setting Bit 1 (THERM Enable) of Configuration Register3
(Reg. 0x78) enables the THERM monitoring functionality.
This is enabled on Pin 14 by default.
Setting Bit 1 (TH5V) of Configuration Register 4
(Reg. 0x7D) enables THERM monitoring on Pin 20
(Bit1 of Configuration Register 3 must also be set). Pin14
can be used as TACH4.Select the desired fan behavior for THERM events.
Setting Bit 2 (BOOST bit) of Configuration Register 3
(Reg. 0x78) causes all fans to run at 100% duty cycle
whenever THERM gets asserted. This allows fail-safe system
cooling. If this bit = 0, the fans run at their current settings
and are not affected by THERM events.Select whether THERM events should generateSMBALERT interrupts.
Bit 5 (F4P) of Mask Register 2 (Reg. 0x75), when set, masks
out SMBALERTs when the THERM limit value gets
exceeded. This bit should be cleared if SMBALERTs based
on THERM events are required.Select a suitable THERM limit value.
This value determines whether an SMBALERT is generated
on the first THERM assertion, or only if a cumulative THERM
assertion time limit is exceeded. A value of 0x00 causes an
SMBALERT to be generated on the first THERM assertion.Select a THERM monitoring time.
This is how often OS or BIOS level software checks the
THERM timer. For example, BIOS could read the THERM
timer once an hour to determine the cumulative THERM
assertion time. If, for example, the total THERM assertion
time is <22.76 ms in Hour 1, >182.08 ms in Hour 2, and
>5.825 s in Hour 3, this can indicate that system performance
is degrading significantly since THERM is asserting more
frequently on an hourly basis.
Alternatively, OS or BIOS level software can time-stamp
when the system is powered on. If an SMBALERT is gener-
ated due to the THERM limit being exceeded, another
time-stamp can be taken. The difference in time can be
calculated for a fixed THERM limit time. For example, if it
takes one week for a THERM limit of 2.914 s to be exceeded
and the next time it takes only 1 hour, then this is an
indication of a serious degradation in system performance.
Configuring the ADT7463 THERM Pin as an Output
In addition to the ADT7463 being able to monitor THERM as
an input, the ADT7463 can optionally drive THERM low as an
output. The user can preprogram system critical thermal limits.
If the temperature exceeds a thermal limit by 0.25°C, THERM
asserts low. If the temperature is still above the thermal limit on
the next monitoring cycle, THERM stays low. THERM remains
asserted low until the temperature is equal to or below the
thermal limit. Since the temperature for that channel is mea-
sured only every monitoring cycle, once THERM asserts it is
guaranteed to remain low for at least one monitoring cycle.
The THERM pin can be configured to assert low if the
Remote 1, Local, or Remote 2 Temperature THERM limits get
exceeded by 0.25°C. The THERM limit registers are at loca-
tions 0x6A, 0x6B, and 0x6C, respectively. Setting Bit 3 of
Registers 0x5F, 0x60, and 0x61 enables the THERM output
feature for the Remote 1, Local, and Remote 2 Temperature
channels, respectively. Figure 28 shows how the THERM pin
asserts low as an output in the event of a critical overtemperature.
Figure 28. Asserting THERM as an Output, Based
on Tripping THERM Limits
FAN DRIVE USING PWM CONTROL
The ADT7463 uses pulse-width modulation (PWM) to control
fan speed. This relies on varying the duty cycle (or on/off ratio)
of a square wave applied to the fan to vary the fan speed. The
external circuitry required to drive a fan using PWM control is
extremely simple. A single NMOSFET is the only drive device
required. The specifications of the MOSFET depend on the
maximum current required by the fan being driven. Typical
notebook fans draw a nominal 170 mA, and so SOT devices can
be used where board space is a concern. In desktops, fans can
typically draw 250 mA to 300 mA each. If you drive several fans
in parallel from a single PWM output or drive larger server fans,
the MOSFET needs to handle the higher current requirements.
The only other stipulation is that the MOSFET should have a
gate voltage drive, VGS < 3.3 V for direct interfacing to the
PWM_OUT pin. VGS can be greater than 3.3 V as long as the
pull-up on the gate is tied to 5 V. The MOSFET should also have
a low onresistance to ensure that there is not significant voltage
drop across the FET. This reduces the voltage applied across
the fan and therefore the maximum operating speed ofthe fan.
Figure 29 shows how a 3-wire fan may be driven using PWM
control.
Figure 29. Driving a 3-Wire Fan Using an
N-Channel MOSFET
Figure 29 uses a 10 kΩ pull-up resistor for the TACH signal. This
assumes that the TACH signal is open-collector from the fan. In
all cases, the TACH signal from the fan must be kept below 5V
maximum to prevent damaging the ADT7463. If in doubt as to
whether the fan used has an open-collector or totem pole TACH
output, use one of the input signal conditioning circuits shown
in the Fan Speed Measurement section of the data sheet.
Figure 30 shows a fan drive circuit using an NPN transistor
such as a general-purpose MMBT2222. While these devices are
inexpensive, they tend to have much lower current handling
capabilities and higher onresistance than MOSFETs. When
choosing a transistor, care should be taken to ensure that it
meets the fan’s current requirements.
Ensure that the base resistor is chosen such that the transistor is
saturated when the fan is powered on.
Figure 30. Driving a 3-Wire Fan Using an NPN Transistor
ADT7463
Figure 31. Interfacing Two Fans in Parallel to the PWM3 Output Using Low Cost NPN Transistors
Figure 32. Interfacing Two Fans in Parallel to the PWM3 Output Using a Single N-Channel MOSFET
Driving Two Fans from PWM3
Note that the ADT7463 has four TACH inputs available for fan
speed measurement, but only three PWM drive outputs. If a
fourth fan is being used in the system, it should be driven from
the PWM3 output in parallel with the third fan. Figure 31 shows
how to drive two fans in parallel using low cost NPN transistors.
Figure 32 is the equivalent circuit using the NDT3055L MOSFET.
Note that since the MOSFET can handle up to 3.5A, it is
simply a matter of connecting another fan directly in parallel
with the first.
Care should be taken in designing drive circuits with transistors
and FETs to ensure that the PWM pins are not required to
source current and that they sink less than the 8 mA maximum
current specified on the data sheet.
Driving up to Three Fans from PWM2
TACH measurements for fans are synchronized to particular
PWM channels, e.g., TACH1 is synchronized to PWM1. TACH3
and TACH4 are both synchronized to PWM3 so PWM3 can
drive 2 fans. Alternatively, PWM2 can be programmed to
synchronize TACH2, TACH3, and TACH4 to the PWM2 out-
put. This allows PWM2 to drive two or three fans. In this case,
the drive circuitry looks the same as shown in Figures 31 and 32.
The SYNC bit in Register 0x62 enables this function.
<4> (SYNC) ENHANCE ACOUSTICS REG 1 (0X62)
SYNC = 1 Synchronizes TACH2, TACH3, and TACH4PWM2.

Partno	Mfg	Dc	Qty	Available	Descript
ADT7463ARQ	AD	N/a	8580	avai	dBCOOL™ Thermal Management Controller and Voltage Monitor
ADT7463ARQ-REEL \|ADT7463ARQREEL	AD	N/a	5000	avai	dBCOOL™ Thermal Management Controller and Voltage Monitor
ADT7463ARQ-REEL7 \|ADT7463ARQREEL7	AD	N/a	1000	avai	dBCOOL™ Thermal Management Controller and Voltage Monitor
ADT7463ARQZ	ADI	N/a	236	avai	dBCOOL™ Thermal Management Controller and Voltage Monitor
ADT7463ARQZ-REEL \|ADT7463ARQZREEL	AD	N/a	3700	avai	dBCOOL™ Thermal Management Controller and Voltage Monitor