ADSST-21065LKS-240 Fast Delivery |IC PHOENIX CO.,LIMITED

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ADSST-21065LKS-240
High End/ Multichannel/ 32-Bit Floating-Point Audio Processor
REV. 0
High End, Multichannel,
32-Bit Floating-Point Audio Processor
GENERAL DESCRIPTION
The SST-Melody-SHARC family of powerful 32-bit Audio Proces-
sors from Analog Devices provides flexible solutions and delivers
a host of features across high end and high fidelity audio systems
to the AV receiver and DVD markets. It includes multichannel
audio decoders, encoders, and post processors for digital
audio designs using DSP chipsets in home theater systems and
automotive audio receivers.
(continued on page 11)
FEATURES
Super Harvard Architecture Computer (SHARC)
4 Independent Buses for Dual Data, Instruction, and
I/O Fetch on a Single Cycle
32-Bit Fixed-Point Arithmetic; 32-Bit and 40-Bit Floating-
Point Arithmetic
544 Kbits On-Chip SRAM Memory, Integrated I/O
Peripheral I2 S Support for 8 Simultaneous Receive and
Transmit Channels
66 MIPS, 198 MFLOPS Peak, 132 MFLOPS Sustained
Performance
User-Configurable 544 Kbits On-Chip SRAM Memory
2 External Port, DMA Channels and 8 Serial Port,
DMA Channels
Decodes Industry Standard Formats Using a 32-Bit
Floating Point Implementation for Decoding
Dolby® Digital AC-3, Dolby Digital EX Processing
Dolby Pro Logic® , 96 kHz, Dolby Pro Logic II
Dolby Headphone, Dolby 3/0
DTS® 5.1, DTS-ES® -Discreet 6.1, DTS Matrix and Matrix 3.0,
DTS 96/24® , DTS NEO:6
THX® Ultra, Select, Ultra2, 5.1, 7.1, EX
SRS® Labs Circle Surround IITM , Virtual Loudspeaker
MPEG AAC, MPEG2 Decode, MPEG 2-Channel Decode
PCM, PCM 96 kHz
HDCD, MLP*
Delay 7.1, 96 kHz
Bass 7.1, 96 kHz, Bass/Treble 2 Channel
ADI Surround: Club, Music, and Stadium
AAC (LC), AAC (LC) 2 Channel, AAC MP
WaveSurround 5.1 Channel to Headphone, Stereo to
Headphone, Channel to Loudspeaker, Stereo to
Loudspeaker
Downsampling 96 kHz to 48 kHz (2-Channel)
3-Band Equalizer, 2-Channel
Encoders: AC-3 2-Channel Consumer Encoder
Single Chip DSP-Based Implementation of Digital Audio
Algorithms2 S Compatible Ports
Interface to External SDRAM
Easy Interfaces to Audio Codecs
96 kHz Processing
Supports Customer Specific Post Processing
Automatic Stream Detection and Code Loading
Easy to Use Software Architecture
Optimized Library of Routines
Host Communication Using 16-Bit Parallel Port or SPI Port
Highly Flexible Serial Ports
SRAM Interface for More Delay
Supports IEC60958 For Bit Streams
8-Channel Output Using TDM Codecs
APPLICATIONS
Home Theater AVR Systems
Automotive Audio Receivers
Video Game Consoles
DVD Players
Cable and Satellite Set-Top Boxes
Multimedia Audio/Video Gateways
Melody and SHARC are registered trademarks of Analog Devices, Inc.
DTS, DTS-ES, and DTS 96/24 are registered trademarks of Digital Theater
Systems, Inc.
Dolby and Pro Logic are registered trademarks of Dolby Laboratories
Licensing Corporation.
SRS is a registered trademark and Circle Surround II is a trademark of SRS Labs.
THX is a registered trademark of the THX, Ltd.
*MLP is implemented, not certified.
FUNCTIONAL BLOCK DIAGRAM
SST -Melody-SHARC–SPECIFICATIONS
RECOMMENDED OPERATING CONDITIONS1
NOTES See Environmental Conditions section for information on thermal specifications. Applies to input and bidirectional pins: DATA31–0, ADDR23–0, BSEL, RD, WR, SW, ACK, SBTS, IRQ2–0, FLAG11–0, HBG, CS, DMAR1, DMAR2, BR2–1, ID2–0,
RPBA, CPA, TFS0, TFS1, RFS0, RFS1, BMS, TMS, TDI, TCK, HBR, DR0A, DR1A, DR0B, DR1B, TCLK0, TCLK1, RCLK0, RCLK1, RESET, TRST,
PWM_EVENT0, PWM_EVENT1, RAS, CAS, SDWE, SDCKE. Applies to input pin CLKIN.
ELECTRICAL CHARACTERISTICS
VOL
IIH
NOTES
1 Applies to output and bidirectional pins: DATA31–0, ADDR 23–0, MS3–0, RD, WR, SW, ACK, FLAG11–0, HBG, REDY, DMAG1, DMAG2, BR2–1, CPA,
TCLK0, TCLK1, RCLK0, RCLK1, TFS0, TFS1, RFS0, RFS1, DT0A, DT1A, DT0B, DT1B, XTAL, BMS, TDO, EMU, BMSTR, PWM_EVENT0,
PWM_EVENT1, RAS, CAS, DQM, SDWE, SDCLK0, SDCLK1, SDCKE, SDA10.
2 See Output Drive Current section for typical drive current capabilities.
3 Applies to input pins: ACK, SBTS, IRQ2–0, HBR, CS, DMAR1, DMAR2, ID1–0, BSEL, CLKIN, RESET, TCK (Note that ACK is pulled up internally with 2kΩ
during reset in a multiprocessor system, when ID1–0 = 01 and another SST-Melody-SHARC is not requesting bus mastership).
4 Applies to input pins with internal pull-ups: DR0A, DR1A, DR0B, DR1B, TRST, TMS, TDI.
5 Applies to three-statable pins: DATA31–0, ADDR 23–0, MS3–0, RD, WR, SW, ACK, FLAG11–0, REDY, HBG, DMAG1, DMAG2, BMS, TDO, RAS, CAS,
DQM, SDWE, SDCLK0, SDCLK1, SDCKE, SDA10, and EMU (note that ACK is pulled up internally with2 kΩ during reset in a multiprocessor system,
when ID1–0 = 01 and another SST-Melody-SHARC is not requesting bus mastership).
6 Applies to three-statable pins with internal pull-ups: DT0A, DT1A, DT0B, DT1B, TCLK0, TCLK1, RCLK0, RCLK1.
7 Applies to CPA pin.
8 Applies to ACK pin when pulled up.
9 Applies to ACK pin when keeper latch enabled. Guaranteed but not tested. Applies to all signal pins.
Specifications subject to change without notice.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although the
SST-Melody-SHARC features proprietary ESD protection circuitry, permanent damage may occur
on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
ABSOLUTE MAXIMUM RATINGS*
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +4.6 V
Input Voltage . . . . . . . . . . . . . . . . . . . . . –0.5 V to VDD + 0.5 V
Output Voltage Swing . . . . . . . . . . . . . . –0.5 V to VDD + 0.5 V
Load Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 pF
Junction Temperature Under Bias . . . . . . . . . . . . . . . . . 130°C
Storage Temperature Range . . . . . . . . . . . . . –65°C to +150°C
Lead Temperature (5 seconds) . . . . . . . . . . . . . . . . . . . . 280°C
*Stresses greater than those listed under Absolute Maximum Ratings may cause
permanent damage to the device. These are stress ratings only; functional opera-
tion of the device at these or any other conditions greater than those indicated in
the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
ORDERING GUIDE
Part Number
ADSST-21065LKS-240
ADSST-21065LCS-240
ADSST-21065LKCA-240
ADSST-21065LKS-264
ADSST-21065LKCA-264
SST-Melody-SHARC
208-LEAD MQFP PIN CONFIGURATIONS
BMSTR
VDD
SBTS
GND
GNDVDDGND
REDY
CPAVDDVDDGNDACK
MS0MS1
GNDGND
MS2MS3
FLAG11
VDD
FLAG10
FLAG9FLAG8
GND
DATA0DATA1DATA2
VDD
DATA3DATA4DATA5
GND
DATA6DATA7DATA8
VDDGNDVDD
DATA9
DATA10DATA11
GND
DATA12DATA13NC
DATA14IRQ2IRQ1IRQ0GNDNCNCFLAG3
VDDVDD
RSF0
GND
RCLK0
DR0A
DR0B
TFS0
TCLK0
VDD
GND
DT0A
DT0B
RFS1
GND
RCLK1
DR1A
DR1B
TFS1
TCLK1
VDD
VDD
DT1A
DT1B
PWM
GND
PWM EVENT0
BR1
BR2
VDD
CLKIN
XTAL
VDD
GND
SDCLK1
GND
VDD
SDCLK0
DMAR1
DMAR2
HBR
GND
RAS
SDWE
VDD
DQM
SDCKE
SDA10
GND
DMAG1
DMAG2
HBG
GND
GND
BMS
BSEL
TCK
GND
TMS
TDI
TRST
TDO
EMU
ID0
ID1
VDD
VDD
GND
GND
VDD
VDD
GND
GND
VDD
VDD
GND
GND
VDD
DATA15
GND
VDD
VDDFLAG2FLAG1FLAG0GNDADDR0ADDR1ADDR2VDDVDDADDR3ADDR4ADDR5GNDGNDADDR6ADDR7ADDR8VDDGNDADDR9ADDR10ADDR11GNDVDDADDR12ADDR13ADDR14VDDADDR15ADDR16ADDR17GND
GND
ADDR18ADDR19ADDR20VDDADDR21ADDR22ADDR23GNDVDDRESET
CAS
DATA16
DATA17
DATA18
DATA19
DATA20
DATA22
DATA21
DATA23
DATA24
DATA25
DATA26
DATA27
DATA28
DATA29
DATA30
DATA31
FLAG7
FLAG6
FLAG5
FLAG4
NC = NO CONNECT
196-BALL CSPBGA PIN CONFIGURATION
SST-Melody-SHARC
208-LEAD MQFP PIN CONFIGURATION
196-BALL CSPBGA PIN CONFIGURATION
A10
A12
A13
F12
F13
L10
L11
L12
L13
SST-Melody-SHARC
PIN FUNCTION DESCRIPTIONS
SST-Melody-SHARC pin definitions are listed below. Inputs identified as synchronous (S) must meet timing requirements with
respect to CLKIN (or with respect to TCK for TMS, TDI). Inputs identified as asynchronous (A) can be asserted asynchronously to
CLKIN (or to TCK for TRST).
Unused inputs should be tied or pulled to VDD or GND, except for ADDR23–0, DATA31–0, FLAG11–0, SW, and inputs that
have internal pull-up or pull-down resistors (CPA, ACK, DTxX, DRxX, TCLKx, RCLKx, TMS, and TDI), which can be left
floating. These pins have a logic-level hold circuit that prevents the input from floating internally.
DATA31–0
MS3–0
DMAR1
DMAR2
DMAG1
DMAG2
BR2–1
ID1–0
SST-Melody-SHARC
PIN FUNCTION DESCRIPTIONS (continued)
DQM
SDCLK1–0
SDCKE
SDA10
XTAL
PWM_EVENT1–0
I = Input, S = Synchronous, P = Power Supply, (O/D) = Open Drain, O = Output, A = Asynchronous, G = Ground, (A/D) = Active Drive, T = Three-state
(when SBTS is asserted, or when the SST-Melody-SHARC is a bus slave).

Partno	Mfg	Dc	Qty	Available	Descript
ADSST-21065LKS-240 \|ADSST21065LKS240	AD	N/a	460	avai	High End/ Multichannel/ 32-Bit Floating-Point Audio Processor