ADSP-TS201SABP-X ,500 MHz, 24 Mbit, Tiger SHARC embedded processorApplicationsPackagePerforms Exceptionally Well on DSP Algorithm and I/O Dual Computation Blocks—Eac ..
ADSP-TS201SABPZ060 , TigerSHARC-R Embedded Processor
ADSP-TS201SABPZ060 , TigerSHARC-R Embedded Processor
ADSP-TS201SYBPZ050 , TigerSHARC-R Embedded Processor
ADSP-TS201SYBPZ050 , TigerSHARC-R Embedded Processor
ADSP-TS202SABP-050 ,500 MHz TigerSHARC Processor with 12 Mbit on-chip embedded DRAMApplications25×25 mm (576-Ball) Thermally Enhanced Ball Grid Array Performs Exceptionally Well on D ..
AM26LS31CNSR ,Quadruple Differential Line DriverElectrical Characteristics ...... 512.2 Related Links.. 146.6 Switching Characteristics – AM26LS31. ..
AM26LS31MFKB ,Quadruple Differential Line Driver 20-LCCC -55 to 125Electrical Characteristics ...... 512.2 Related Links.. 146.6 Switching Characteristics – AM26LS31. ..
AM26LS31MJB ,Quadruple Differential Line Driver 16-CDIP -55 to 125Block Diagram..... 9Information..... 144 Revision HistoryNOTE: Page numbers for previous revisions ..
AM26LS31PC ,Quad Line Driver with NAND Enabled Three-State OutputsOrder this document by AM26LS31/D * * ** ** *The Motorola AM26LS31 is a quad differential line dr ..
AM26LS32 ,QUAD EIA-422/3 LINE RECEIVER WITH THREE.STATE OUTPUTSBlock DiagramInputs A+2 15–Inputs BThree–State+Outputs A 3 14Differential Control3–StateInputs Inpu ..
AM26LS32 ,QUAD EIA-422/3 LINE RECEIVER WITH THREE.STATE OUTPUTSElectrical Characteristics ofTHREE–STATE OUTPUTSBalanced/Unbalanced Voltage Digital Interface Circu ..
ADSP-TS201SABP-X
600 MHz, 24 Mbit, Tiger SHARC embedded processor
TigerSHARC and the TigerSHARC logo are registered trademarks of Analog Devices, Inc.
TigerSHARC®
Embedded Processor
Rev. PrH
KEY FEATURES
Up to 600MHz, 1.67ns Instruction Cycle Rate
24MBits of Internal—On-Chip—DRAM Memory
25×25mm (576-Ball) Thermally Enhanced Ball Grid Array
Package
Dual Computation Blocks—Each Containing an ALU, a Multi-
plier, a Shifter, a Register File, and a Communications Logic
Unit (CLU)
Dual Integer ALUs, providing Data Addressing and Pointer
Manipulation
Integrated I/O Includes 14Channel DMA Controller, External
Port, Four Link Ports, SDRAM Controller, Programmable
Flag Pins, Two Timers, and Timer Expired Pin for System
Integration
1149.1 IEEE Compliant JTAG Test Access Port for On-Chip
Emulation
On-Chip Arbitration for Glueless Multiprocessing
KEY BENEFITS
Provides High-Performance Static Superscalar DSP Opera-
tions, Optimized for Telecommunications Infrastructure
and Other Large, Demanding Multiprocessor DSP
Applications
Performs Exceptionally Well on DSP Algorithm and I/O
Benchmarks (See Benchmarks in Table1)
Supports Low-Overhead DMA Transfers Between Internal
Memory, External Memory, Memory-Mapped Peripherals,
Link Ports, Host Processors, and Other (Multiprocessor)
DSPs
Eases DSP Programming Through Extremely Flexible Instruc-
tion Set and High-Level-Language Friendly DSP
Architecture
Enables Scalable Multiprocessing Systems With Low Commu-
nications OverheadFigure 1.Functional block diagram
TABLE OF CONTENTSGeneral Description ................................................. 3
Dual Compute Blocks ............................................ 4
Data Alignment Buffer (DAB) .................................. 4
Dual Integer ALU (IALU) ....................................... 4
Program Sequencer ............................................... 5
Interrupt Controller ........................................... 5
Flexible Instruction Set ........................................ 5
DSP Memory ....................................................... 5
External Port
(Off-Chip Memory/Peripherals Interface) ................ 6
Host Interface ................................................... 6
Multiprocessor Interface ...................................... 7
SDRAM Controller ............................................ 7
EPROM Interface .............................................. 7
DMA Controller ................................................... 7
Link Ports (LVDS) ................................................ 8
Timer and General-Purpose I/O ............................... 9
Reset and Booting ................................................. 9
Clock Domains .................................................... 9
Power Domains .................................................... 9
Filtering Reference Voltage and Clocks ...................... 9
Development Tools ............................................. 10
Designing an Emulator-Compatible DSP Board(Target) 11
Additional Information ........................................ 11
Pin Function Descriptions ........................................ 12
Strap Pin Function Descriptions ................................ 19
ADSP-TS201S—Specifications ................................... 21
Recommended Operating Conditions ...................... 21
Electrical Characteristics ....................................... 21
Absolute Maximum Ratings ................................... 22
ESD Sensitivity ................................................... 22
Timing Specifications ........................................... 23
General AC Timing .......................................... 23
Link Port Low-Voltage, Differential-Signal (LVDS)
Electrical Characteristics and Timing ................. 27
Link Port—Data Out Timing ........................... 28
Link Port—Data In Timing .............................. 31
Output Drive Currents ......................................... 32
Test Conditions .................................................. 33
Output Disable Time ......................................... 33
Output Enable Time ......................................... 34
Capacitive Loading ........................................... 34
Environmental Conditions .................................... 36
Thermal Characteristics ..................................... 36
576-Ball BGA_ED Pin Configurations ......................... 36
Outline Dimensions ................................................ 40
Ordering Guide ..................................................... 40
REVISION HISTORY
Revision PrH:Applies corrections and additional information (includ-
ing information on 600MHz parts) to VREF Filtering
Scheme (page10), SCLK_VREF Filtering Scheme
(page10), Drive Strength/Output Impedance Selection
(page19), Recommended Operating Conditions
(page22), Electrical Characteristics (page22), Reference
Clocks (page24), Power-Up Reset Timing (page25), AC
Signal Specifications (page26), Link Port—Data Out
Timing (page29), Link Port—Data In Timing (page32),
and Ordering Guide (page42). Provides unused pin termination data in Pin Function
Descriptions (page13). Changes pins R2 and R3 to NC in 576-Ball (25 mm × 25
mm) BGA_ED Pin Assignments (page38).
GENERAL DESCRIPTIONThe ADSP-TS201S TigerSHARC processor is an ultra-high per-
formance, static superscalar processor optimized for large signal
processing tasks and communications infrastructure. The DSP
combines very wide memory widths with dual computation
blocks—supporting 32- and 40-bit floating-point and support-
ing 8-, 16-, 32-, and 64-bit fixed-point processing—to set a new
standard of performance for digital signal processors. The
TigerSHARC static superscalar architecture lets the DSP exe-
cute up to four instructions each cycle, performing twenty-four
16-bit fixed-point operations or six floating-point operations.
Four independent 128-bit wide internal data buses, each con-
necting to the six 4Mbit memory banks, enable quad-word
data, instruction, and I/O accesses and provide 33.6Gbytes per
second of internal memory bandwidth. Operating at 600MHz,
the ADSP-TS201S processor’s core has a 1.67ns instruction
cycle time. Using its Single-Instruction, Multiple-Data (SIMD)
features, the ADSP-TS201S processor can perform 4.8 billion
40-bit MACs or 1.2 billion 80-bit MACs per second. Table1
shows the DSP’s performance benchmarks.
The ADSP-TS201S processor is code-compatible with the other
TigerSHARC processors.
The Functional Block Diagram onpage1 shows the ADSP-
TS201S processor’s architectural blocks. These blocks include:Dual compute blocks, each consisting of an ALU, multi-
plier, 64-bit shifter, 128-bit CLU, and 32-word register file
and associated Data Alignment Buffers (DABs) Dual integer ALUs (IALUs), each with its own 31-word
register file for data addressing and a status registerA program sequencer with Instruction Alignment Buffer
(IAB) and Branch Target Buffer (BTB)An interrupt controller that supports hardware and soft-Four 128-bit internal data buses, each connecting to the six bit memory banksOn-chip DRAM (24Mbit)An external port that provides the interface to host proces-
sors, multiprocessing space (DSPs), off-chip memory-
mapped peripherals, and external SRAM and SDRAMA 14 channel DMA controllerFour full-duplex LVDS link portsTwo 64-bit interval timers and timer expired pinA 1149.1 IEEE compliant JTAG test access port for on-chip
emulation
Figure2 on page3 shows a typical single-processor system with
external SRAM and SDRAM. Figure3 on page6 shows a typical
multiprocessor system.
The TigerSHARC DSP uses a Static Superscalar* architecture.
This architecture is superscalar in that the ADSP-TS201S pro-
cessor’s core can execute simultaneously from one to four 32-bit
instructions encoded in a Very Large Instruction Word (VLIW)
instruction line using the DSP’s dual compute blocks. Because
Table 1.General Purpose Algorithm Benchmarks
at 600 MHz Cache preloaded
Figure 2.ADSP-TS201S Single-Processor System With External SDRAM
the DSP does not perform instruction re-ordering at runtime—
the programmer selects which operations will execute in parallel
prior to runtime—the order of instructions is static.
With few exceptions, an instruction line, whether it contains
one, two, three, or four 32-bit instructions, executes with a
throughput of one cycle in a ten-deep processor pipeline.
For optimal DSP program execution, programmers must follow
the DSP’s set of instruction parallelism rules when encoding an
instruction line. In general, the selection of instructions that the
DSP can execute in parallel each cycle depends on the instruc-
tion line resources each instruction requires and on the source
and destination registers used in the instructions. The program-
mer has direct control of three core components—the IALUs,
the compute blocks, and the program sequencer.
The ADSP-TS201S processor, in most cases, has a two-cycle
execution pipeline that is fully interlocked, so—whenever a
computation result is unavailable for another operation depen-
dent on it—the DSP automatically inserts one or more stall
cycles as needed. Efficient programming with dependency-free
instructions can eliminate most computational and memory
transfer data dependencies.
In addition, the ADSP-TS201S processor supports SIMD opera-
tions two ways—SIMD compute blocks and SIMD
computations. The programmer can load both compute blocks
with the same data (broadcast distribution) or different data
(merged distribution).
DUAL COMPUTE BLOCKSThe ADSP-TS201S processor has compute blocks that can exe-
cute computations either independently or together as a Single-
Instruction, Multiple-Data (SIMD) engine. The DSP can issue
up to two compute instructions per compute block each cycle,
instructing the ALU, multiplier, shifter, or CLU to perform
independent, simultaneous operations. Each compute block can
execute eight 8-bit, four 16-bit, two 32-bit, or one 64-bit SIMD
computations in parallel with the operation in the other block.
The compute blocks are referred to as X and Y in assembly syn-
tax, and each block contains four computational units—an
ALU, a multiplier, a 64-bit shifter, a 128-bit CLU—and a 32-
word register file.Register File—Each Compute Block has a multiported 32-
word, fully orthogonal register file used for transferring
data between the computation units and data buses and for
storing intermediate results. Instructions can access the
registers in the register file individually (word-aligned), in
sets of two (dual-aligned), or in sets of four (quad-aligned).ALU—The ALU performs a standard set of arithmetic
operations in both fixed- and floating-point formats. It also
performs logic operations.Multiplier—The multiplier performs both fixed- and float-
ing-point multiplication and fixed-point multiply and
accumulate.Shifter—The 64-bit shifter performs logical and arithmetic
shifts, bit and bitstream manipulation, and field deposit
and extraction operations.Communications Logic Unit (CLU)—This is a 128-bit unit
provides Trellis Decoding (for example, Viterbi and Turbo
decoders) and executes complex correlations for CDMA
communication applications (for example chip-rate and
symbol-rate functions).
Using these features, the compute blocks can:Provide 8 MACs per cycle peak and 7.1 MACs per cycle
sustained 16-bit performance and provide 2 MACs per
cycle peak and 1.8 MACs per cycle sustained 32-bit perfor-
mance (based on FIR) Execute six single-precision floating-point or execute
twenty-four 16-bit fixed-point operations per cycle, pro-
viding 3GFLOPS or 12.0GOPS performancePerform two complex 16-bit MACs per cycleExecute eight Trellis butterflies in one cycle
DATA ALIGNMENT BUFFER (DAB)The DAB is a quad-word FIFO that enables loading of quad-
word data from nonaligned addresses. Normally, load instruc-
tions must be aligned to their data size so that quad words are
loaded from a quad-aligned address. Using the DAB signifi-
cantly improves the efficiency of some applications, such as FIR
filters.
DUAL INTEGER ALU (IALU)The ADSP-TS201S processor has two IALUs that provide pow-
erful address generation capabilities and perform many general-
purpose integer operations. The IALUs are referred to as J and
K in assembly syntax and have the following features:Provides memory addresses for data and update pointersSupports circular buffering and bit-reverse addressingPerforms general-purpose integer operations, increasing
programming flexibilityIncludes a 31-word register file for each IALU
As address generators, the IALUs perform immediate or indi-
rect (pre- and post-modify) addressing. They perform modulus
and bit-reverse operations with no constraints placed on mem-
ory addresses for the modulus data buffer placement. Each
IALU can specify either a single-, dual-, or quad-word access
from memory.
The IALUs have hardware support for circular buffers, bit
reverse, and zero-overhead looping. Circular buffers facilitate
efficient programming of delay lines and other data structures
required in digital signal processing, and they are commonly
used in digital filters and Fourier transforms. Each IALU pro-
vides registers for four circular buffers, so applications can set
up a total of eight circular buffers. The IALUs handle address
pointer wraparound automatically, reducing overhead, increas-
ing performance, and simplifying implementation. Circular
Because the IALU’s computational pipeline is one cycle deep, in
most cases integer results are available in the next cycle. Hard-
ware (register dependency check) causes a stall if a result is
unavailable in a given cycle.
PROGRAM SEQUENCERThe ADSP-TS201S processor’s program sequencer supports the
following:A fully interruptible programming model with flexible pro-
gramming in assembly and C/C++ languages; handles
hardware interrupts with high throughput and no aborted
instruction cyclesA ten-cycle instruction pipeline—four-cycle fetch pipe and
six-cycle execution pipe—computation results available
two cycles after operands are availableSupply of instruction fetch memory addresses; the
sequencer’s Instruction Alignment Buffer (IAB) caches up
to five fetched instruction lines waiting to execute; the pro-
gram sequencer extracts an instruction line from the IAB
and distributes it to the appropriate core component for
executionManagement of program structures and program flow
determined according to JUMP, CALL, RTI, RTS instruc-
tions, loop structures, conditions, interrupts, and software
exceptionsBranch prediction and a 128-entry branch target buffer
(BTB) to reduce branch delays for efficient execution of
conditional and unconditional branch instructions and
zero-overhead looping; correctly predicted branches that
are taken occur with zero overhead cycles, overcoming the
five-to-nine stage branch penaltyCompact code without the requirement to align code in
memory; the IAB handles alignment
Interrupt ControllerThe DSP supports nested and nonnested interrupts. Each inter-
rupt type has a register in the interrupt vector table. Also, each
has a bit in both the interrupt latch register and the interrupt
mask register. All interrupts are fixed as either level-sensitive or
edge-sensitive, except the IRQ3–0 hardware interrupts, which
are programmable.
The DSP distinguishes between hardware interrupts and soft-
ware exceptions, handling them differently. When a software
exception occurs, the DSP aborts all other instructions in the
instruction pipe. When a hardware interrupt occurs, the DSP
continues to execute instructions already in the instruction pipe.
Flexible Instruction SetThe 128-bit instruction line, which can contain up to four 32-bit
instructions, accommodates a variety of parallel operations for
concise programming. For example, one instruction line can
direct the DSP to conditionally execute a multiply, an add, and a
subtract in both computation blocks while it also branches to
another location in the program. Some key features of the
instruction set include:CLU instructions for communications infrastructure to
govern Trellis Decoding (for example, Viterbi and Turbo
decoders) and Despreading via complex correlationsAlgebraic assembly language syntaxDirect support for all DSP, imaging, and video arithmetic
typesEliminates toggling DSP hardware modes because modes
are supported as options (for example, rounding, satura-
tion, and others) within instructionsBranch prediction encoded in instruction; enables zero-
overhead loopsParallelism encoded in instruction lineConditional execution optional for all instructionsUser defined partitioning between program and data
memory
DSP MEMORYThe DSP’s internal and external memory is organized into a
unified memory map, which defines the location (address) of all
elements in the system, as shown in Figure3.
The memory map is divided into four memory areas—host
space, external memory, multiprocessor space, and internal
memory—and each memory space, except host memory, is sub-
divided into smaller memory spaces.
The ADSP-TS201S processor internal memory has 24Mbits of
on-chip DRAM memory, divided into six blocks of 4Mbits
(128Kwords×32bits). Each block—M0, M2, M4, M6, M8, and
M10—can store program, data, or both, so applications can
configure memory to suit specific needs. Placing program
instructions and data in different memory blocks, however,
enables the DSP to access data while performing an instruction
fetch. Each memory segment contains a 128K bit cache to
enable single cycle accesses to internal DRAM.
The six internal memory blocks connect to the four 128-bit wide
internal buses through a crossbar connection, enabling the DSP
to perform four memory transfers in the same cycle. The DSP’s
internal bus architecture provides a total memory bandwidth of
33.6Gbytes per second, enabling the core and I/O to access
eight 32-bit data words and four 32-bit instructions each cycle.
The DSP’s flexible memory structure enables:DSP core and I/O accesses to different memory blocks in
the same cycleDSP core access to three memory blocks in parallel—one
instruction and two data accessesProgrammable partitioning of program and data memoryProgram access of all memory as 32-, 64-, or 128-bit
words—16-bit words with the DAB
EXTERNAL PORT
(OFF-CHIP MEMORY/PERIPHERALS INTERFACE)The ADSP-TS201S processor’s external port provides the DSP’s
interface to off-chip memory and peripherals. The 4Gword
address space is included in the DSP’s unified address space.
The separate on-chip buses—four 128-bit data buses and four
32-bit address buses—are multiplexed at the SOC interface and
transferred to the external port over the SOC bus to create an
external system bus transaction. The external system bus pro-
vides a single 64-bit data bus and a single 32-bit address bus.
The external port supports data transfer rates of 1Gbytes per
second over the external bus.
The external bus can be configured for 32- or 64-bit, little-
endian operations. When the system bus is configured for 64-bit
operations, the lower 32 bits of the external data bus connect to
The external port supports pipelined, slow, and SDRAM proto-
cols. Addressing of external memory devices and memory-
mapped peripherals is facilitated by on-chip decoding of high-
order address lines to generate memory bank select signals.
The ADSP-TS201S processor provides programmable memory,
pipeline depth, and idle cycle for synchronous accesses, and
external acknowledge controls to support interfacing to pipe-
lined or slow devices, host processors, and other memory-
mapped peripherals with variable access, hold, and disable time
requirements.
Host InterfaceThe ADSP-TS201S processor provides an easy and configurable
Figure 3.ADSP-TS201S Memory Map
the host interface supports pipelined or slow protocols for
ADSP-TS201S processor accesses of the host as slave or pipe-
lined for host accesses of the ADSP-TS201S processor as slave.
Each protocol has programmable transmission parameters,
such as idle cycles, pipe depth, and internal wait cycles.
The host interface supports burst transactions initiated by a host
processor. After the host issues the starting address of the burst
and asserts the BRST signal, the DSP increments the address
internally while the host continues to assert BRST.
The host interface provides a deadlock recovery mechanism that
enables a host to recover from deadlock situations involving the
DSP. The BOFF signal provides the deadlock recovery mecha-
nism. When the host asserts BOFF, the DSP backs off the
current transaction and asserts HBG and relinquishes the exter-
nal bus.
The host can directly read or write the internal memory of the
ADSP-TS201S processor, and it can access most of the DSP reg-
isters, including DMA control (TCB) registers. Vector
interrupts support efficient execution of host commands.
Multiprocessor InterfaceThe ADSP-TS201S processor offers powerful features tailored
to multiprocessing DSP systems through the external port and
link ports. This multiprocessing capability provides highest
bandwidth for interprocessor communication, including:Up to eight DSPs on a common busOn-chip arbitration for glueless multiprocessingLink ports for point to point communication
The external port and link ports provide integrated, glueless
multiprocessing support.
The external port supports a unified address space (see Figure3)
that enables direct interprocessor accesses of each ADSP-
TS201S processor’s internal memory and registers. The DSP’s
on-chip distributed bus arbitration logic provides simple, glue-
less connection for systems containing up to eight ADSP-
TS201S processors and a host processor. Bus arbitration has a
rotating priority. Bus lock supports indivisible read-modify-
write sequences for semaphores. A bus fairness feature prevents
one DSP from holding the external bus too long.
The DSP’s four link ports provide a second path for interproces-
sor communications with throughput of 4Gbytes per second.
The cluster bus provides 1Gbytes per second throughput—with
a total of 4.8Gbytes per second interprocessor bandwidth (lim-
ited by SOC bandwidth).
SDRAM ControllerThe SDRAM controller controls the ADSP-TS201S processor’s
transfers of data to and from external synchronous DRAM
(SDRAM) at a throughput of 32 or 64 bits per SCLK cycle using
the external port and SDRAM control pins.
The SDRAM interface provides a glueless interface with stan-
dard SDRAMs—16Mbit, 64Mbit, 128Mbit, and 256Mbit. The
DSP supports directly a maximum of four banks of
64Mwords×32bit of SDRAM. The SDRAM interface is
mapped in external memory in each DSP’s unified memory
map.
EPROM InterfaceThe ADSP-TS201S processor can be configured to boot from an
external 8-bit EPROM at reset through the external port. An
automatic process (which follows reset) loads a program from
the EPROM into internal memory. This process uses sixteen
wait cycles for each read access. During booting, the BMS pin
functions as the EPROM chip select signal. The EPROM boot
procedure uses DMA channel 0, which packs the bytes into 32-
bit instructions. Applications can also access the EPROM (write
flash memories) during normal operation through DMA.
The EPROM or Flash Memory interface is not mapped in the
DSP’s unified memory map. It is a byte address space limited to
a maximum of 16Mbytes (twenty-four address bits). The
EPROM or Flash Memory interface can be used after boot via a
DMA.
DMA CONTROLLERThe ADSP-TS201S processor’s on-chip DMA controller, with
14 DMA channels, provides zero-overhead data transfers with-
out processor intervention. The DMA controller operates
independently and invisibly to the DSP’s core, enabling DMA
operations to occur while the DSP’s core continues to execute
program instructions.
The DMA controller performs DMA transfers between internal
memory and external memory and memory-mapped peripher-
als, the internal memory of other DSPs on a common bus, a host
processor, or link port I/O; between external memory and exter-
nal peripherals or link port I/O; and between an external bus
master and internal memory or link port I/O. The DMA con-
troller performs the following DMA operations:External port block transfers. Four dedicated bidirectional
DMA channels transfer blocks of data between the DSP’s
internal memory and any external memory or memory-
mapped peripheral on the external bus. These transfers
support master mode and handshake mode protocols.Link port transfers. Eight dedicated DMA channels (four
transmit and four receive) transfer quad-word data only
between link ports and between a link port and internal or
external memory. These transfers only use handshake
mode protocol. DMA priority rotates between the four
receive channels. AutoDMA transfers. Two dedicated unidirectional DMA
channels transfer data received from an external bus master
to internal memory or to link port I/O. These transfers only
use slave mode protocol, and an external bus master must
initiate the transfer.
The DMA controller provides these additional features:Flyby transfers. Flyby operations only occur through the
external port (DMA channel 0) and do not involve the
DSP’s core. The DMA controller acts as a conduit to trans-
data bus; outputs addresses, memory selects (MSSD3–0)
and the IORD, IOWR, IOEN, and RD/WR strobes; and
responds to ACK.DMA chaining. DMA chaining operations enable applica-
tions to automatically link one DMA transfer sequence to
another for continuous transmission. The sequences can
occur over different DMA channels and have different
transmission attributes.Two-dimensional transfers. The DMA controller can
access and transfer two-dimensional memory arrays on any
DMA transmit or receive channel. These transfers are
implemented with index, count, and modify registers for
LINK PORTS (LVDS)The DSP’s four full-duplex link ports each provide additional
four-bit receive and four-bit transmit I/O capability, using Low-
Voltage, Differential-Signal (LVDS) technology. With the abil-
ity to operate at a double data rate—latching data on both the
rising and falling edges of the clock—running at up to 500MHz,
each link port can support up to 500Mbytes per second per
direction, for a combined maximum throughput of 4Gbytes per
second.
The link ports provide an optional communications channel
that is useful in multiprocessor systems for implementing point-
to-point interprocessor communications. Applications can also
Figure 4.ADSP-TS201S Shared Memory Multiprocessing System
Each link port has its own triple-buffered quad-word input and
double-buffered quad-word output registers. The DSP’s core
can write directly to a link port’s transmit register and read from
a receive register, or the DMA controller can perform DMA
transfers through eight (four transmit and four receive) dedi-
cated link port DMA channels.
Each link port direction has three signals that control its opera-
tion. For the transmitter, LxCLKOUT is the output transmit
clock, LxACKI is the handshake input to control the data flow,
and the LxBCMPO output indicates that the block transfer is
complete. For the receiver, LxCLKIN is the input receive clock,
LxACKO is the handshake output to control the data flow, and
the LxBCMPI input indicates that the block transfer is com-
plete. The LxDATO3–0 pins are the data output bus for the
transmitter and the LxDATI3–0 pins are the input data bus for
the receiver.
Applications can program separate error detection mechanisms
for transmit and receive operations (applications can use the
checksum mechanism to implement consecutive link port
transfers), the size of data packets, and the speed at which bytes
are transmitted.
TIMER AND GENERAL-PURPOSE I/OThe ADSP-TS201S processor has a timer pin (TMR0E) that
generates output when a programmed timer counter has
expired and four programmable general-purpose I/O pins
(FLAG3–0) that can function as either single-bit input or out-
put. As outputs, these pins can signal peripheral devices; as
inputs, they can provide the test for conditional branching.
RESET AND BOOTINGThe ADSP-TS201S processor has three levels of reset:Power-up reset—After power-up of the system (SCLK, all
static inputs, and strap pins are stable), the RST_IN pin
must be asserted (low). Normal reset—For any chip reset following the power-up
reset, the RST_IN pin must be asserted (low). DSP-core reset—When setting the SWRST bit in
EMUCTL, the DSP core is reset, but not the external port
or I/O.
For normal operations, tie the RST_OUT pin to the POR_IN
pin.
After reset, the ADSP-TS201S processor has four boot options
for beginning operation:
•Boot from EPROM.Boot by an external master (host or another ADSP-TS201S
processor).
•Boot by link port.No boot—Start running from memory address selected
with one of the IRQ3–0 interrupt signals. See Table2.
Using the ‘no boot’ option, the ADSP-TS201S processor must
start running from memory when one of the interrupts is
asserted.
The ADSP-TS201S processor core always exits from reset in the
idle state and waits for an interrupt. Some of the interrupts in
the interrupt vector table are initialized and enabled after reset.
For more information on boot options, see the EE-174: ADSP-
TS101S Booting Methods on the Analog Devices website
()
CLOCK DOMAINSThe DSP uses calculated ratios of the SCLK clock to operate as
shown in Figure5. The instruction execution rate is equal to
CCLK. A PLL from SCLK generates CCLK which is phase-
locked. The SCLKRATx pins define the clock multiplication of
SCLK to CCLK (see Table4 on page13). The link port clock is
generated from CCLK via a software programmable divisor, and
the SOC bus operates at 1/2 CCLK. Memory transfers to exter-
nal and link port buffers operate at the SOCCLK rate. SCLK also
provides clock input for the external bus interface and defines
the AC specification reference for the external bus signals. The
external bus interface runs at the SCLK frequency. The maxi-
mum SCLK frequency is one quarter the internal DSP clock
(CCLK) frequency.
POWER DOMAINSThe ADSP-TS201S processor has separate power supply con-
nections for internal logic (VDD), analog circuits (VDD_A), I/O
buffer (VDD_IO), and internal DRAM (VDD_DRAM) power supply.
Note that the analog (VDD_A) supply powers the clock generator
PLLs. To produce a stable clock, systems must provide a clean
power supply to power input VDD_A. Designs must pay critical
attention to bypassing the VDD_A supply.
Table 2.No Boot, Run From Memory AddressesFigure 5.Clock Domains
FILTERING REFERENCE VOLTAGE AND CLOCKSFigure6 and Figure7 show possible circuits for filtering VREF,
and SCLK_VREF. These circuits provide the reference voltages
for the switching voltage reference and system clock reference.
DEVELOPMENT TOOLSThe ADSP-TS201S processor is supported with a complete set
of CROSSCORE† software and hardware development tools,
including Analog Devices emulators and VisualDSP++‡ devel-
opment environment. The same emulator hardware that
supports other TigerSHARC processors also fully emulates the
ADSP-TS201S processor.
The VisualDSP++ project management environment lets pro-
grammers develop and debug an application. This environment
includes an easy to use assembler (which is based on an alge-
braic syntax), an archiver (librarian/library builder), a linker, a
loader, a cycle-accurate instruction-level simulator, a C/C++
compiler, and a C/C++ runtime library that includes DSP and
mathematical functions. A key point for theses tools is C/C++
code efficiency. The compiler has been developed for efficient
translation of C/C++ code to DSP assembly. The DSP has archi-
tectural features that improve the efficiency of compiled C/C++
code.
The VisualDSP++ debugger has a number of important fea-
tures. Data visualization is enhanced by a plotting package that
offers a significant level of flexibility. This graphical representa-
tion of user data enables the programmer to quickly determine
the performance of an algorithm. As algorithms grow in com-
plexity, this capability can have increasing significance on the
designer’s development schedule, increasing productivity. Sta-
tistical profiling enables the programmer to nonintrusively poll
the processor as it is running the program. This feature, unique
to VisualDSP++, enables the software developer to passively
gather important code execution metrics without interrupting
the realtime characteristics of the program. Essentially, the
developer can identify bottlenecks in software quickly and effi-
ciently. By using the profiler, the programmer can focus on
those areas in the program that impact performance and take
corrective action.
Debugging both C/C++ and assembly programs with the
VisualDSP++ debugger, programmers can:View mixed C/C++ and assembly code (interleaved source
and object information)Insert breakpointsSet conditional breakpoints on registers, memory,
andstacksTrace instruction executionPerform linear or statistical profiling of program executionFill, dump, and graphically plot the contents of memoryPerform source level debuggingCreate custom debugger windows
The VisualDSP++ IDE lets programmers define and manage
DSP software development. Its dialog boxes and property pages
let programmers configure and manage all of the TigerSHARC
processor development tools, including the color syntax high-
lighting in the VisualDSP++ editor. This capability permit
programmers to:Control how the development tools process inputs and
generate outputsMaintain a one-to-one correspondence with the tool’s
command line switches
The VisualDSP++™ Kernel (VDK) incorporates scheduling and
resource management tailored specifically to address the mem-
ory and timing constraints of DSP programming. These
capabilities enable engineers to develop code more effectively,
eliminating the need to start from the very beginning, when
developing new application code. The VDK features include
Threads, Critical and Unscheduled regions, Semaphores,
Events, and Device flags. The VDK also supports Priority-based,
Preemptive, Cooperative and Time -Sliced scheduling
approaches. In addition, the VDK was designed to be scalable. If
the application does not use a specific feature, the support code
for that feature is excluded from the target system.
Because the VDK is a library, a developer can decide whether to
use it or not. The VDK is integrated into the VisualDSP++™
Figure 6.VREF Filtering Scheme
Figure 7.SCLK_VREF Filtering Scheme
command line tools. When the VDK is used, the development
environment assists the developer with many error-prone tasks
and assists in managing system resources, automating the gen-
eration of various VDK based objects, and visualizing the
system state, when debugging an application that uses the VDK.
VCSE is Analog Devices’ technology for creating, using, and
reusing software components (independent modules of sub-
stantial functionality) to quickly and reliably assemble software
applications. Download components from the Web and drop
them into the application. Publish component archives from
within VisualDSP++™. VCSE supports component implementa-
tion in C/C++ or assembly language.
Use the Expert Linker to visually manipulate the placement of
code and data on the embedded system. View memory utiliza-
tion in a color-coded graphical form, easily move code and data
to different areas of the DSP or external memory with the drag
of the mouse, examine run-time stack and heap usage. The
Expert Linker is fully compatible with existing Linker Definition
File (LDF), allowing the developer to move between the graphi-
cal and textual environments.
Analog Devices DSP emulators use the IEEE 1149.1 JTAG Test
Access Port of the ADSP-TS201S processor to monitor and con-
trol the target board processor during emulation. The emulator
provides full speed emulation, allowing inspection and modifi-
cation of memory, registers, and processor stacks. Nonintrusive
in-circuit emulation is assured by the use of the processor’s
JTAG interface—the emulator does not affect target system
loading or timing.
In addition to the software and hardware development tools
available from Analog Devices, third parties provide a wide
range of tools supporting the TigerSHARC processor family.
Hardware tools include TigerSHARC processor PC plug-in
cards. Third party software tools include DSP libraries, real-
time operating systems, and block diagram designtools.
DESIGNING AN EMULATOR-COMPATIBLE DSP
BOARD(TARGET)The Analog Devices family of emulators are tools that every
DSP developer needs to test and debug hardware and software
systems. Analog Devices has supplied an IEEE 1149.1 JTAG
Test Access Port (TAP) on each JTAG DSP. The emulator uses
the TAP to access the internal features of the DSP, allowing the
developer to load code, set breakpoints, observe variables,
observe memory, and examine registers. The DSP must be
halted to send data and commands, but once an operation has
been completed by the emulator, the DSP system is set running
at full speed with no impact on system timing.
To use these emulators, the target board must include a header
that connects the DSP’s JTAG port to the emulator.
For details on target board design issues including mechanical
layout, single processor connections, multiprocessor scan
chains, signal buffering, signal termination, and emulator pod
logic, see the EE-68: Analog Devices JTAG Emulation Technical
Reference on the Analog Devices website ()—
use site search on “EE-68”. This document is updated regularly
ADDITIONAL INFORMATIONThis data sheet provides a general overview of the ADSP-
TS201S processor’s architecture and functionality. For detailed
information on the ADSP-TS201S processor’s core architecture
and instruction set, see the ADSP-TS201 TigerSHARC Processor
Hardware Reference and the ADSP-TS201 TigerSHARC Proces-
sor Programming Reference. For detailed information on the
development tools for this processor, see the VisualDSP++
User’s Guide for TigerSHARC Processors.
PIN FUNCTION DESCRIPTIONSWhile most of the ADSP-TS201S processor’s input pins are nor-
mally synchronous—tied to a specific clock—a few are
asynchronous. For these asynchronous signals, an on-chip syn-
chronization circuit prevents metastability problems. Use the
AC specification for asynchronous signals when the system
design requires predictable, cycle-by-cycle behavior for these
signals.
The output pins can be three-stated during normal operation.
The DSP three-states all outputs during reset, allowing these
pins to get to their internal pullup or pulldown state. Some pins
have an internal pullup or pulldown resistor (±30% tolerance)
that maintains a known value during transitions between differ-
ent drivers.
Table 3.Pin Definitions—Clocks and Reset
I = input; A = asynchronous; O = output; OD = open drain output; T = Three-State; P = power supply; G = ground;
pd = internal pulldown 5kΩ; pu = internal pullup 5kΩ; pd_0 = internal pulldown 5kΩ on DSP ID=0; pu_0 = internal pullup 5kΩ on DSP
ID=0; pu_od_0 = internal pullup 500Ω on DSP ID=0; pd_m = internal pulldown 5kΩ on DSP bus master; pu_m = internal pullup 5kΩ on DSP
bus master; pu_ad = internal pullup 40kΩ; For more pulldown and pullup information, see Electrical Characteristics on page22.
Term (for termination) column symbols: epd = External pull-down approximately 5kΩ to VSS; epu = External pull-up approximately 5kΩ
to VDD_IO, nc = Not connected; au = Always used.For more information on SCLK and SCLK_VREF on revision 0.x silicon, see the EE-179: ADSP-TS20x TigerSHARC System Design Guidelines on the Analog Devices website
().
Table 4.SCLK Ratio
Table 5.Pin Definitions—External Port Bus Controls
I = input; A = asynchronous; O = output; OD = open drain output; T = Three-State; P = power supply; G = ground;
pd = internal pulldown 5kΩ; pu = internal pullup 5kΩ; pd_0 = internal pulldown 5kΩ on DSP ID=0; pu_0 = internal pullup 5kΩ on DSP
ID=0; pu_od_0 = internal pullup 500Ω on DSP ID=0; pd_m = internal pulldown 5kΩ on DSP bus master; pu_m = internal pullup 5kΩ on DSP
bus master; pu_ad = internal pullup 40kΩ; For more pulldown and pullup information, see Electrical Characteristics on page22.
Term (for termination) column symbols: epd = External pull-down approximately 5kΩ to VSS; epu = External pull-up approximately 5kΩ
Table 6.Pin Definitions—External Port Arbitration
I = input; A = asynchronous; O = output; OD = open drain output; T = Three-State; P = power supply; G = ground;
pd = internal pulldown 5kΩ; pu = internal pullup 5kΩ; pd_0 = internal pulldown 5kΩ on DSP ID=0; pu_0 = internal pullup 5kΩ on DSP
ID=0; pu_od_0 = internal pullup 500Ω on DSP ID=0; pd_m = internal pulldown 5kΩ on DSP bus master; pu_m = internal pullup 5kΩ on DSP
bus master; pu_ad = internal pullup 40kΩ; For more pulldown and pullup information, see Electrical Characteristics on page22.
Term (for termination) column symbols: epd = External pull-down approximately 5kΩ to VSS; epu = External pull-up approximately 5kΩ
to VDD_IO, nc = Not connected; au = Always used.This external pull-up resistor may be omitted for the ID=000 TigerSHARC processor.
Table 7.Pin Definitions—External Port DMA/Flyby
I = input; A = asynchronous; O = output; OD = open drain output; T = Three-State; P = power supply; G = ground;
pd = internal pulldown 5kΩ; pu = internal pullup 5kΩ; pd_0 = internal pulldown 5kΩ on DSP ID=0; pu_0 = internal pullup 5kΩ on DSP
ID=0; pu_od_0 = internal pullup 500Ω on DSP ID=0; pd_m = internal pulldown 5kΩ on DSP bus master; pu_m = internal pullup 5kΩ on DSP
bus master; pu_ad = internal pullup 40kΩ; For more pulldown and pullup information, see Electrical Characteristics on page22.
Term (for termination) column symbols: epd = External pull-down approximately 5kΩ to VSS; epu = External pull-up approximately 5kΩ
to VDD_IO, nc = Not connected; au = Always used.
Table 8.Pin Definitions—External Port SDRAM Controller
I = input; A = asynchronous; O = output; OD = open drain output; T = Three-State; P = power supply; G = ground;
pd = internal pulldown 5kΩ; pu = internal pullup 5kΩ; pd_0 = internal pulldown 5kΩ on DSP ID=0; pu_0 = internal pullup 5kΩ on DSP
ID=0; pu_od_0 = internal pullup 500Ω on DSP ID=0; pd_m = internal pulldown 5kΩ on DSP bus master; pu_m = internal pullup 5kΩ on DSP
bus master; pu_ad = internal pullup 40kΩ; For more pulldown and pullup information, see Electrical Characteristics on page22.
Term (for termination) column symbols: epd = External pull-down approximately 5kΩ to VSS; epu = External pull-up approximately 5kΩ
to VDD_IO, nc = Not connected; au = Always used.
Table 9.Pin Definitions—JTAG Port
I = input; A = asynchronous; O = output; OD = open drain output; T = Three-State; P = power supply; G = ground;
pd = internal pulldown 5kΩ; pu = internal pullup 5kΩ; pd_0 = internal pulldown 5kΩ on DSP ID=0; pu_0 = internal pullup 5kΩ on DSP
ID=0; pu_od_0 = internal pullup 500Ω on DSP ID=0; pd_m = internal pulldown 5kΩ on DSP bus master; pu_m = internal pullup 5kΩ on DSP
bus master; pu_ad = internal pullup 40kΩ; For more pulldown and pullup information, see Electrical Characteristics on page22
Term (for termination) column symbols: epd = External pull-down approximately 5kΩ to VSS; epu = External pull-up approximately 5kΩ
to VDD_IO, nc = Not connected; au = Always used.See the reference onpage11 to the JTAG emulation technical reference EE-68.
Table 8.Pin Definitions—External Port SDRAM Controller (Continued)
I = input; A = asynchronous; O = output; OD = open drain output; T = Three-State; P = power supply; G = ground;
pd = internal pulldown 5kΩ; pu = internal pullup 5kΩ; pd_0 = internal pulldown 5kΩ on DSP ID=0; pu_0 = internal pullup 5kΩ on DSP
ID=0; pu_od_0 = internal pullup 500Ω on DSP ID=0; pd_m = internal pulldown 5kΩ on DSP bus master; pu_m = internal pullup 5kΩ on DSP
bus master; pu_ad = internal pullup 40kΩ; For more pulldown and pullup information, see Electrical Characteristics on page22.
Term (for termination) column symbols: epd = External pull-down approximately 5kΩ to VSS; epu = External pull-up approximately 5kΩ
to VDD_IO, nc = Not connected; au = Always used.
Table 10.Pin Definitions—Flags, Interrupts, and Timer
I = input; A = asynchronous; O = output; OD = open drain output; T = Three-State; P = power supply; G = ground;
pd = internal pulldown 5kΩ; pu = internal pullup 5kΩ; pd_0 = internal pulldown 5kΩ on DSP ID=0; pu_0 = internal pullup 5kΩ on DSP
ID=0; pu_od_0 = internal pullup 500Ω on DSP ID=0; pd_m = internal pulldown 5kΩ on DSP bus master; pu_m = internal pullup 5kΩ on DSP
bus master; pu_ad = internal pullup 40kΩ; For more pulldown and pullup information, see Electrical Characteristics on page22.
Term (for termination) column symbols: epd = External pull-down approximately 5kΩ to VSS; epu = External pull-up approximately 5kΩ
to VDD_IO, nc = Not connected; au = Always used.
Table 11.Pin Definitions—Link Ports
I = input; A = asynchronous; O = output; OD = open drain output; T = Three-State; P = power supply; G = ground;
pd = internal pulldown 5kΩ; pu = internal pullup 5kΩ; pd_0 = internal pulldown 5kΩ on DSP ID=0; pu_0 = internal pullup 5kΩ on DSP
ID=0; pu_od_0 = internal pullup 500Ω on DSP ID=0; pd_m = internal pulldown 5kΩ on DSP bus master; pu_m = internal pullup 5kΩ on DSP
bus master; pu_ad = internal pullup 40kΩ; For more pulldown and pullup information, see Electrical Characteristics on page22.
Term (for termination) column symbols: epd = External pull-down approximately 5kΩ to VSS; epu = External pull-up approximately 5kΩ
to VDD_IO, nc = Not connected; au = Always used.The L1BCMPO and L2BCMPO pins have different termination requirements on revision 0.x silicon, see the EE-179: ADSP-TS20xS TigerSHARC System Design Guidelines
on the Analog Devices website ().
Table 12.Pin definitions—Impedance Control , Drive Strength Control, and Regulator Enable
I = input; A = asynchronous; O = output; OD = open drain output; T = Three-State; P = power supply; G = ground;
pd = internal pulldown 5kΩ; pu = internal pullup 5kΩ; pd_0 = internal pulldown 5kΩ on DSP ID=0; pu_0 = internal pullup 5kΩ on DSP
ID=0; pu_od_0 = internal pullup 500Ω on DSP ID=0; pd_m = internal pulldown 5kΩ on DSP bus master; pu_m = internal pullup 5kΩ on DSP
bus master; pu_ad = internal pullup 40kΩ; For more pulldown and pullup information, see Electrical Characteristics on page22.
Term (for termination) column symbols: epd = External pull-down approximately 5kΩ to VSS; epu = External pull-up approximately 5kΩ
to VDD_IO, nc = Not connected; au = Always used.
Table 13.Drive Strength/Output Impedance SelectionCONTROLIMP1=0, A/D mode disabled.CONTROLIMP1=1, A/D mode enabled.
STRAP PIN FUNCTION DESCRIPTIONSSome pins have alternate functions at reset. Strap options set
DSP operating modes. During reset, the DSP samples the strap
option pins. Strap pins have an internal pullup or pulldown for
the default value. If a strap pin is not connected to an overdriv-
ing external pullup, pulldown, or logic load, the DSP samples
the default value during reset. If strap pins are connected to
logic inputs, a stronger external pullup or pulldown may be
required to ensure default value depending on leakage and/or
low level input current of the logic load. To set a mode other
than the default mode, connect the strap pin to a sufficiently
stronger external pullup or pulldown. Table15 lists and
describes each of the DSP’s strap pins.
Table 14.Pin Definitions—Power, Ground, and Reference
I = input; A = asynchronous; O = output; OD = open drain output; T = Three-State; P = power supply; G = ground;
pd = internal pulldown 5kΩ; pu = internal pullup 5kΩ; pd_0 = internal pulldown 5kΩ on DSP ID=0; pu_0 = internal pullup 5kΩ on DSP
ID=0; pu_od_0 = internal pullup 500Ω on DSP ID=0; pd_m = internal pulldown 5kΩ on DSP bus master; pu_m = internal pullup 5kΩ on DSP
bus master; pu_ad = internal pullup 40kΩ; For more pulldown and pullup information, see Electrical Characteristics on page22.
Term (for termination) column symbols: epd = External pull-down approximately 5kΩ to VSS; epu = External pull-up approximately 5kΩ
to VDD_IO, nc = Not connected; au = Always used.For more information on SCLK and SCLK_VREF on revision 0.0 silicon, see the EE-179: ADSP-TS20xS TigerSHARC System Design Guidelines on the Analog Devices website
().
Table 15.Pin Definitions—I/O Strap Pins
I = input; A = asynchronous; O = output; OD = open drain output; T = Three-State; P = power supply; G = ground;
pd = internal pulldown 5kΩ; pu = internal pullup 5kΩ; pd_0 = internal pulldown 5kΩ on DSP ID=0; pu_0 = internal pullup 5kΩ on DSP
ID=0; pu_od_0 = internal pullup 500Ω on DSP ID=0; pd_m = internal pulldown 5kΩ on DSP bus master; pu_m = internal pullup 5kΩ on DSP
When default configuration is used, no external resistor is
needed on the strap pins. To apply other configurations, a 500Ω
resistor connected to VDD_IO is required. If providing external
pulldowns, do not strap these pins directly to VSS; the strap pins
require 500Ω resistor straps.
All strap pins are sampled on the rising edge of RST_IN (de-
assertion edge). Each pin latches the strapped pin state (state of
the strap pin at the rising edge of RST_IN). Shortly after de-
assertion of RST_IN, these pins are re-configured to their nor-
mal functionality.
These strap pins have an internal pull-down resistor, pull-up
resistor, or no-resistor (three-state) on each pin. The resistor
type, which is connected to the I/O pad, depends on whether
RST_IN is active (low) or if RST_IN is de-asserted (high).
Table16 shows the resistors that are enabled during active reset
and during normal operation.
Table 15.Pin Definitions—I/O Strap Pins (Continued)
I = input; A = asynchronous; O = output; OD = open drain output; T = Three-State; P = power supply; G = ground;
pd = internal pulldown 5kΩ; pu = internal pullup 5kΩ; pd_0 = internal pulldown 5kΩ on DSP ID=0; pu_0 = internal pullup 5kΩ on DSP
ID=0; pu_od_0 = internal pullup 500Ω on DSP ID=0; pd_m = internal pulldown 5kΩ on DSP bus master; pu_m = internal pullup 5kΩ on DSP
bus master; pu_ad = internal pullup 40kΩ; For more pulldown and pullup information, see Electrical Characteristics on page22.
Table 16.Strap Pin Internal Resistors—Active Reset
(RST_IN = 0) Versus Normal Operation (RST_IN = 1)
pd = internal pulldown 5kΩ; pu = internal pullup 5kΩ; pd_0 =
internal pulldown 5kΩ on DSP ID=0; pu_0 = internal pullup 5kΩ
on DSP ID=0
