ADSP-TS101SAB1-000 ,300 MHz TigerSHARC Processor with 6 Mbit on-chip SRAMCharacteristics . 36Flexible Instruction Set .... 5 PBGA Pin Configurations .... 36On-Chip SRAM Mem ..
ADSP-TS101SAB1Z100 , TigerSHARC Embedded Processor
ADSP-TS101SAB1Z100 , TigerSHARC Embedded Processor
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ADSP-TS201SABP-050 ,500/600 MHz TigerSHARC Processor with 24 Mbit on-chip embedded DRAMGENERAL DESCRIPTIONThe ADSP-TS201S TigerSHARC processor is an ultra-high per- • Four 128-bit intern ..
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ADSP-TS101S-ADSP-TS101SAB1-000
300 MHz TigerSHARC Processor with 6 Mbit on-chip SRAM
TigerSHARC and the TigerSHARC logo are registered trademarks of Analog Devices, Inc.
Rev. B
KEY FEATURES
300MHz, 3.3ns instruction cycle ratebits of internal—on-chip—SRAM memory
19 mm×19mm (484-ball) or 27 mm×27mm
(625-ball) PBGA package
Dual computation blocks—each containing an ALU, a multi-
plier, a shifter, and a register file
Dual integer ALUs, providing data addressing and pointer
manipulation
Integrated I/O includes 14-channel DMA controller, external
port, four link ports, SDRAM controller, programmable
flag pins, two timers, and timer expired pin for system
integration
1149.1 IEEE compliant JTAG test access port for on-chip
emulation
On-chip arbitration for glueless multiprocessing with up to
eight TigerSHARC processors on a bus
KEY BENEFITS
Provides high performance Static Superscalar DSP opera-
tions, optimized for telecommunications infrastructure
and other large, demanding multiprocessor DSP
applications
Performs exceptionally well on DSP algorithm and I/O bench-
marks (see benchmarks in Table1 and Table2)
Supports low overhead DMA transfers between internal
memory, external memory, memory-mapped peripherals,
link ports, other DSPs (multiprocessor), and host
processors
Eases DSP programming through extremely flexible instruc-
tion set and high level language friendly DSP architecture
Enables scalable multiprocessing systems with low commu-
nications overheadFigure 1.Functional Block Diagram
TABLE OF CONTENTSGeneral Description ................................................. 3
Dual Compute Blocks ............................................ 4
Data Alignment Buffer (DAB) .................................. 4
Dual Integer ALUs (IALUs) .................................... 4
Program Sequencer ............................................... 5
Interrupt Controller ........................................... 5
Flexible Instruction Set ........................................ 5
On-Chip SRAM Memory ........................................ 5
External Port
(Off-Chip Memory/Peripherals Interface) ................ 6
Host Interface ................................................... 6
Multiprocessor Interface ...................................... 7
SDRAM Controller ............................................ 7
EPROM Interface .............................................. 7
DMA Controller ................................................... 7
Link Ports ........................................................... 8
Timer and General-Purpose I/O ............................... 9
Reset and Booting ................................................. 9
Low Power Operation ............................................ 9
Clock Domains .................................................... 9
Output Pin Drive Strength Control ......................... 10
Power Supplies ................................................... 10
Filtering Reference Voltage and Clocks .................... 10
Development Tools ............................................. 10
Designing an Emulator-
Compatible DSP Board(Target) .......................... 11
Additional Information ........................................ 11
Pin Function Descriptions ....................................... 12
Pin States at Reset ............................................... 12
Pin Definitions ................................................... 12
Strap Pin Function Descriptions ................................ 19
Specifications ........................................................ 20
Recommended Operating Conditions ...................... 20
Electrical Characteristics ....................................... 20
Absolute Maximum Ratings .................................. 21
ESD Sensitivity ................................................... 21
Timing Specifications .......................................... 21
General AC Timing .......................................... 21
Link Ports Data Transfer
and Token Switch Timing ............................... 29
Output Drive Currents ......................................... 32
Test Conditions .................................................. 34
Output Disable Time ......................................... 34
Output Enable Time ......................................... 34
Capacitive Loading ........................................... 34
Environmental Conditions .................................... 36
Thermal Characteristics ..................................... 36
PBGA Pin Configurations ........................................ 36
Outline Dimensions ................................................ 43
Ordering Guide ..................................................... 44
REVISION HISTORY
12/04—Rev. A to Rev. BProvides more information on clock signals (including a usable
jitter specification) in:
Reference Clocks—Core Clock (CCLK) Cycle Time ..... 22
Reference Clocks—Local Clock (LCLK) Cycle Time .... 22
Reference Clocks—System Clock (SCLK) Cycle Time .. 23
Reference Clocks—Test Clock (TCK) Cycle Time ....... 23
Updates input setup times for external port pins in:
AC Signal Specifications (for SCLK <16.7 ns) ............. 25
GENERAL DESCRIPTIONThe ADSP-TS101S TigerSHARC processor is an ultrahigh per-
formance, static superscalar processor optimized for large signal
processing tasks and communications infrastructure. The DSP
combines very wide memory widths with dual computation
blocks—supporting 32- and 40-bit floating-point and 8-, 16-,
32-, and 64-bit fixed-point processing—to set a new standard of
performance for digital signal processors. The TigerSHARC
processor’s static superscalar architecture lets the processor exe-
cute up to four instructions each cycle, performing 24 fixed-
point (16-bit) operations or six floating-point operations.
Three independent 128-bit wide internal data buses, each
connecting to one of the three 2Mbit memory banks, enable
quad word data, instruction, and I/O accesses and provide
14.4Gbytes per second of internal memory bandwidth. Operat-
ing at 300MHz, the ADSP-TS101S processor’s core has a 3.3ns
instruction cycle time. Using its Single-Instruction, Multiple-
Data (SIMD) features, the ADSP-TS101S can perform 2.4 bil-
lion 40-bit MACs or 600 million 80-bit MACs per second.
Table1 and Table2 show the DSP’s performance benchmarks.
The ADSP-TS101S is code compatible with the other
TigerSHARC processors.
The Functional Block Diagram onPage1 shows the ADSP-
TS101S processor’s architectural blocks. These blocks include:Dual compute blocks, each consisting of an ALU, multi-
plier, 64-bit shifter, and 32-word register file and associated
data alignment buffers (DABs)
•Dual integer ALUs (IALUs), each with its own 31-word
register file for data addressingA program sequencer with instruction alignment buffer
(IAB), branch target buffer (BTB), and interrupt controllerThree 128-bit internal data buses, each connecting to one
of three 2Mbit memory banks
•On-chip SRAM (6Mbit)An external port that provides the interface to host proces-
sors, multiprocessing space (DSPs), off-chip memory
mapped peripherals, and external SRAM and SDRAMA 14-channel DMA controllerFour link portsTwo 64-bit interval timers and timer expired pinA 1149.1 IEEE compliant JTAG test access port for on-chip
emulation
Figure2 shows a typical single processor system with external
SDRAM. Figure4 on Page8 shows a typical multiprocessor
system.
The TigerSHARC processor uses a Static SuperscalarTM† architec-
ture. This architecture is superscalar in that the ADSP-TS101S
processor’s core can execute simultaneously from one to four
32-bit instructions encoded in a very large instruction word
(VLIW) instruction line using the DSP’s dual compute blocks.
Because the DSP does not perform instruction reordering at
run-time—the programmer selects which operations will exe-
cute in parallel prior to run-time—the order of instructions is
static.
With few exceptions, an instruction line, whether it contains
one, two, three, or four 32-bit instructions, executes with a
throughput of one cycle in an eight-deep processor pipeline.
For optimal DSP program execution, programmers must follow
the DSP’s set of instruction parallelism rules when encoding an
instruction line. In general, the selection of instructions that the
DSP can execute in parallel each cycle depends on the instruc-
tion line resources each instruction requires and on the source
and destination registers used in the instructions. The program-
mer has direct control of three core components—the IALUs,
the compute blocks, and the program sequencer.
The ADSP-TS101S, in most cases, has a two-cycle arithmetic
execution pipeline that is fully interlocked, so whenever a com-
putation result is unavailable for another operation dependent
Table 1.General-Purpose Algorithm Benchmarks
at 300 MHz
Table 2.3G Wireless Algorithm BenchmarksThe execution speed is in instruction cycles per second.This value is for six iterations of the algorithm. For eight iterations of the turbo
decoder, this benchmark is 67 MIPS.Adaptive multi rate (AMR)
on it, the DSP automatically inserts one or more stall cycles as
needed. Efficient programming with dependency-free instruc-
tions can eliminate most computational and memory transfer
data dependencies.
In addition, the ADSP-TS101S supports SIMD operations two
ways—SIMD compute blocks and SIMD computations.The
programmer can direct both compute blocks to operate on the
same data (broadcast distribution) or on different data (merged
distribution). In addition, each compute block can execute four
16-bit or eight 8-bit SIMD computations in parallel.
DUAL COMPUTE BLOCKSThe ADSP-TS101S has compute blocks that can execute com-
putations either independently or together as a SIMD engine.
The DSP can issue up to two compute instructions per compute
block each cycle, instructing the ALU, multiplier, or shifter to
perform independent, simultaneous operations.
The compute blocks are referred to as X and Y in assembly syn-
tax, and each block contains three computational units—an
ALU, a multiplier, a 64-bit shifter—and a 32-word register file.Register file—each compute block has a multiported
32-word, fully orthogonal register file used for transferring
data between the computation units and data buses and for
storing intermediate results. Instructions can access the
registers in the register file individually (word aligned), or
in sets of two (dual aligned) or four (quad aligned).ALU—the ALU performs a standard set of arithmetic oper-
ations in both fixed- and floating-point formats. It also
performs logic operations.Multiplier—the multiplier performs both fixed- and float-
ing-point multiplication and fixed-point multiply and
accumulate.Shifter—the 64-bit shifter performs logical and arithmetic
shifts, bit and bit stream manipulation, and field deposit
and extraction operations.Accelerator—128-bit unit for trellis decoding (for example,
Viterbi and turbo decoders) and complex correlations for
communication applications.
Using these features, the compute blocks can:Provide 8 MACs per cycle peak and 7.1 MACs per cycle
sustained 16-bit performance and provide 2 MACs per
cycle peak and 1.8 MACs per cycle sustained 32-bit perfor-
mance (based on FIR) Execute six single precision floating-point or execute 24
fixed-point (16-bit) operations per cycle, providing
1,800MFLOPS or 7.3GOPS performancePerform two complex 16-bit MACs per cycleExecute eight trellis butterflies in one cycle
DATA ALIGNMENT BUFFER (DAB)The DAB is a quad word FIFO that enables loading of quad
word data from nonaligned addresses. Normally, load instruc-
tions must be aligned to their data size so that quad words are
loaded from a quad aligned address. Using the DAB signifi-
cantly improves the efficiency of some applications, such as FIR
filters.
DUAL INTEGER ALUS (IALUS)The ADSP-TS101S has two IALUs that provide powerful
address generation capabilities and perform many general-pur-
pose integer operations. Each of the IALUs:Provides memory addresses for data and update pointersSupports circular buffering and bit-reverse addressingPerforms general-purpose integer operations, increasing
programming flexibilityIncludes a 31-word register file for each IALU
As address generators, the IALUs perform immediate or indi-
rect (pre- and post-modify) addressing. They perform modulus
and bit-reverse operations with no constraints placed on mem-
ory addresses for the modulus data buffer placement. Each
IALU can specify either a single, dual, or quad word access from
memory.
The IALUs have hardware support for circular buffers, bit
reverse, and zero-overhead looping. Circular buffers facilitate
Figure 2.Single Processor System with External SDRAM
used in digital filters and Fourier transforms. Each IALU pro-
vides registers for four circular buffers, so applications can set
up a total of eight circular buffers. The IALUs handle address
pointer wraparound automatically, reducing overhead, increas-
ing performance, and simplifying implementation. Circular
buffers can start and end at any memory location.
Because the IALU’s computational pipeline is one cycle deep, in
most cases, integer results are available in the next cycle. Hard-
ware (register dependency check) causes a stall if a result is
unavailable in a given cycle.
PROGRAM SEQUENCERThe ADSP-TS101S processor’s program sequencer supports:A fully interruptible programming model with flexible pro-
gramming in assembly and C/C++ languages; handles
hardware interrupts with high throughput and no aborted
instruction cycles.An eight-cycle instruction pipeline—three-cycle fetch pipe
and five-cycle execution pipe—with computation results
available two cycles after operands are available.The supply of instruction fetch memory addresses; the
sequencer’s instruction alignment buffer (IAB) caches up
to five fetched instruction lines waiting to execute; the pro-
gram sequencer extracts an instruction line from the IAB
and distributes it to the appropriate core component for
execution.The management of program structures and determination
of program flow according to JUMP, CALL, RTI, RTS
instructions, loop structures, conditions, interrupts, and
software exceptions.Branch prediction and a 128-entry branch target buffer
(BTB) to reduce branch delays for efficient execution of
conditional and unconditional branch instructions and
zero-overhead looping; correctly predicted branches that
are taken occur with zero-to-two overhead cycles, over-
coming the three-to-six stage branch penalty.Compact code without the requirement to align code in
memory; the IAB handles alignment.
Interrupt ControllerThe DSP supports nested and non-nested interrupts. Each
interrupt type has a register in the interrupt vector table. Also,
each has a bit in both the interrupt latch register and the inter-
rupt mask register. All interrupts are fixed as either level
sensitive or edge sensitive, except the IRQ3–0 hardware inter-
rupts, which are programmable.
The DSP distinguishes between hardware interrupts and soft-
ware exceptions, handling them differently. When a software
exception occurs, the DSP aborts all other instructions in the
instruction pipe. When a hardware interrupt occurs, the DSP
continues to execute instructions already in the instruction pipe.
Flexible Instruction SetThe 128-bit instruction line, which can contain up to four 32-bit
instructions, accommodates a variety of parallel operations for
concise programming. For example, one instruction line can
direct the DSP to conditionally execute a multiply, an add, and a
subtract in both computation blocks while it also branches to
another location in the program. Some key features of the
instruction set include:Enhanced instructions for communications infrastructure
to govern trellis decoding (for example, Viterbi and turbo
decoders) and despreading via complex correlationsAlgebraic assembly language syntaxDirect support for all DSP, imaging, and video arithmetic
types, eliminating hardware modesBranch prediction encoded in instruction, enables zero-
overhead loopsParallelism encoded in instruction lineConditional execution optional for all instructionsUser-defined, programmable partitioning between pro-
gram and data memory
ON-CHIP SRAM MEMORYThe ADSP-TS101S has 6Mbits of on-chip SRAM memory,
divided into three blocks of 2Mbits (64Kwords×32bits). Each
block—M0, M1, and M2—can store program, data, or both, so
applications can configure memory to suit specific needs. Plac-
ing program instructions and data in different memory blocks,
however, enables the DSP to access data while performing an
instruction fetch.
The DSP’s internal and external memory (Figure3) is organized
into a unified memory map, which defines the location
(address) of all elements in the system.
The memory map is divided into four memory areas—host
space, external memory, multiprocessor space, and internal
memory—and each memory space, except host memory, is sub-
divided into smaller memory spaces.
Each internal memory block connects to one of the 128-bit wide
internal buses—block M0 to bus MD0, block M1 to bus MD1,
and block M2 to bus MD2—enabling the DSP to perform three
memory transfers in the same cycle. The DSP’s internal bus
architecture provides a total memory bandwidth of 14.4Gbytes
per second, enabling the core and I/O to access eight 32-bit data
words (256 bits) and four 32-bit instructions each cycle. The
DSP’s flexible memory structure enables:DSP core and I/O access of different memory blocks in the
same cycleDSP core access of all three memory blocks in parallel—
one instruction and two data accessesProgrammable partitioning of program and data memoryProgram access of all memory as 32-, 64-, or 128-bit
words—16-bit words with the DAB
EXTERNAL PORT
(OFF-CHIP MEMORY/PERIPHERALS INTERFACE)The ADSP-TS101S processor’s external port provides the pro-
cessor’s interface to off-chip memory and peripherals. The word address space is included in the DSP’s unified address
space. Theseparate on-chip buses—three 128-bit data buses and
three 32-bit address buses—are multiplexed at the external port
to create an external system bus with a single 64-bit data bus
and a single 32-bit address bus. The external port supports data
transfer rates of 800Mbytes per second over external bus.
The external bus can be configured for 32- or 64-bit operation.
When the system bus is configured for 64-bit operation, the
lower 32 bits of the external data bus connect to even addresses,
and the upper 32 bits connect to odd addresses.
The external port supports pipelined, slow, and SDRAM proto-
cols. Addressing of external memory devices and memory
mapped peripherals is facilitated by on-chip decoding of high
order address lines to generate memory bank select signals.
The ADSP-TS101S provides programmable memory, pipeline
depth, and idle cycle for synchronous accesses, and external
acknowledge controls to support interfacing to pipelined or
slow devices, host processors, and other memory-mapped
peripherals with variable access, hold, and disable time
requirements.
Host InterfaceThe ADSP-TS101S provides an easy and configurable interface
Figure 3.Memory Map
interface supports pipelined or slow protocols for accesses of the
host as slave. Each protocol has programmable transmission
parameters, such as idle cycles, pipe depth, and internal
waitcycles.
The host interface supports burst transactions initiated by a host
processor. After the host issues the starting address of the burst
and asserts the BRST signal, the DSP increments the address
internally while the host continues to assert BRST.
The host interface provides a deadlock recovery mechanism that
enables a host to recover from deadlock situations involving the
DSP. The BOFF signal provides the deadlock recovery mecha-
nism. When the host asserts BOFF, the DSP backs off the
current transaction and asserts HBG and relinquishes the exter-
nal bus.
The host can directly read or write the internal memory of the
ADSP-TS101S, and it can access most of the DSP registers,
including DMA control (TCB) registers. Vector interrupts sup-
port efficient execution of host commands.
Multiprocessor InterfaceThe ADSP-TS101S offers powerful features tailored to multi-
processing DSP systems through the external port and link
ports. This multiprocessing capability provides highest band-
width for interprocessor communication, including:Up to eight DSPs on a common busOn-chip arbitration for glueless multiprocessingLink ports for point-to-point communication
The external port and link ports provide integrated, glueless
multiprocessing support.
The external port supports a unified address space (see Figure3)
that enables direct interprocessor accesses of each ADSP-
TS101S processor’s internal memory and registers. The DSP’s
on-chip distributed bus arbitration logic provides simple, glue-
less connection for systems containing up to eight ADSP-
TS101S processors and a host processor. Bus arbitration has a
rotating priority. Bus lock supports indivisible read-modify-
write sequences for semaphores. A bus fairness feature prevents
one DSP from holding the external bus too long.
The DSP’s four link ports provide a second path for interproces-
sor communications with throughput of 1Gbytes per second.
The cluster bus provides 800Mbytes per second throughput—
with a total of 1.8Gbytes per second interprocessor bandwidth.
SDRAM ControllerThe SDRAM controller controls the ADSP-TS101S processor’s
transfers of data to and from synchronous DRAM (SDRAM).
The throughput is 32 or 64 bits per SCLK cycle using the exter-
nal port and SDRAM control pins.
The SDRAM interface provides a glueless interface with stan-
dard SDRAMs—16Mbit, 64Mbit, 128Mbit, and 256Mbit. The
DSP directly supports a maximum of 64Mwords×32bits of
SDRAM. The SDRAM interface is mapped in external memory
in the DSP’s unified memory map.
EPROM InterfaceThe ADSP-TS101S can be configured to boot from external
8-bit EPROM at reset through the external port. An automatic
process (which follows reset) loads a program from the EPROM
into internal memory. This process uses 16 wait cycles for each
read access. During booting, the BMS pin functions as the
EPROM chip select signal. The EPROM boot procedure uses
DMA Channel 0, which packs the bytes into 32-bit instructions.
Applications can also access the EPROM (write flash memories)
during normal operation through DMA.
The EPROM or flash memory interface is not mapped in the
DSP’s unified memory map. It is a byte address space limited to
a maximum of 16Mbytes (24 address bits). The EPROM or
flash memory interface can be used after boot viaaDMA.
DMA CONTROLLERThe ADSP-TS101S processor’s on-chip DMA controller, with
14 DMA channels, provides zero-overhead data transfers with-
out processor intervention. The DMA controller operates
independently and invisibly to the DSP’s core, enabling DMA
operations to occur while the DSP’s core continues to execute
program instructions. The DMA controller performs DMA
transfers between:Internal memory and external memory and memory-
mapped peripheralsInternal memory of other DSPs on a common bus, a host
processor, or link port I/OExternal memory and external peripherals or link port I/OExternal bus master and internal memory or link port I/O
The DMA controller provides a number of additional features.
The DMA controller supports flyby transfers. Flyby operations
only occur through the external port (DMA Channel 0) and do
not involve the DSP’s core. The DMA controller acts as a con-
duit to transfer data from one external device to another
through external memory. During a transaction, the DSP:Relinquishes the external data busOutputs addresses, memory selects (MS1–0, MSSD, RAS,
CAS, and SDWE) and the FLYBY, IOEN, and RD/WR
strobes
•Responds to ACK
DMA chaining is also supported by the DMA controller. DMA
chaining operations enable applications to automatically link
one DMA transfer sequence to another for continuous trans-
mission. The sequences can occur over different DMA channels
and have different transmission attributes.
The DMA controller also supports two-dimensional transfers.
The DMA controller can access and transfer two-dimensional
memory arrays on any DMA transmit or receive channel. These
transfers are implemented with index, count, and modify regis-
ters for both the X and Y dimensions.
The DMA controller performs the following DMA operations:External port block transfers. Four dedicated bidirectional
DMA channels transfer blocks of data between the DSP’s
internal memory and any external memory or memory-
mapped peripheral on the external bus. These transfers
support master mode and handshake mode protocols.Link port transfers. Eight dedicated DMA channels (four
transmit and four receive) transfer quad word data only
between link ports and between a link port and internal or
external memory. These transfers only use handshake
mode protocol. DMA priority rotates between the four
receive channels. AutoDMA transfers. Two dedicated unidirectional DMA
channels transfer data received from an external bus master
to internal memory or to link port I/O. These transfers only
use slave mode protocol, and an external bus master must
initiate the transfer.
LINK PORTSThe DSP’s four link ports provide additional 8-bit bidirectional
I/O capability. With the ability to operate at a double data rate—
latching data on both the rising and falling edges of the clock—
Figure 4.Shared Memory Multiprocessing System
running at 125MHz, each link port can support up to
250Mbytes per second, for a combined maximum throughput
of 1Gbytes per second.
The link ports provide an optional communications channel
that is useful in multiprocessor systems for implementing point
to point interprocessor communications. Applications can also
use the link ports for booting.
Each link port has its own double-buffered input and output
registers. The DSP’s core can write directly to a link port’s trans-
mit register and read from a receive register, or the DMA
controller can perform DMA transfers through eight (four
transmit and four receive) dedicated link port DMA channels.
Each link port has three signals that control its operation.
LxCLKOUT and LxCLKIN implement clock/acknowledge
handshaking. LxDIR indicates the direction of transfer and is
used only when buffering the LxDAT signals. An example appli-
cation would be using differential low-swing buffers for long
twisted-pair wires. LxDAT provides the 8-bit data bus
input/output.
Applications can program separate error detection mechanisms
for transmit and receive operations (applications can use the
checksum mechanism to implement consecutive link port
transfers), the size of data packets, and the speed at which bytes
are transmitted.
Under certain conditions, the link port receiver can initiate a
token switch to reverse the direction of transfer; the transmitter
becomes the receiver and vice versa.
TIMER AND GENERAL-PURPOSE I/OThe ADSP-TS101S has a timer pin (TMR0E) that generates out-
put when a programmed timer counter has expired. Also, the
DSP has four programmable general-purpose I/O pins
(FLAG3–0) that can function as either single bit input or out-
put. As outputs, these pins can signal peripheral devices; as
inputs, they can provide the test for conditional branching.
RESET AND BOOTINGThe ADSP-TS101S has two levels of reset (see reset specifica-
tions onPage24):Power-up reset—after power-up of the system, and strap
options are stable, the RESET pin must be asserted (low). Normal reset—for any resets following the power-up reset
sequence, the RESET pin must be asserted.
The DSP can be reset internally (core reset) by setting the
SWRST bit in SQCTL. The core is reset, but not the external
port or I/O.
After reset, the ADSP-TS101S has four boot options for begin-
ning operation:Boot from EPROM. The DSP defaults to EPROM booting
when the BMS pin strap option is set low. See Strap Pin
Function Descriptions on Page19.Boot by an external master (host or another ADSP-
TS101S). Any master on the cluster bus can boot the
ADSP-TS101S through writes to its internal memory or
through autoDMA.Boot by link port. All four receive link DMA channels are
initialized after reset to transfer a 256-word block to inter-
nal memory address 0 to 255, and to issue an interrupt at
the end of the block (similar to EP DMA). The correspond-
ing DMA interrupts are set to address zero (0).No boot—Start running from an external memory. Using
the “no boot” option, the ADSP-TS101S must start running
from an external memory, caused by asserting one of the
IRQ3–0 interrupt signals.
The ADSP-TS101S core always exits from reset in the idle state
and waits for an interrupt. Some of the interrupts in the inter-
rupt vector table are initialized and enabled after reset.
LOW POWER OPERATIONThe ADSP-TS101S can enter a low power sleep mode in which
its core does not execute instructions, reducing power con-
sumption to a minimum. The ADSP-TS101S exits sleep mode
when it senses a falling edge on any of its IRQ3–0 interrupt
inputs. The interrupt, if enabled, causes the ADSP-TS101S to
execute the corresponding interrupt service routine. This fea-
ture is useful for systems that require a low power standby
mode.
CLOCK DOMAINSAs shown in Figure5, the ADSP-TS101S has two clock inputs,
SCLK (system clock) and LCLK (local clock).
These inputs drive its two major clock domains:SCLK (system clock). Provides clock input for the external
bus interface and defines the ac specification reference for
the external bus signals. The external bus interface runs at
1× the SCLK frequency. A DLL locks internal SCLK to
SCLK input. LCLK (local clock). Provides clock input to the internal
clock driver, CCLK, which is the internal clock for the core,
Figure 5.Clock Domains
execution rate is equal to CCLK. A PLL from LCLK gener-
ates CCLK which is phase-locked. The LCLKRAT pins
define the clock multiplication of LCLK to CCLK (see
Table4). The link port clock is generated from CCLK via a
software programmable divisor. RESET must be asserted
until LCLK is stable and within specification for at least ms. This applies to power-up as well as any dynamic
modification of LCLK after power-up. Dynamic modifica-
tion may include LCLK going out of specification as long as
RESET is asserted.
Connecting SCLK and LCLK to the same clock source is a
requirement for the device. Using an integer clock multipli-
cation value provides predictable cycle-by-cycle operation, a
requirement of fault-tolerant systems and some multi-
processing systems.
Noninteger values are completely functional and acceptable for
applications that do not require predictable cycle-by-cycle
operation.
OUTPUT PIN DRIVE STRENGTH CONTROLPins CONTROLIMP2-0 and DS2-0 work together to control
the output drive strength of two groups of pins, the
Address/Data/Control pin group and the Link pin group.
CONTROLIMP2-0 independently configures the two pin
groups to the maximum drive strength or to a digitally con-
trolled drive strength that is selectable by the DS2-0 pins (see
Table13 on Page18). If the digitally controlled drive strength is
selected for a pin group, the DS2-0 pins determine one of eight
strength levels for that group (see Table14 on Page18). The
drive strength selected varies the slew rate of the driver. Drive
strength 0 (DS2-0 = 000) is the weakest and slowest slew rate.
Drive strength 7 (DS2-0 = 111) is the strongest and fastest slew
rate.
The stronger drive strengths are useful for high frequency
switching while the lower strengths may allow use of a relaxed
design methodology. The strongest drive strengths have a larger
di/dt and thus require more attention to signal integrity issues
such a ringing, reflections and coupling. Also a larger di/dt can
increase external supply rail noise, which impacts power supply
and power distribution design.
The drive strengths for the EMU, CPA, and DPA pins are not
controllable and are fixed to the maximum level.
For drive strength calculation, see Output Drive Currents on
Page32.
POWER SUPPLIESThe ADSP-TS101S has separate power supply connections for
internal logic (VDD), analog circuits (VDD_A), and I/O buffer
(VDD_IO) power supply. The internal (VDD) and analog (VDD_A)
supplies must meet the 1.2V requirement. The I/O buffer
(VDD_IO) supply must meet the 3.3V requirement.
The analog supply (VDD_A) powers the clock generator PLLs. To
produce a stable clock, systems must provide a clean power sup-
ply to power input VDD_A. Designs must pay critical attention to
bypassing the VDD_A supply.
The required power-on sequence for the DSP is to provide VDD
(and VDD_A) before VDD_IO.
FILTERING REFERENCE VOLTAGE AND CLOCKSFigure6 shows a possible circuit for filtering VREF, SCLK_N, and
LCLK_N. This circuit provides the reference voltage for the
switching voltage, system clock, and local clock references.
DEVELOPMENT TOOLSThe ADSP-TS101S is supported with a complete set of
CROSSCORE®† software and hardware development tools,
including Analog Devices emulators and VisualDSP++®‡ devel-
opment environment. The same emulator hardware that
supports other TigerSHARC processors also fully emulates the
ADSP-TS101S.
The VisualDSP++ project management environment lets pro-
grammers develop and debug an application. This environment
includes an easy to use assembler (which is based on an alge-
braic syntax), an archiver (librarian/library builder), a linker, a
loader, a cycle-accurate instruction-level simulator, a C/C++
compiler, and a C/C++ run-time library that includes DSP and
mathematical functions. A key point for these tools is C/C++
code efficiency. The compiler has been developed for efficient
translation of C/C++ code to DSP assembly. The DSP has archi-
tectural features that improve the efficiency of compiled C/C++
code.
The VisualDSP++ debugger has a number of important fea-
tures. Data visualization is enhanced by a plotting package that
offers a significant level of flexibility. This graphical representa-
tion of user data enables the programmer to quickly determine
the performance of an algorithm. As algorithms grow in com-
plexity, this capability can have increasing significance on the
designer’s development schedule, increasing productivity. Sta-
tistical profiling enables the programmer to nonintrusively poll
the processor as it is running the program. This feature, unique
to VisualDSP++, enables the software developer to passively
gather important code execution metrics without interrupting
the real-time characteristics of the program. Essentially, the
developer can identify bottlenecks in software quickly and
Figure 6.VREF, SCLK_N, and LCLK_N Filter
efficiently. By using the profiler, the programmer can focus on
those areas in the program that impact performance and take
corrective action.
Debugging both C/C++ and assembly programs with the
VisualDSP++ debugger, programmers can:View mixed C/C++ and assembly code (interleaved source
and object information)Insert breakpointsSet conditional breakpoints on registers, memory,
andstacksTrace instruction executionPerform linear or statistical profiling of program executionFill, dump, and graphically plot the contents of memoryPerform source level debuggingCreate custom debugger windows
The VisualDSP++ IDDE lets programmers define and manage
DSP software development. Its dialog boxes and property pages
let programmers configure and manage all of the TigerSHARC
development tools, including the color syntax highlighting in
the VisualDSP++ editor. This capability permits programmers
to:Control how the development tools process inputs and
generate outputsMaintain a one-to-one correspondence with the tool’s
command line switches
The VisualDSP++ Kernel (VDK) incorporates scheduling and
resource management tailored specifically to address the mem-
ory and timing constraints of DSP programming. These
capabilities enable engineers to develop code more effectively,
eliminating the need to start from the very beginning, when
developing new application code. The VDK features include
threads, critical and unscheduled regions, semaphores, events,
and device flags. The VDK also supports priority-based, pre-
emptive, cooperative, and time-sliced scheduling approaches. In
addition, the VDK was designed to be scalable. If the application
does not use a specific feature, the support code for that feature
is excluded from the target system.
Because the VDK is a library, a developer can decide whether to
use it or not. The VDK is integrated into the VisualDSP++
development environment, but can also be used via standard
command line tools. When the VDK is used, the development
environment assists the developer with many error-prone tasks
and assists in managing system resources, automating the gen-
eration of various VDK-based objects, and visualizing the
system state, when debugging an application that uses the VDK.
VCSE is Analog Devices technology for creating, using, and
reusing software components (independent modules of sub-
stantial functionality) to quickly and reliably assemble software
applications. It is also used for downloading components from
the Web, dropping them into the application, and publishing
component archives from within VisualDSP++. VCSE supports
component implementation in C/C++ or assembly language.
Use the expert linker to visually manipulate the placement of
code and data on the embedded system. View memory utiliza-
tion in a color-coded graphical form, easily move code and data
to different areas of the DSP or external memory with a drag of
the mouse, examine run-time stack and heap usage. The expert
linker is fully compatible with existing linker definition file
(LDF), allowing the developer to move between the graphical
and textual environments.
Analog Devices DSP emulators use the IEEE 1149.1 JTAG Test
Access Port of the ADSP-TS101S processor to monitor and con-
trol the target board processor during emulation. The emulator
provides full speed emulation, allowing inspection and modifi-
cation of memory, registers, and processor stacks. Nonintrusive
in-circuit emulation is assured by the use of the processor’s
JTAG interface—the emulator does not affect target system
loading or timing.
In addition to the software and hardware development tools
available from Analog Devices, third parties provide a wide
range of tools supporting the TigerSHARC processor family.
Hardware tools include TigerSHARC processor PC plug-in
cards. Third party software tools include DSP libraries, real-
time operating systems, and block diagram designtools.
DESIGNING AN EMULATOR-
COMPATIBLE DSP BOARD(TARGET)The Analog Devices family of emulators are tools that every
DSP developer needs to test and debug hardware and software
systems. Analog Devices has supplied an IEEE 1149.1 JTAG test
access port (TAP) on each JTAG DSP. The emulator uses the
TAP to access the internal features of the DSP, allowing the
developer to load code, set breakpoints, observe variables,
observe memory, and examine registers. The DSP must be
halted to send data and commands, but once an operation has
been completed by the emulator, the DSP system is set running
at full speed with no impact on system timing.
To use these emulators, the target board must include a header
that connects the DSP’s JTAG port to the emulator.
For details on target board design issues including mechanical
layout, single processor connections, multiprocessor scan
chains, signal buffering, signal termination, and emulator pod
logic, see the EE-68: Analog Devices JTAG Emulation Technical
Reference on the Analog Devices website ()—
use site search on “EE-68.” This document is updated regularly
to keep pace withimprovements to emulator support.
ADDITIONAL INFORMATIONThis data sheet provides a general overview of the ADSP-
TS101S processor’s architecture and functionality. For detailed
information on the ADSP-TS101S processor’s core architecture
and instruction set, see the ADSP-TS101 TigerSHARC Processor
Programming Reference and the ADSP-TS101 TigerSHARC Pro-
cessor Hardware Reference. For detailed information on the
development tools for this processor, see the VisualDSP++
User’s Guide for TigerSHARC Processors.
PIN FUNCTION DESCRIPTIONSWhile most of the ADSP-TS101S processor’s input pins are nor-
mally synchronous—tied to a specific clock—a few are
asynchronous. For these asynchronous signals, an on-chip syn-
chronization circuit prevents metastability problems. The
synchronous ac specification for asynchronous signals is used
only when predictable cycle-by-cycle behavior is required.
All inputs are sampled by a clock reference, therefore input
specifications (asynchronous minimum pulse widths or syn-
chronous input setup and hold) must be met to guarantee
recognition.
PIN STATES AT RESETThe output pins can be three-stated during normal operation.
The DSP three-states all outputs during reset, allowing these
pins to get to their internal pull-up or pull-down state. Some
output pins (control signals) have a pull-up or pull-down that
maintains a known value during transitions between different
drivers.
PIN DEFINITIONSThe Type column in the following pin definitions tables
describes the pin type, when the pin is used in the system. The
Term (for termination) column describes the pin termination
type if the pin is not used by the system. Note that some pins are
always used (indicated with au symbol).
Table 3.Pin Definitions—Clocks and Reset
Type column symbols: A = asynchronous; G = ground; I = input; O = output; o/d = open drain output; P = power supply; pd = internal pull-down approximately 100kΩ; pu = internal pull-up approximately 100kΩ; T = three-state
Term (for termination) column symbols: epd = external pull-down approximately 10kΩ to VSS; epu = external pull-up approximately 10kΩ
to VDD-IO, nc = not connected; au = always used.The internal pull-down may not be sufficient. A stronger pull-down may be necessary.See Electrical Characteristics on Page20 for maximum and minimum current consumption for pull-up and pull-down resistances.The internal pull-up may not be sufficient. A stronger pull-up may be necessary.
Table 4.LCLK Ratio
Table 5.Pin Definitions—External Port Bus Controls
Type column symbols: A = asynchronous; G = ground; I = input; O = output; o/d = open drain output; P = power supply; pd = internal pull-down approximately 100kΩ; pu = internal pull-up approximately 100kΩ; T = three-state
Term (for termination) column symbols: epd = external pull-down approximately 10kΩ to VSS; epu = external pull-up approximately 10kΩ
to VDD-IO, nc = not connected; au = always used.
The address and data buses may float for several cycles during bus mastership transitions between a TigerSHARC processor and a host. Floating in this case means that these inputs are not driven by any source and that dc-biased terminations are not present. It is not necessary to add pull-ups as there are no reliability issues and the worst-case
power consumption for these floating inputs is negligible. Unconnected address pins may require pull-ups or pull-downs to avoid erroneous slave accesses, depending on
the system. Unconnected data pins may be left floating.The internal pull-up may not be sufficient. A stronger pull-up may be necessary.See Electrical Characteristics on Page20 for maximum and minimum current consumption for pull-up and pull-down resistances.The internal pull-down may not be sufficient. A stronger pull-down may be necessary.
Table 6.Pin Definitions—External Port Arbitration
Type column symbols: A = asynchronous; G = ground; I = input; O = output; o/d = open drain output; P = power supply; pd = internal pull-down approximately 100kΩ; pu = internal pull-up approximately 100kΩ; T = three-state
Term (for termination) column symbols: epd = external pull-down approximately 10kΩ to VSS; epu = external pull-up approximately 10kΩ
to VDD-IO, nc = not connected; au = always used.
Table 5.Pin Definitions—External Port Bus Controls (Continued)
Type column symbols: A = asynchronous; G = ground; I = input; O = output; o/d = open drain output; P = power supply; pd = internal pull-down approximately 100kΩ; pu = internal pull-up approximately 100kΩ; T = three-state
Term (for termination) column symbols: epd = external pull-down approximately 10kΩ to VSS; epu = external pull-up approximately 10kΩ
to VDD-IO, nc = not connected; au = always used.
The internal pull-down may not be sufficient. A stronger pull-down may be necessary.See Electrical Characteristics on Page20 for maximum and minimum current consumption for pull-up and pull-down resistances.3The internal pull-up may not be sufficient. A stronger pull-up may be necessary.
Table 7.Pin Definitions—External Port DMA/Flyby
Type column symbols: A = asynchronous; G = ground; I = input; O = output; o/d = open drain output; P = power supply; pd = internal pull-down approximately 100kΩ; pu = internal pull-up approximately 100kΩ; T = three-state
Term (for termination) column symbols: epd = external pull-down approximately 10kΩ to VSS; epu = external pull-up approximately 10kΩ
to VDD-IO, nc = not connected; au = always used.The internal pull-up may not be sufficient. A stronger pull-up may be necessary.
2See Electrical Characteristics on Page20 for maximum and minimum current consumption for pull-up and pull-down resistances.
Table 6.Pin Definitions—External Port Arbitration (Continued)
Type column symbols: A = asynchronous; G = ground; I = input; O = output; o/d = open drain output; P = power supply; pd = internal pull-down approximately 100kΩ; pu = internal pull-up approximately 100kΩ; T = three-state
Term (for termination) column symbols: epd = external pull-down approximately 10kΩ to VSS; epu = external pull-up approximately 10kΩ
to VDD-IO, nc = not connected; au = always used.
Table 8.Pin Definitions—External Port SDRAM Controller
Type column symbols: A = asynchronous; G = ground; I = input; O = output; o/d = open drain output; P = power supply; pd = internal pull-down approximately 100kΩ; pu = internal pull-up approximately 100kΩ; T = three-state
Term (for termination) column symbols: epd = external pull-down approximately 10kΩ to VSS; epu = external pull-up approximately 10kΩ
to VDD-IO, nc = not connected; au = always used.The internal pull-up may not be sufficient. A stronger pull-up may be necessary.See Electrical Characteristics on Page20 for maximum and minimum current consumption for pull-up and pull-down resistances.The internal pull-down may not be sufficient. A stronger pull-down may be necessary.
Table 9.Pin Definitions—JTAG Port
Type column symbols: A = asynchronous; G = ground; I = input; O = output; o/d = open drain output; P = power supply; pd = internal pull-down approximately 100kΩ; pu = internal pull-up approximately 100kΩ; T = three-state
Term (for termination) column symbols: epd = external pull-down approximately 10kΩ to VSS; epu = external pull-up approximately 10kΩ
to VDD-IO, nc = not connected; au = always used.See the reference onPage11 to the JTAG emulation technical reference EE-68.The internal pull-up may not be sufficient. A stronger pull-up may be necessary.See Electrical Characteristics on Page20 for maximum and minimum current consumption for pull-up and pull-down resistances.
Table 10.Pin Definitions—Flags, Interrupts, and Timer
Type column symbols: A = asynchronous; G = ground; I = input; O = output; o/d = open drain output; P = power supply; pd = internal pull-down approximately 100kΩ; pu = internal pull-up approximately 100kΩ; T = three-state
Term (for termination) column symbols: epd = external pull-down approximately 10kΩ to VSS; epu = external pull-up approximately 10kΩ
to VDD-IO, nc = not connected; au = always used.The internal pull-down may not be sufficient. A stronger pull-down may be necessary.See Electrical Characteristics on Page20 for maximum and minimum current consumption for pull-up and pull-down resistances.The internal pull-up may not be sufficient. A stronger pull-up may be necessary.
Table 11.Pin Definitions—Link Ports
Type column symbols: A = asynchronous; G = ground; I = input; O = output; o/d = open drain output; P = power supply; pd = internal pull-down approximately 100kΩ; pu = internal pull-up approximately 100kΩ; T = three-state
Term (for termination) column symbols: epd = external pull-down approximately 10kΩ to VSS; epu = external pull-up approximately 10kΩ
The link port data pins, if connected or floated for extended periods (for example, token slave with no token master), do not require pull-ups or pull-downs as there are no reliability issues and the worst-case power consumption for these floating inputs is negligible. Floating in this case means that these inputs are not driven by any source and
that dc-biased terminations are not present.The internal pull-down may not be sufficient. A stronger pull-down may be necessary.See Electrical Characteristics on Page20 for maximum and minimum current consumption for pull-up and pull-down resistances.
Table 12.Pin Definitions—Impedance and Drive Strength Control
Type column symbols: A = asynchronous; G = ground; I = input; O = output; o/d = open drain output; P = power supply; pd = internal pull-down approximately 100kΩ; pu = internal pull-up approximately 100kΩ; T = three-state
Term (for termination) column symbols: epd = external pull-down approximately 10kΩ to VSS; epu = external pull-up approximately 10kΩ
to VDD-IO, nc = not connected; au = always used.The internal pull-up may not be sufficient. A stronger pull-up may be necessary.The internal pull-down may not be sufficient. A stronger pull-down may be necessary.
3See Electrical Characteristics on Page20 for maximum and minimum current consumption for pull-up and pull-down resistances.
Table 11.Pin Definitions—Link Ports (Continued)
Type column symbols: A = asynchronous; G = ground; I = input; O = output; o/d = open drain output; P = power supply; pd = internal pull-down approximately 100kΩ; pu = internal pull-up approximately 100kΩ; T = three-state
Term (for termination) column symbols: epd = external pull-down approximately 10kΩ to VSS; epu = external pull-up approximately 10kΩ
to VDD-IO, nc = not connected; au = always used.
Table 13.Control Impedance Selection
Table 14.Drive Strength Selection
STRAP PIN FUNCTION DESCRIPTIONSSome pins have alternate functions at reset. Strap options set
DSP operating modes. During reset, the DSP samples the strap
option pins. Strap pins have an approximately 100kΩ pull-
down for the default value. If a strap pin is not connected to an
external pull-up or logic load, the DSP samples the default value
during reset. If strap pins are connected to logic inputs, a stron-
ger external pull-down may be required to ensure default value
depending on leakage and/or low level input current of the logic
load. To set a mode other than the default mode, connect the
strap pin to a sufficiently stronger external pull-up. In a multi-
processor system, up to eight DSPs may be connected on the
cluster bus, resulting in parallel combination of strap pin pull-
down resistors. Table16 lists and describes each of the DSP’s
strap pins.
Table 15.Pin Definitions—Power, Ground, and Reference
Type column symbols: A = asynchronous; G = ground; I = input; O = output; o/d = open drain output; P = power supply; pd = internal pull-down approximately 100kΩ; pu = internal pull-up approximately 100kΩ; T = three-state
Term (for termination) column symbols: epd = external pull-down approximately 10kΩ to VSS; epu = external pull-up approximately 10kΩ
to VDD-IO, nc = not connected; au = always used.
Table 16.Pin Definitions—I/O Strap Pins
SPECIFICATIONSNote that component specifications are subject to change with-
out notice.
RECOMMENDED OPERATING CONDITIONS
ELECTRICAL CHARACTERISTICS Applies to input and bidirectional pins.For details on internal and external power estimation, including: power vector definitions, current usage descriptions, and formulas, see EE-169, Estimating Power for the
ADSP-TS101S on the Analog Devices website—use site search on “EE-169” (). This document is updated regularly to keep pace with silicon revisions.Applies to output and bidirectional pins.Applies to input pins with internal pull-downs (pd).Applies to input pins without internal pull-ups (pu).Applies to input pins with internal pull-ups (pu).Applies to three-stateable pins without internal pull-downs (pd).Applies to open drain (od) pins with 500Ω pull-ups (pu).Applies to three-stateable pins with internal pull-downs (pd).Applies to three-stateable pins without internal pull-ups (pu).Applies to three-stateable pins with internal pull-ups (pu).
ABSOLUTE MAXIMUM RATINGS
ESD SENSITIVITY
TIMING SPECIFICATIONSWith the exception of link port, IRQ3–0, DMAR3–0, TMR0E,
FLAG3–0 (input), and TRST pins, all ac timing for the ADSP-
TS101S is relative to a reference clock edge. Because input
setup/hold, output valid/hold, and output enable/disable times
are relative to a clock edge, the timing data for the ADSP-
TS101S has few calculated (formula-based) values. For informa-
tion on ac timing, see General AC Timing. For information on
link port transfer timing, see Link Ports Data Transfer and
Token Switch Timing on Page29.
General AC TimingTiming is measured on signals when they cross the 1.5V level as
described in Figure15 on Page28. All delays (in nanoseconds)
are measured between the point that the first signal reaches
1.5V and the point that the second signal reaches 1.5V.
The ac asynchronous timing data for the IRQ3–0, DMAR3–0,
TMR0E, FLAG3–0 (input), and TRST pins appears in Table17.
The general ac timing data appears in Table17, Table25, and
Table26. All ac specifications are measured with the load speci-
fied in Figure7, and with the output drive strength set to
strength4. Output valid and hold are based on standard capaci-
tive loads: 30pF on all pins. The delay and hold specifications
given should be derated by a drive strength related factor for
loads other than the nominal value of 30pF.
In order to calculate the output valid and hold times for differ-
ent load conditions and/or output drive strengths, refer to
Figure31 on Page34 through Figure38 on Page36 (Rise and
Fall Time vs. Load Capacitance) and Figure39 on Page36 (Out-
put Valid vs. Load Capacitance and Drive Strength).
For power-up sequencing, power-up reset, and normal reset
(hot reset) timing requirements, refer respectively to Table22
and Figure12, Table23 and Figure13, and Table24 and
Figure14.
Internal (Core) Supply Voltage (VDD)1Stresses greater than those listed above may cause permanent damage to the device.
These are stress ratings only; functional operation of the device at these or any other
conditions greater than those indicated in the operational sections of this specification
is not implied. Exposure to absolute maximum rating conditions for extended periods
may affect device reliability.
–0.3 V to +1.40 V
Analog (PLL) Supply Voltage (VDD_A)1–0.3 V to +1.40 V
External (I/O) Supply Voltage (VDD_IO)1–0.3 V to +4.6 V
Input Voltage1–0.5 V to VDD_IO+0.5 V
Output Voltage Swing1–0.5 V to VDD_IO+0.5 V
Storage Temperature Range1–65ºC to +150ºC
CAUTIONESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the ADSP-TS101S features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
Figure 7.Equivalent Device Loading for AC Measurements
(Includes All Fixtures)
Table 17.AC Asynchronous Signal Specifications
(All values in this table are in nanoseconds.)These input pins do not need to be synchronized to a clock reference.This pin is a strap option. During reset, an internal resistor pulls the pin low.For output specifications, see Table25 and Table26.
Table 18.Reference Clocks—Core Clock (CCLK) Cycle TimeCCLK is the internal processor clock or instruction cycle time. The period of this clock is equal to the system clock period (tSCLK) divided by the system clock ratio
(SCLKRAT2–0). For information on available part numbers for different internal processor clock rates, see the Ordering Guide on Page44.
Figure 8.Reference Clocks—Core Clock (CCLK) Cycle Time
Table 19.Reference Clocks—Local Clock (LCLK) Cycle Time1For more information, see Table3 on Page12.For more information, see Clock Domains on Page9.LCLK_P and SCLK_P must be connected to the same source.The value of (tLCLK / LCLKRAT2-0) must not violate the specification for tCCLK.
5Actual input jitter should be combined with ac specifications for accurate timing analysis.Jitter specification is maximum peak-to-peak time interval error (TIE) jitter.
Figure 9.Reference Clocks—Local Clock (LCLK) Cycle Time
