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ADSP-BF561-ADSP-BF561SBB600-ADSP-BF561SKBCZ500
Blackfin Symmetric Multi-Processor for Consumer Multimedia
Blackfin and the Blackfin logo are registered trademarks of Analog Devices, Inc.
Rev. PrD
FEATURES
Dual Symmetric 600 MHz High Performance Blackfin Cores
328 Kbytes of On-chip Memory (See Memory Info onPage3)
Each Blackfin Core Includes:
Two 16-Bit MACs, Two 40-Bit ALUs, Four 8-Bit Video ALUs,
40-Bit Shifter
RISC-Like Register and Instruction Model for Ease of Pro-
gramming and Compiler-Friendly Support
Advanced Debug, Trace, and Performance Monitoring
0.8 - 1.2V core VDD
3.3V and 2.5V Tolerant I/O
256-Ball Mini BGA and 297-Ball PBGA Package Options
PERIPHERALS
Two Parallel Input/Output Peripheral Interface Units Sup-
porting ITU-R 656 Video and Glueless Interface to Analog
Front End ADCs
Two Dual Channel, Full Duplex Synchronous Serial Ports Sup-
porting Eight Stereo I2S Channels
Dual 16 Channel DMA Controllers and one internal memory
DMA controller
12 General Purpose 32-bit Timer/Counters, with PWM
Capability
SPI-Compatible Port
UART with Support for IrDA®
Dual Watchdog Timers
48 Programmable Flags
On-Chip Phase Locked Loop Capable of 1x to 63x Frequency
MultiplicationFigure 1.Functional Block Diagram
TABLE OF CONTENTSGeneral Description ................................................. 3
Portable Low Power Architecture ............................. 3
Blackfin Processor Core .......................................... 3
Memory Architecture ............................................ 4
DMA Controllers .................................................. 8
WatchDog Timers ................................................ 8
Serial Ports (SPORTs) ............................................ 9
Serial Peripheral Interface (SPI) Port ......................... 9
UART Port .......................................................... 9
Programmable Flags (PFx) .................................... 10
Timers ............................................................. 10
Parallel Peripheral Interface ................................... 10
Dynamic Power Management ................................ 11
Voltage Regulation .............................................. 12
Clock Signals ..................................................... 12
Booting Modes ................................................... 13
Instruction Set Description ................................... 14
Development Tools ............................................. 14
Designing an Emulator Compatible
Processor Board (Target) ................................... 15
Additional Information ........................................ 15
Pin Descriptions .................................................... 16
Specifications ........................................................ 20
Recommended Operating Conditions ...................... 20
Electrical Characteristics ....................................... 20
Absolute Maximum Ratings .................................. 21
ESD Sensitivity ................................................... 21
Timing Specifications ........................................... 22
Clock and Reset Timing ..................................... 23
Asynchronous Memory Read Cycle Timing ............ 24
Asynchronous Memory Write Cycle Timing ........... 25
SDRAM Interface Timing .................................. 26
External Port Bus Request and Grant Cycle Timing .. 27
Parallel Peripheral Interface Timing ..................... 28
Serial Ports ..................................................... 29
Serial Peripheral Interface (SPI) Port—Master Timing 34
Serial Peripheral Interface (SPI) Port—Slave Timing . 35
Universal Asynchronous Receiver Transmitter (UART)
Port—Receive and Transmit Timing .................. 36
Timer Cycle Timing .......................................... 37
Programmable Flags Cycle Timing ....................... 38
JTAG Test And Emulation Port Timing ................. 39
Output Drive Currents ......................................... 40
Power Dissipation ............................................... 42
Test Conditions .................................................. 43
Environmental Conditions .................................... 46
256-ball MBGA Pinout ............................................ 47
297-ball PBGA Pinout ............................................. 49
Outline Dimensions ................................................ 51
Outline Dimensions ................................................ 52
Ordering Guide ..................................................... 52
REVISION HISTORY
Revision PrD:Edits made to pinlists and timing specification.
Added graphics for the output drivers.
GENERAL DESCRIPTIONThe ADSP-BF561 processor is a high performance member of
the Blackfin family of products targeting a variety of multimedia
and telecommunications applications. At the heart of this device
are two independent Analog Devices Blackfin processors. These
Blackfin processors combine a dual-MAC state-of-the-art signal
processing engine, the advantage of a clean, orthogonal RISC-
like microprocessor instruction set, and single instruction, mul-
tiple-data (SIMD) multimedia capabilities into a single
instruction set architecture. The ADSP-BF561 device integrates
a general purpose set of digital imaging peripherals.
The ADSP-BF561 processor has 328 Kbytes of on-chip memory.
Each Blackfin core includes:16 Kbytes of Instruction SRAM/Cache16 Kbytes of Instruction SRAM32 Kbytes of Data SRAM/Cache32 Kbytes of Data SRAM4 Kbytes of Scratchpad SRAM
Additional on-chip memory peripherals include:128 Kbytes of Low Latency On-chip L2 SRAMFour Channel Internal Memory DMA ControllerExternal Memory controller with glueless support for
SDRAM. Mobile SDRAM, SRAM, and Flash.
PORTABLE LOW POWER ARCHITECTUREBlackfin processors provide world class power management and
performance for embedded signal processing applications.
Blackfin processors are designed in a low power and low voltage
design methodology and feature Dynamic Power Management.
Dynamic Power Management is the ability to vary both the volt-
age and frequency of operation to significantly lower the overall
power dissipation. This translates into an exponential reduction
in power dissipation, providing longer battery life to portable
applications.
BLACKFIN PROCESSOR COREAs shown in Figure2, each Blackfin core contains two multi-
plier/accumulators (MACs), two 40-bit ALUs, four video ALUs,
and a single shifter. The computational units process 8-bit, 16-
bit, or 32-bit data from the register file.
Figure 2.Blackfin Processor Core
Each MAC performs a 16-bit by 16-bit multiply in every cycle,
with accumulation to a 40-bit result, providing 8 bits of
extended precision. The ALUs perform a standard set of arith-
metic and logical operations. With two ALUs capable of
operating on 16- or 32-bit data, the flexibility of the computa-
tion units covers the signal processing requirements of a varied
set of application needs.
Each of the two 32-bit input registers can be regarded as two 16-
bit halves, so each ALU can accomplish very flexible single 16-
bit arithmetic operations. By viewing the registers as pairs of 16-
bit operands, dual 16-bit or single 32-bit operations can be
accomplished in a single cycle. By further taking advantage of
the second ALU, quad 16-bit operations can be accomplished
simply, accelerating the per cycle throughput.
The powerful 40-bit shifter has extensive capabilities for per-
forming shifting, rotating, normalization, extraction, and
depositing of data. The data for the computational units is
found in a multi-ported register file of sixteen 16-bit entries or
eight 32-bit entries.
A powerful program sequencer controls the flow of instruction
execution, including instruction alignment and decoding. The
sequencer supports conditional jumps and subroutine calls, as
well as zero overhead looping. A loop buffer stores instructions
locally, eliminating instruction memory accesses for tight
looped code.
Two data address generators (DAGs) provide addresses for
simultaneous dual operand fetches from memory. The DAGs
share a register file containing four sets of 32-bit Index, Modify,
Length, and Base registers. Eight additional 32-bit registers pro-
vide pointers for general indexing of variables and stack
locations.
Blackfin processors support a modified Harvard architecture in
combination with a hierarchical memory structure. Level 1 (L1)
memories are those that typically operate at the full processor
speed with little or no latency. Level 2 (L2) memories are other
memories, on-chip or off-chip, that may take multiple processor
cycles to access. At the L1 level, the instruction memory holds
instructions only. The two data memories hold data, and a dedi-
cated scratchpad data memory stores stack and local variable
information. At the L2 level, there is a single unified memory
space, holding both instructions and data.
In addition, half of L1 instruction memory and half of L1 data
memories may be configured as either Static RAMs (SRAMs) or
caches. The Memory Management Unit (MMU) provides mem-
ory protection for individual tasks that may be operating on the
core and may protect system registers from unintended access.
The architecture provides three modes of operation: User mode,
Supervisor mode, and Emulation mode. User mode has
restricted access to certain system resources, thus providing a
protected software environment, while supervisor mode has
unrestricted access to the system and core resources.
The Blackfin instruction set has been optimized so that 16-bit
op-codes represent the most frequently used instructions,
resulting in excellent compiled code density. Complex DSP
port a limited multi-issue capability, where a 32-bit instruction
can be issued in parallel with two 16-bit instructions, allowing
the programmer to use many of the core resources in a single
instruction cycle.
The Blackfin assembly language uses an algebraic syntax for
ease of coding and readability. The architecture has been opti-
mized for use in conjunction with the VisualDSP C/C++
compiler, resulting in fast and efficient software
implementations.
MEMORY ARCHITECTUREThe ADSP-BF561 views memory as a single unified 4Gbyte
address space, using 32-bit addresses. All resources including
internal memory, external memory, and I/O control registers
occupy separate sections of this common address space. The
memory portions of this address space are arranged in a hierar-
chical structure to provide a good cost/performance balance of
some very fast, low latency memory as cache or SRAM very
close to the processor, and larger, lower cost and performance
memory systems farther away from the processor. The ADSP-
BF561 memory map is shown in Figure3.
The L1 memory system in each core is the highest performance
memory available to each Blackfin core. The L2 memory pro-
vides additional capacity with lower performance. Lastly, the
off-chip memory system, accessed through the External Bus
Interface Unit (EBIU), provides expansion with SDRAM, flash
memory, and SRAM, optionally accessing more than
768Mbytes of physical memory. The memory DMA controllers
provide high bandwidth data movement capability. They can
perform block transfers of code or data between the internal
L1/L2 memories and the external memory spaces.
Internal (On-chip) MemoryThe ADSP-BF561 has four blocks of on-chip memory providing
high bandwidth access to the core.
The first is the L1 instruction memory of each Blackfin core
consisting of 16Kbytes of 4-way set-associative cache memory
and 16Kbytes of SRAM. The cache memory may also be config-
ured as an SRAM. This memory is accessed at full processor
speed. When configured as SRAM, each of the two 16K banks of
memory is broken into 4K sub-banks which can be indepen-
dently accessed by the processor and DMA.
The second on-chip memory block is the L1 data memory of
each Blackfin core which consists of four banks of 16Kbytes
each. Two of the L1 data memory banks can be configured as
one way of a two-way set-associative cache or as an SRAM. The
other two banks are configured as SRAM. All banks are accessed
at full processor speed. When configured as SRAM, each of the
four 16K banks of memory is broken into 4K sub-banks which
can be independently accessed by the processor and DMA.
The third memory block associated with each core is a 4 Kbyte
scratchpad SRAM which runs at the same speed as the L1 mem-
ories, but is only accessible as data SRAM (it cannot be
configured as cache memory and is not accessible via DMA).
The fourth on-chip memory system is the L2 SRAM memory
array which provides 128Kbytes of high speed SRAM operating
at one half the frequency of the core, and slightly longer latency
than the L1 memory banks. The L2 memory is a unified instruc-
tion and data memory and can hold any mixture of code and
data required by the system design. The Blackfin cores share a
dedicated low latency 64-bit wide data path port into the L2
SRAM memory.
Each Blackfin core processor has its own set of core Memory
Mapped Registers (MMRs) but share the same system MMR
registers and 128 Kbytes L2 SRAM memory.
External (Off-Chip) MemoryThe ADSP-BF561 external memory is accessed via the External
Bus Interface Unit (EBIU). This interface provides a glueless
connection to up to four banks of synchronous DRAM
(SDRAM) as well as up to four banks of asynchronous memory
devices including flash, EPROM, ROM, SRAM, and memory
mapped I/O devices.
The PC133 compliant SDRAM controller can be programmed
to interface to up to four banks of SDRAM, with each bank con-
taining between 16 Mbytes and 128 Mbytes providing access to
up to 512 Mbytes of SDRAM. Each bank is independently pro-
grammable and is contiguous with adjacent banks regardless of
Figure 3.Memory Map
flexible configuration and upgradability of system memory
while allowing the core to view all SDRAM as a single, contigu-
ous, physical address space.
The asynchronous memory controller can also be programmed
to control up to four banks of devices with very flexible timing
parameters for a wide variety of devices. Each bank occupies a Mbyte segment regardless of the size of the devices used so
that these banks will only be contiguous if fully populated with Mbytes of memory.
I/O Memory SpaceBlackfin processors do not define a separate I/O space. All
resources are mapped through the flat 32-bit address space. On-
chip I/O devices have their control registers mapped into mem-
ory mapped registers (MMRs) at addresses near the top of the Gbyte address space. These are separated into two smaller
blocks, one which contains the control MMRs for all core func-
tions, and the other which contains the registers needed for
setup and control of the on-chip peripherals outside of the core.
The core MMRs are accessible only by the core and only in
supervisor mode and appear as reserved space by on-chip
peripherals. The system MMRs are accessible by the core in
supervisor mode and can be mapped as either visible or reserved
to other devices, depending on the system protection model
desired.
BootingThe ADSP-BF561 contains a small boot kernel, which config-
ures the appropriate peripheral for booting. If the ADSP-BF561
is configured to boot from boot ROM memory space, the pro-
cessor starts executing from the on-chip boot ROM.
Event HandlingThe event controller on the ADSP-BF561 handles all asynchro-
nous and synchronous events to the processor. The ADSP-
BF561 provides event handling that supports both nesting and
prioritization. Nesting allows multiple event service routines to
be active simultaneously. Prioritization ensures that servicing of
a higher priority event takes precedence over servicing of a
lower priority event. The controller provides support for five
different types of events: Emulation – An emulation event causes the processor to
enter emulation mode, allowing command and control of
the processor via the JTAG interface.Reset – This event resets the processor.Non-Maskable Interrupt (NMI) – The NMI event can be
generated by the software watchdog timer or by the NMI
input signal to the processor. The NMI event is frequently
used as a power down indicator to initiate an orderly shut
down of the system.Exceptions – Events that occur synchronously to program
flow, i.e., the exception will be taken before the instruction
is allowed to complete. Conditions such as data alignment
violations, undefined instructions, etc. cause exceptions.Interrupts – Events that occur asynchronously to program
flow. They are caused by timers, peripherals, input pins,
and an explicit software instruction.
Each event has an associated register to hold the return address
and an associated “return from event” instruction. When an
event is triggered, the state of the processor is saved on the
supervisor stack.
The ADSP-BF561 event controller consists of two stages, the
Core Event Controller (CEC) and the System Interrupt Control-
ler (SIC). The Core Event Controller works with the System
Interrupt Controller to prioritize and control all system events.
Conceptually, interrupts from the peripherals enter into the
SIC, and are then routed directly into the general-purpose inter-
rupts of the CEC.
Core Event Controller (CEC)The CEC supports nine general-purpose interrupts (IVG15–7),
in addition to the dedicated interrupt and exception events. Of
these general-purpose interrupts, the two lowest priority inter-
rupts (IVG15–14) are recommended to be reserved for software
interrupt handlers, leaving seven prioritized interrupt inputs to
support the peripherals of the ADSP-BF561. Table1 describes
the inputs to the CEC, identifies their names in the Event Vector
Table (EVT), and lists their priorities.
System Interrupt Controller (SIC)The System Interrupt Controller provides the mapping and
Table 1.Core Event Controller (CEC)
Although the ADSP-BF561 provides a default mapping, the user
can alter the mappings and priorities of interrupt events by writ-
ing the appropriate values into the Interrupt Assignment
Registers (SIC_IAR7–0). Table2 describes the inputs into the
SIC and the default mappings into the CEC.
Event ControlThe ADSP-BF561 provides the user with a very flexible mecha-
nism to control the processing of events. In the CEC, three
registers are used to coordinate and control events. Each of the
registers is 16-bits wide, while each bit represents a particular
event class.CEC Interrupt Latch Register (ILAT) – The ILAT register
indicates when events have been latched. The appropriate
bit is set when the processor has latched the event and
cleared when the event has been accepted into the system.
This register is updated automatically by the controller, but
may be written only when its corresponding IMASK bit is
cleared.CEC Interrupt Mask Register (IMASK) – The IMASK reg-
ister controls the masking and unmasking of individual
events. When a bit is set in the IMASK register, that event is
unmasked and will be processed by the CEC when asserted.
A cleared bit in the IMASK register masks the event
Table 2.Peripheral Interrupt Source Reset StatePeripheral Interrupt Channel Number
2Default User IVG Interrupt
Table 2.Peripheral Interrupt Source Reset State (Continued)
This register may be read from or written to while in super-
visor mode. (Note that general-purpose interrupts can be
globally enabled and disabled with the STI and CLI
instructions.)CEC Interrupt Pending Register (IPEND) – The IPEND
register keeps track of all nested events. A set bit in the
IPEND register indicates the event is currently active or
nested at some level. This register is updated automatically
by the controller but may be read while in supervisor mode.
The SIC allows further control of event processing by providing
six 32-bit interrupt control and status registers. Each register
contains a bit corresponding to each of the peripheral interrupt
events shown in Table2.SIC Interrupt Mask Register
(SIC_IMASK0, SIC_IMASK1)–
This register controls the masking and unmasking of each
peripheral interrupt event. When a bit is set in the register,
that peripheral event is unmasked and will be processed by
the system when asserted. A cleared bit in the register
masks the peripheral event thereby preventing the proces-
sor from servicing the event. SIC Interrupt Status Register
(SIC_ISR0, SIC_ISR1)–
As multiple peripherals can be mapped to a single event,
this register allows the software to determine which periph-
eral event source triggered the interrupt. A set bit indicates
the peripheral is asserting the interrupt, a cleared bit indi-
cates the peripheral is not asserting the event.SIC Interrupt Wakeup Enable Register
(SIC_IWR0, SIC_IWR1)–
By enabling the corresponding bit in this register, each
peripheral can be configured to wake up the processor,
should the processor be in a powered down mode when the
event is generated.
Because multiple interrupt sources can map to a single general-
purpose interrupt, multiple pulse assertions can occur simulta-
neously, before or during interrupt processing for an interrupt
event already detected on this interrupt input. The IPEND reg-
ister contents are monitored by the SIC as the interrupt
acknowledgement.
The appropriate ILAT register bit is set when an interrupt rising
edge is detected (detection requires two core clock cycles). The
bit is cleared when the respective IPEND register bit is set. The
IPEND bit indicates that the event has entered into the proces-
sor pipeline. At this point the CEC will recognize and queue the
next rising edge event on the corresponding event input. The
minimum latency from the rising edge transition of the general-
purpose interrupt to the IPEND output asserted is three core
clock cycles; however, the latency can be much higher, depend-
ing on the activity within and the mode of the processor.
DMA CONTROLLERSThe ADSP-BF561 has multiple, independent DMA controllers
that support automated data transfers with minimal overhead
als. Additionally, DMA transfers can be accomplished between
any of the DMA-capable peripherals and external devices con-
nected to the external memory interfaces, including the
SDRAM controller and the asynchronous memory controller.
DMA-capable peripherals include the SPORTs, SPI port,
UART, and PPI. Each individual DMA-capable peripheral has
at least one dedicated DMA channel.
The ADSP-BF561 DMA controllers support both 1-dimen-
sional (1D) and 2-dimensional (2D) DMA transfers. DMA
transfer initialization can be implemented from registers or
from sets of parameters called descriptor blocks.
The 2D DMA capability supports arbitrary row and column
sizes up to 64K elements by 64K elements, and arbitrary row
and column step sizes up to +/– 32K elements. Furthermore, the
column step size can be less than the row step size, allowing
implementation of interleaved data streams. This feature is
especially useful in video applications where data can be de-
interleaved on the fly.
Examples of DMA types supported by the ADSP-BF561 DMA
controllers include:A single, linear buffer that stops upon completionA circular, auto-refreshing buffer that interrupts on each
full or fractionally full buffer1-D or 2-D DMA using a linked list of descriptors2-D DMA using an array of descriptors, specifying only the
base DMA address within a common page
In addition to the dedicated peripheral DMA channels, each
DMA Controller has four memory DMA channels provided for
transfers between the various memories of the ADSP-BF561
system. These enable transfers of blocks of data between any of
the memories—including external SDRAM, ROM, SRAM, and
flash memory—with minimal processor intervention. Memory
DMA transfers can be controlled by a very flexible descriptor-
based methodology or by a standard register-based autobuffer
mechanism.
Further, the ADSP-BF561 has a four channel Internal Memory
DMA (IMDMA) Controller. The IMDMA Controller allows
data transfers between any of the internal L1 and L2 memories.
WATCHDOG TIMERSEach ADSP-BF561 core includes a 32-bit timer, which can be
used to implement a software watchdog function. A software
watchdog can improve system availability by forcing the proces-
sor to a known state, via generation of a hardware reset, non-
maskable interrupt (NMI), or general-purpose interrupt, if the
timer expires before being reset by software. The programmer
initializes the count value of the timer, enables the appropriate
interrupt, then enables the timer. Thereafter, the software must
reload the counter before it counts to zero from the pro-
grammed value. This protects the system from remaining in an
unknown state where software, which would normally reset the
timer, has stopped running due to an external noise condition
or software error.
After a reset, software can determine if the watchdog was the
source of the hardware reset by interrogating a status bit in the
timer control register, which is set only upon a watchdog gener-
ated reset.
The timer is clocked by the system clock (SCLK), at a maximum
frequency of fSCLK.
SERIAL PORTS (SPORTS)The ADSP-BF561 incorporates two dual-channel synchronous
serial ports (SPORT0 and SPORT1) for serial and multiproces-
sor communications. The SPORTs support the following
features:2S capable operation.Bidirectional operation – Each SPORT has two sets of inde-
pendent transmit and receive pins, enabling eight channels
of I2S stereo audio.Buffered (8-deep) transmit and receive ports – Each port
has a data register for transferring data words to and from
other DSP components and shift registers for shifting data
in and out of the data registers.Clocking – Each transmit and receive port can either use an
external serial clock or generate its own, in frequencies
ranging from (fSCLK/131,070)Hz to (fSCLK/2)Hz.Word length – Each SPORT supports serial data words
from 3 to 32bits in length, transferred most-significant-bit
first or least-significant-bit first.Framing – Each transmit and receive port can run with or
without frame sync signals for each data word. Frame sync
signals can be generated internally or externally, active high
or low, and with either of two pulsewidths and early or late
frame sync.Companding in hardware – Each SPORT can perform
A-law or µ-law companding according to ITU recommen-
dation G.711. Companding can be selected on the transmit
and/or receive channel of the SPORT without additional
latencies.DMA operations with single-cycle overhead – Each SPORT
can automatically receive and transmit multiple buffers of
memory data. The DSP can link or chain sequences of
DMA transfers between a SPORT and memory.Interrupts – Each transmit and receive port generates an
interrupt upon completing the transfer of a data word or
after transferring an entire data buffer or buffers through
DMA.Multichannel capability – Each SPORT supports 128 chan-
nels out of a 1024-channel window and is compatible with
the H.100, H.110, MVIP-90, and HMVIP standards.
SERIAL PERIPHERAL INTERFACE (SPI) PORTThe ADSP-BF561 has one SPI-compatible port that enables the
processor to communicate with multiple SPI-compatible
devices.
The SPI interface uses three pins for transferring data: two data
pins (Master Output-Slave Input, MOSIx, and Master Input-
Slave Output, MISO) and a clock pin (Serial Clock, SCK). One
SPI chip select input pin (SPISS) lets other SPI devices select the
DSP, and seven SPI chip select output pins (SPISEL7–1) let the
DSP select other SPI devices. The SPI select pins are reconfig-
ured Programmable Flag pins. Using these pins, the SPI ports
provide a full duplex, synchronous serial interface, which sup-
ports both master and slave modes and multimaster
environments.
The baud rate and clock phase/polarities for the SPI port are
programmable (see SPI Clock Rate equation), and each has an
integrated DMA controller, configurable to support transmit or
receive data streams. The SPI DMA controller can only service
unidirectional accesses at any given time.
During transfers, the SPI port simultaneously transmits and
receives by serially shifting data in and out on its two serial data
lines. The serial clock line synchronizes the shifting and sam-
pling of data on the two serial data lines.
UART PORTThe ADSP-BF561 provides a full duplex Universal Asynchro-
nous Receiver/Transmitter (UART) port, fully compatible with
PC-standard UARTs. The UART port provides a simplified
UART interface to other peripherals or hosts, supporting full
duplex, DMA supported, asynchronous transfers of serial data.
The UART port includes support for 5 to 8data bits; 1 or 2stop
bits; and none, even, or odd parity. The UART port supports
two modes of operation, as follows:PIO (Programmed I/O) – The processor sends or receives
data by writing or reading I/O-mapped UATX or UARX
registers, respectively. The data is double buffered on both
transmit and receive.DMA (Direct Memory Access) – The DMA controller
transfers both transmit and receive data. This reduces the
number and frequency of interrupts required to transfer
data to and from memory. The UART has two dedicated
DMA channels, one for transmit and one for receive. These
DMA channels have lower priority than most DMA chan-
nels because of their relatively low service rates.
The baud rate (see UART Clock Rate equation), serial data for-
mat, error code generation and status, and interrupts for the
UART port are programmable. In the UART Clock Rate equa-
tion, the divisor (D) can be 1 to 65536.
SPI Clock RatefSCLKSPIBAUD×-----------------------------------=
UART Clock RatefSCLKD×----------------=
The UART’s programmable features include:Supporting bit rates ranging from (fSCLK/ 1048576) to
(fSCLK/16) bits per second.Supporting data formats from 7 to 12bits per frame.Both transmit and receive operations can be configured to
generate maskable interrupts to the processor.
In conjunction with the general-purpose timer functions, auto-
baud detection is supported.
The capabilities of the UART are further extended with support
for the Infrared Data Association (IrDA®) Serial Infrared Physi-
cal Layer Link Specification (SIR) protocol.
PROGRAMMABLE FLAGS (PFX)The ADSP-BF561 has 48 bi-directional, general-purpose I/O,
Programmable Flag (PF47–0) pins. The Programmable Flag
pins have special functions for SPI port operation. Each pro-
grammable flag can be individually controlled by manipulation
of the flag control, status, and interrupt registers as follows:Flag Direction Control Register – Specifies the direction of
each individual PFx pin as input or output.Flag Control and Status Registers – Rather than forcing the
software to use a read-modify-write process to control the
setting of individual flags, the ADSP-BF561 employs a
"write one to set" and "write one to clear" mechanism that
allows any combination of individual flags to be set or
cleared in a single instruction, without affecting the level of
any other flags. Two control registers are provided, one
register is written-to in order to set flag values while
another register is written-to in order to clear flag values.
Reading the flag status register allows software to interro-
gate the sense of the flags.Flag Interrupt Mask Registers – The Flag Interrupt Mask
Registers allow each individual PFx pin to function as an
interrupt to the processor. Similar to the Flag Control Reg-
isters that are used to set and clear individual flag values,
one Flag Interrupt Mask Register sets bits to enable an
interrupt function, and the other Flag Interrupt Mask reg-
ister clears bits to disable an interrupt function. PFx pins
defined as inputs can be configured to generate hardware
interrupts, while output PFx pins can be configured to gen-
erate software interrupts.Flag Interrupt Sensitivity Registers – The Flag Interrupt
Sensitivity Registers specify whether individual PFx pins
are level- or edge-sensitive and specify, if edge-sensitive,
whether just the rising edge or both the rising and falling
edges of the signal are significant. One register selects the
type of sensitivity, and one register selects which edges are
significant for edge-sensitivity.
TIMERSThere are fourteen (14) programmable timer units in the ADSP-
BF561.
Each of the twelve general-purpose timer units can be indepen-
The general-purpose timer units can be used in conjunction
with the UART to measure the width of the pulses in the data
stream to provide an auto-baud detect function for a serial
channel. The general-purpose timers can generate interrupts to
the processor core providing periodic events for synchroniza-
tion, either to the processor clock or to a count of external
signals.
In addition to the twelve general-purpose programmable tim-
ers, another timer is also provided for each core. These extra
timers are clocked by the internal processor clock (CCLK) and
are typically used as a system tick clock for generation of operat-
ing system periodic interrupts.
PARALLEL PERIPHERAL INTERFACEThe processor provides two Parallel Peripheral Interfaces (PPI0,
PPI1) that can connect directly to parallel A/D and D/A con-
verters, ITU-R-601/656 video encoders and decoders, and other
general purpose peripherals. Each PPI consists of a dedicated
input clock pin, up to 3 frame synchronization pins, and up to
16 data pins.
General Purpose Mode DescriptionsThe general-purpose modes of the PPI are intended to suit a
wide variety of data capture and transmission applications. The
modes are divided into four main categories, each allowing up
to 16 bits of data transfer per PPI_CLK cycle:Data Receive with Internally Generated Frame SyncsData Receive with Externally Generated Frame SyncsData Transmit with Internally Generated Frame SyncsData Transmit with Externally Generated Frame Syncs
These modes support ADC/DAC connections, as well as video
communication with hardware signaling. Many of the modes
support more than one level of frame synchronization. If
desired, a programmable delay can be inserted between asser-
tion of a frame sync and reception / transmission of data.
ITU -R 656 Mode DescriptionsIn ITU-R 656 mode, the PPI receives and parses a data stream of
8-bit or 10-bit data elements. On-chip decode of embedded pre-
amble control and synchronization information is supported.
Three distinct ITU-R 656 modes are supported:Active Video Only modeVertical Blanking Only modeEntire Field mode
Active Video Only ModeIn this mode, the PPI does not read in any data between the End
of Active Video (EAV) and Start of Active Video (SAV) pream-
ble symbols, or any data present during the vertical blanking
intervals. In this mode, the control byte sequences are not stored
to memory; they are filtered by the PPI.
Vertical Blanking Interval ModeIn this mode, the PPI transfers vertical blanking interval (VBI)
data, as well as horizontal blanking information and control
byte sequences on VBI lines.
Entire Field ModeIn this mode, the entire incoming bitstream is read in through
the PPI. This includes active video, control preamble sequences,
and ancillary data that may be embedded in horizontal and ver-
tical blanking intervals.
Though not explicitly supported, ITU-R 656 output functional-
ity can be achieved by setting up the entire frame structure
(including active video, blanking and control information) in
memory and streaming the data out of the PPI in a frame
syncless mode. The processor’s 2D DMA features facilitate this
transfer by allowing the static frame buffer (blanking and con-
trol codes) to be placed in memory once, and simply updating
the active video information on a per-frame basis.
DYNAMIC POWER MANAGEMENTThe ADSP-BF561 provides four power management modes and
one power management state, each with a different perfor-
mance/power profile. In addition, Dynamic Power
Management provides the control functions to dynamically
alter the processor core supply voltage, further reducing power
dissipation. Control of clocking to each of the ADSP-BF561
peripherals also reduces power consumption. See Table3 for a
summary of the power settings for each mode.
Full-On Operating Mode – Maximum PerformanceIn the Full-On mode, the PLL is enabled and is not bypassed,
providing capability for maximum operational frequency. This
is the default execution state in which maximum performance
can be achieved. The processor cores and all enabled peripherals
run at full speed.
Active Operating Mode – Moderate Power SavingsIn the Active mode, the PLL is enabled but bypassed. Because
the PLL is bypassed, the processor’s core clock (CCLK) and sys-
tem clock (SCLK) run at the input clock (CLKIN) frequency. In
this mode, the CLKIN to CCLK multiplier ratio can be changed,
although the changes are not realized until the Full-On mode is
entered. DMA access is available to appropriately configured L1
and L2 memories.
In the Active mode, it is possible to disable the PLL through the
PLL Control register (PLL_CTL). If disabled, the PLL must be
re-enabled before transitioning to the Full-On or Sleep modes.
Sleep Operating Mode—High Dynamic Power SavingsThe Sleep mode reduces power dissipation by disabling the
clock to the processor core (CCLK). The PLL and system clock
(SCLK), however, continue to operate in this mode. Typically an
external event will wake up the processor. When in the Sleep
mode, assertion of wakeup will cause the processor to sense the
value of the BYPASS bit in the PLL Control register (PLL_CTL).
When in the Sleep mode, system DMA access is only available
to external memory, not to L1 or on-chip L2 memory.
Deep Sleep Operating Mode—Maximum Dynamic Power
SavingsThe Deep Sleep mode maximizes power savings by disabling the
clocks to the processor cores (CCLK) and to all synchronous
peripherals (SCLK). Asynchronous peripherals will not be able
to access internal resources or external memory. This powered-
down mode can only be exited by assertion of the reset interrupt
(RESET). If BYPASS is disabled, the processor will transition to
the Full On mode. If BYPASS is enabled, the processor will tran-
sition to the Active mode.
Hibernate Operating State—Maximum Static Power
SavingsThe Hibernate state maximizes static power savings by disabling
the voltage and clocks to the processor core (CCLK) and to all
the synchronous peripherals (SCLK). The internal voltage regu-
lator for the processor can be shut off by writing b#00 to the
FREQ bits of the VR_CTL register. This disables both CCLK
and SCLK. Furthermore, it sets the internal power supply volt-
age (VDDINT) to 0 V to provide the lowest static power
dissipation. Any critical information stored internally (memory
contents, register contents, etc.) must be written to a non-vola-
tile storage device prior to removing power if the processor state
is to be preserved. Since VDDEXT is still supplied in this mode, all
of the external pins three-state, unless otherwise specified. This
allows other devices that may be connected to the processor to
have power still applied without drawing unwanted current.
The internal supply regulator can be woken up by asserting the
RESET pin.
Power SavingsAs shown in Table4, the ADSP-BF561 supports two different
power domains. The use of multiple power domains maximizes
flexibility, while maintaining compliance with industry stan-
dards and conventions. By isolating the internal logic of the
ADSP-BF561 into its own power domain, separate from the I/O,
Table 3.Power Settings
Table 3.Power Settings (Continued)
the processor can take advantage of Dynamic Power Manage-
ment, without affecting the I/O devices. There are no
sequencing requirements for the various power domains.
The power dissipated by a processor is largely a function of the
clock frequency of the processor and the square of the operating
voltage. For example, reducing the clock frequency by 25%
results in a 25% reduction in dynamic power dissipation, while
reducing the voltage by 25% reduces dynamic power dissipation
by more than 40%. Further, these power savings are additive, in
that if the clock frequency and supply voltage are both reduced,
the power savings can be dramatic.
The Dynamic Power Management feature of the ADSP-BF561
allows both the processor’s input voltage (VDDINT) and clock
frequency (fCCLK) to be dynamically controlled.
The savings in power dissipation can be modeled using the
Power Savings Factor and %Power Savings calculations.
The Power Savings Factor is calculated as:
where the variables in the equations are:
•fCCLKNOM is the nominal core clock frequency
•fCCLKRED is the reduced core clock frequency
•VDDINTNOM is the nominal internal supply voltage
•VDDINTRED is the reduced internal supply voltage
•TNOM is the duration running at fCCLKNOM
•TRED is the duration running at fCCLKRED
The percent power savings is calculated as:
VOLTAGE REGULATIONThe ADSP-BF561 processor provides an on-chip voltage regula-
tor that can generate processor core voltage levels 0.85V(–5% /
+10%) to 1.2V(–5% / +10%) [for commercial grade mini-PBGA
parts] or core voltage levels 0.9V(–7.5% / +12.5%) to
1.15V(–7.5% / +12.5%) [for industrial grade PBGA parts] from
an external 2.25V to 3.6V supply. Figure4 shows the typical
external components required to complete the power manage-
ment system. The regulator controls the internal logic voltage
Register (VR_CTL) in increments of 50mV. To reduce standby
power consumption, the internal voltage regulator can be pro-
grammed to remove power to the processor core while keeping
I/O power (VDDEXT) supplied. While in the hibernate state
VDDEXT can still be applied, eliminating the need for external
buffers. The voltage regulator can be activated from this power-
down state by asserting RESET, which will then initiate a boot
sequence. The regulator can also be disabled and bypassed at the
user’s discretion.
CLOCK SIGNALSThe ADSP-BF561 can be clocked by an external crystal, a sine
wave input, or a buffered, shaped clock derived from an external
clock oscillator.
If an external clock is used, it should be a TTL compatible signal
and must not be halted, changed, or operated below the speci-
fied frequency during normal operation. This signal is
connected to the processor CLKIN pin. When an external clock
is used, the XTAL pin must be left unconnected.
Alternatively, because the ADSP-BF561 includes an on-chip
oscillator circuit, an external crystal may be used. The crystal
should be connected across the CLKIN and XTAL pins, with
two capacitors connected as shown in Figure5.
Capacitor values are dependent on crystal type and should be
specified by the crystal manufacturer. A parallel-resonant, fun-
damental frequency, microprocessor grade crystal should be
used.
Table 4.ADSP-BF561 Power DomainsPower Savings Factor
fCCLKRED
fCCLKNOM---------------------VDDINTRED
VDDINTNOM--------------------------⎝⎠⎛⎞2×TRED
TNOM-------------⎝⎛×⎠⎞=
% Power Savings1Power Savings Factor–()100%×=
Figure 4.Voltage Regulator Circuit
Figure 5.External Crystal Connections
As shown in Figure6, the core clock (CCLK) and system
peripheral clock (SCLK) are derived from the input clock
(CLKIN) signal. An on-chip PLL is capable of multiplying the
CLKIN signal by a user programmable 1x to 63x multiplication
factor. The default multiplier is 10x, but it can be modified by a
software instruction sequence. On the fly frequency changes can
be effected by simply writing to the PLL_DIV register.
All on-chip peripherals are clocked by the system clock (SCLK).
The system clock frequency is programmable by means of the
SSEL3–0 bits of the PLL_DIV register. The values programmed
into the SSEL fields define a divide ratio between the PLL output
(VCO) and the system clock. SCLK divider values are 1 through
15. Table5 illustrates typical system clock ratios:
The maximum frequency of the system clock is fSCLK. Note that
the divisor ratio must be chosen to limit the system clock fre-
quency to its maximum of fSCLK. The SSEL value can be changed
dynamically without any PLL lock latencies by writing the
appropriate values to the PLL divisor register (PLL_DIV).
The core clock (CCLK) frequency can also be dynamically
changed by means of the CSEL[1–0] bits of the PLL_DIV regis-
ter. Supported CCLK divider ratios are 1, 2, 4, and 8, as shown
in Table6. This programmable core clock capability is useful for
fast core frequency modifications.
BOOTING MODESThe ADSP-BF561 has three mechanisms (listed in Table7) for
automatically loading internal L1 instruction memory or L2
after a reset. A fourth mode is provided to execute from external
memory, bypassing the boot sequence.
The BMODE pins of the Reset Configuration Register, sampled
during power-on resets and software initiated resets, implement
the following modes:Execute from 16-bit external memory –
Execution starts from address 0x2000 0000 with 16-bit
packing. The boot ROM is bypassed in this mode. All con-
figuration settings are set for the slowest device possible (3-
cycle hold time, 15-cycle R/W access times, 4-cycle setup).Boot from 8/16-bit external FLASH memory–
The 8/16-bit FLASH boot routine located in boot ROM
memory space is set up using Asynchronous Memory Bank
0. All configuration settings are set for the slowest device
possible (3-cycle hold time; 15-cycle R/W access times;
4-cycle setup).Boot from SPI serial EEPROM (16-bit addressable)–
The SPI uses the PF2 output pin to select a single SPI
EPROM device, submits a read command at address
0x0000, and begins clocking data into the beginning of L1
instruction memory. A 16-bit addressable SPI-compatible
EPROM must be used.
For each of the boot modes, a boot loading protocol is used to
transfer program and data blocks, from an external memory
device, to their specified memory locations. Multiple memory
Figure 6.Frequency Modification Methods
Table 5.Example System Clock Ratios
Table 6.Core Clock Ratios
Table 7.Booting Modes
loaded, Core A program execution commences from the start of
L1 instruction SRAM (0xFFA0 0000). Core B remains in a held-
off state until bit 5 of SICA_SYSCR is cleared. After that, Core B
will start execution at address 0xFF60 0000.
In addition, bit 4 of the Reset Configuration Register can be set
by application code to bypass the normal boot sequence during
a software reset. For this case, the processor jumps directly to
the beginning of L1 instruction memory.
INSTRUCTION SET DESCRIPTIONThe Blackfin processor family assembly language instruction set
employs an algebraic syntax that was designed for ease of coding
and readability. The instructions have been specifically tuned to
provide a flexible, densely encoded instruction set that compiles
to a very small final memory size. The instruction set also pro-
vides fully featured multifunction instructions that allow the
programmer to use many of the processor core resources in a
single instruction. Coupled with many features more often seen
on microcontrollers, this instruction set is very efficient when
compiling C and C++ source code. In addition, the architecture
supports both a user (algorithm/application code) and a super-
visor (O/S kernel, device drivers, debuggers, ISRs) mode of
operation—allowing multiple levels of access to core processor
resources.
The assembly language, which takes advantage of the proces-
sor’s unique architecture, offers the following advantages:Seamlessly integrated DSP/CPU features are optimized for
both 8-bit and 16-bit operations.A multi-issue load/store modified Harvard architecture,
which supports two 16-bit MAC or four 8-bit ALU plus
two load/store plus two pointer updates per cycle.All registers, I/O, and memory are mapped into a unified Gbyte memory space providing a simplified program-
ming model.Microcontroller features, such as arbitrary bit and bit-field
manipulation, insertion, and extraction; integer operations
on 8-, 16-, and 32-bit data types; and separate user and ker-
nel stack pointers.Code density enhancements, which include intermixing of
16- and 32-bit instructions (no mode switching, no code
segregation). Frequently used instructions are encoded as
16-bits.
DEVELOPMENT TOOLSThe ADSP-BF561 is supported with a complete set of
CROSSCORE®* software and hardware development tools,
including Analog Devices emulators and the VisualDSP++®†
development environment. The same emulator hardware that
supports other Analog Devices processors also fully emulates
the ADSP-BF561.
The VisualDSP++ project management environment lets pro-
grammers develop and debug an application. This environment
includes an easy to use assembler that is based on an algebraic
syntax, an archiver (librarian/library builder), a linker, a loader,
a cycle-accurate instruction-level simulator, a C/C++ compiler,
and a C/C++ runtime library that includes DSP and mathemati-
cal functions. A key point for these tools is C/C++ code
efficiency. The compiler has been developed for efficient trans-
lation of C/C++ code to Blackfin assembly. The Blackfin
processor has architectural features that improve the efficiency
of compiled C/C++code.
The VisualDSP++ debugger has a number of important fea-
tures. Data visualization is enhanced by a plotting package that
offers a significant level of flexibility. This graphical representa-
tion of user data enables the programmer to quickly determine
the performance of an algorithm. As algorithms grow in com-
plexity, this capability can have increasing significance on the
designer’s development schedule, increasing productivity. Sta-
tistical profiling enables the programmer to non-intrusively poll
the processor as it is running the program. This feature, unique
to VisualDSP++, enables the software developer to passively
gather important code execution metrics without interrupting
the real time characteristics of the program. Essentially, the
developer can identify bottlenecks in software quickly and effi-
ciently. By using the profiler, the programmer can focus on
those areas in the program that impact performance and take
corrective action.
Debugging both C/C++ and assembly programs with the Visu-
alDSP++ debugger, programmers can:View mixed C/C++ and assembly code (interleaved source
and object information)Insert breakpointsSet conditional breakpoints on registers, memory, and
stacksTrace instruction executionPerform linear or statistical profiling of program executionFill, dump, and graphically plot the contents of memoryPerform source level debugging
•Create custom debugger windows
The VisualDSP++ IDE lets programmers define and manage
software development. Its dialog boxes and property pages let
programmers configure and manage all development tools,
including Color Syntax Highlighting in the VisualDSP++ edi-
tor. These capabilities permit programmers to:Control how the development tools process inputs and
generate outputs.Maintain a one-to-one correspondence with the tool’s
command line switches.
The VisualDSP++ Kernel (VDK) incorporates scheduling and
resource management tailored specifically to address the mem-
ory and timing constraints of embedded, real time
programming. These capabilities enable engineers to develop
very beginning, when developing new application code. The
VDK features include Threads, Critical and Unscheduled
regions, Semaphores, Events, and Device flags. The VDK also
supports Priority based, Pre-emptive, Cooperative and Time-
Sliced scheduling approaches. In addition, the VDK was
designed to be scalable. If the application does not use a specific
feature, the support code for that feature is excluded from the
target system.
Because the VDK is a library, a developer can decide whether to
use it or not. The VDK is integrated into the VisualDSP++
development environment, but can also be used with standard
command line tools. When the VDK is used, the development
environment assists the developer with many error prone tasks
and assists in managing system resources, automating the gen-
eration of various VDK based objects, and visualizing the
system state, when debugging an application that uses the VDK.
VCSE is Analog Devices’ technology for creating, using, and
reusing software components (independent modules of sub-
stantial functionality) to quickly and reliably assemble software
applications. Components can be downloaded from the Web
and dropped into the application. Component archives can be
published from within VisualDSP++. VCSE supports compo-
nent implementation in C/C++ or assembly language.
The Expert Linker can be used to visually manipulate the place-
ment of code and data in the embedded system. Memory
utilization can be viewed in a color coded graphical form. Code
and data can be easily moved to different areas of the processor
or external memory with the drag of the mouse. Runtime stack
and heap usage can be examined. The Expert Linker is fully
compatible with existing Linker Definition File (LDF), allowing
the developer to move between the graphical and textual
environments.
Analog Devices’ emulators use the IEEE 1149.1 JTAG test access
port of the ADSP-BF561 to monitor and control the target
board processor during emulation. The emulator provides full-
speed emulation, allowing inspection and modification of mem-
ory, registers, and processor stacks. Non-intrusive in-circuit
emulation is assured by the use of the processor’s JTAG inter-
face—the emulator does not affect target system loading or
timing.
In addition to the software and hardware development tools
available from Analog Devices, third parties provide a wide
range of tools supporting the Blackfin processor family. Third
party software tools include DSP libraries, real time operating
systems, and block diagram design tools.
DESIGNING AN EMULATOR COMPATIBLE
PROCESSOR BOARD (TARGET)The Analog Devices family of emulators are tools that every sys-
tem developer needs to test and debug hardware and software
systems. Analog Devices has supplied an IEEE 1149.1 JTAG
Test Access Port (TAP) on the ADSP-BF561. The emulator uses
the TAP to access the internal features of the processor, allow-
ing the developer to load code, set breakpoints, observe
variables, observe memory, and examine registers. The proces-
sor must be halted to send data and commands, but once an
operation has been completed by the emulator, the processor is
set running at full speed with no impact on system timing.
To use these emulators, the target board must include a header
that connects the processor’s JTAG port to the emulator.
For details on target board design issues including mechanical
layout, single processor connections, multiprocessor scan
chains, signal buffering, signal termination, and emulator pod
logic, see EE-68: Analog Devices JTAG Emulation Technical Ref-
erence on the Analog Devices web site ()—use
site search on “EE-68.” This document is updated regularly to
keep pace withimprovements to emulator support.
ADDITIONAL INFORMATIONThis data sheet provides a general overview of the ADSP-BF561
architecture and functionality. For detailed information on the
Blackfin DSP family core architecture and instruction set, refer
to the ADSP-BF561 Hardware Reference and the Blackfin Family
Instruction Set Reference.
PIN DESCRIPTIONSADSP-BF561 pin definitions are listed in Table8. Unused
inputs should be tied or pulled to VDDEXT or GND. Output
drive currents for each driver type are shown in Figure22
through Figure29.
Table 8.Pin Descriptions
Table 8.Pin Descriptions (Continued)
Table 8.Pin Descriptions (Continued)
Total pins256
Table 8.Pin Descriptions (Continued)SPECIFICATIONSNote that component specifications are subject to change
without notice.
RECOMMENDED OPERATING CONDITIONS
ELECTRICAL CHARACTERISTICS
Table 9.The ADSP-BF561 is 3.3 V tolerant (always accepts up to 3.6 V maximum VIH), but voltage compliance (on outputs, VOH) depends on the input VDDEXT, because VOH
(maximum) approximately equals VDDEXT (maximum). This 3.3 V tolerance applies to bi-directional and input only pins.
Table 10.Applies to output and bidirectional pins.Applies to all input pins.Applies to all input pins except TCK, TDI, TMS, and TRST.Applies to TCK, TDI, TMS, and TRST.Applies to three-statable pins.Applies to all signal pins.Guaranteed, but not tested.
ABSOLUTE MAXIMUM RATINGS
ESD SENSITIVITYStresses greater than those listed above may cause permanent damage to the device. These
are stress ratings only. Functional operation of the device at these or any other conditions
greater than those indicated in the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect device
reliability.For proper SDRAM controller operation, the maximum load capacitance is 50 pF (at
3.3V) or 30 pF (at 2.5V) for ADDR25–2, DATA31–0, ABE3–0/SDQM3–0, CLKOUT,
SCKE, SA10, SRAS, SCAS, SWE, and SMS.
Table 11.
CAUTIONESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the ADSP-BF561 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precau-
tions are recommended to avoid performance degradation or loss of functionality.
TIMING SPECIFICATIONSTable12 and Table15 describe the timing requirements for the
ADSP-BF561 clocks. Take care in selecting MSEL, SSEL, and
CSEL ratios so as not to exceed the maximum core clock, system
clock and Voltage Controlled Oscillator (VCO) operating fre-
quencies, as described in For more information, see “Absolute
Maximum Ratings” on page 21. Table15 describes Phase
Locked Loop operating conditions.
Table 12.Core and System Clock Requirements—ADSP-BF561SKBCZ500
Table 13.Core and System Clock Requirements—ADSP-BF561SKBCZ600X
Table 14.Core and System Clock Requirements—ADSP-BF561SBB600
Table 15.Phase Locked Loop Operating Conditions
Clock and Reset TimingTable16 and Figure7 describe clock and reset operations. Per
Figure7, combinations of CLKIN and clock multipliers must
not select core/peripheral clocks in excess of 600/133 MHz.
Table 16.Clock and Reset Timing1Applies to bypass mode and non-bypass mode.Applies after power-up sequence is complete. At power-up, the processor’s internal phase locked loop requires no more than 2000 CLKIN cycles, while RESET is asserted,
assuming stable power supplies and CLKIN (not including startup time of external clock oscillator).The figure below shows a �2 ratio between tCKIN and tSCLK, but the ratio has many programmable options. For more information, see the System Design chapter of the ADSP-
BF561 Hardware Reference.tSCLK must always also be larger than tCCLK.
Figure 7.Clock and Reset Timing
Asynchronous Memory Read Cycle Timing
Table 17.Asynchronous Memory Read Cycle Timing Output pins include AMS3–0, ABE3–0, ADDR25–2, AOE, ARE.
Figure 8.Asynchronous Memory Read Cycle Timing
Asynchronous Memory Write Cycle Timing
Table 18.Asynchronous Memory Write Cycle Timing Output pins include AMS3–0, ABE3–0, ADDR25–2, DATA31–0, AOE, AWE.
Figure 9.Asynchronous Memory Write Cycle Timing
SDRAM Interface Timing
Table 19.SDRAM Interface TimingCommand pins include: SRAS, SCAS, SWE, SDQM, SMS3–0, SA10, SCKE.
Figure 10.SDRAM Interface Timing
