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ADSP-BF539
Blackfin Processor for Automotive Navigation, Entertainment and Audio Systems
ANALOG
DEVICES
Blackfin
Embedded Processor
ADSP-BF539/ADSP-BF539F
FEATURES
Up to 533 MHz high performance Blackfin processor
Two 1 6-bit MACs, two 40-bit ALUs, four 8-bit video ALUs,
40-bit shifter
RlSC-like register and instruction model for ease of
programming and compiler friendly support
Advanced debug, trace, and performance monitoring
Wide range of operating voltages; see Operating Conditions
on Page 26
Qualified for automotive applications
Programmable on-chip voltage regulator
316-ball Pb-free CSP_BGA package
MEMORY
148K bytes of on-chip memory
16K bytes of instruction SRAM/cache
64K bytes of instruction SRAM
32K bytes of data SRAM
32K bytes of data SRAM/cache
4K bytes of scratchpad SRAM
Optional 8M bit parallel flash with boot option
Memory management unit providing memory protection
External memory controller with glueless support
for SDRAM, SRAM, flash, and ROM
Flexible memory booting options from SPI and external
memory
PERIPHERALS
Parallel peripheral interface (PPI), supporting lTU-R 656
video data formats
4 dual-channel, full-duplex synchronous serial ports,
supporting 16 stereo Ps channels
2 DMA controllers supporting 26 peripheral DMAs
4 memory-to-memory DMAs
Controller area network (CAN) 2.0B controller
Media transceiver (MXVR) for connection
to a MOST network
3 SPl-compatible ports
Three 32-bit timer/counters with PWM support
3 UARTs with support for IrDA
2 TWI controllers compatible with Pc industry standard
Up to 38 generaI-purpose l/O pins (GPIO)
Up to 16 general-purpose flag pins (GPF)
ReaI-time clock, watchdog timer, and 32-bit core timer
On-chip PLL capable of frequency multiplication
Debug/JTAG interface
VOLTAGE REGULATOR JTAG TEST AND EMULATION
A A ii
PERIPHERAL ACCESS BUS U
, 7 , r m
INTERRUPT w
x ' u WATCHDOG
lraariitrs CONTROLLER g 1:» TIMER
4=tr GPIO CAN 2.0B t'
PORT DMA CORE l m H E RTC
C BUS 2 E
<=>| MXVR ' u:
i 4 E rsrnlCCz')
DMA L1 INSTRUCTION L1 DATA DMA C=D
GPlO <=>| SPI” CONTROLLER1 MEMORY MEMORY CONTROLLER o o GPIO
4=tr PORT e A g TIMER0-2 c=D PORT 4=ty
D m n: F
UAnT1-2 3 DMA
, DMA CORE DMA ||— EXTERNAL 3
tl BUS1 EXTERNAL DMA CORE BUS o aus 0 'is,'
GPO SPORT2-3 8 BUS1 <
4xty PORT T Q g
E E EXTERNAL PORT n
FLASH, SDRAM CONTROL
8M BIT PARALLEL FLASH
(See Table 1)
BOOT ROM
Figure 1. FunctionalB/ock Diagram
Blacldin and the Blackfm logo are registered trademarks of Analog Devices, Inc.
Rev. F Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.0. Box 9106, Norwood, MA 02062-9106 U.S.A.
Tel: 781.329.4700 ©2013 Analog Devices, Inc. All rights reserved.
Technical Support
ADSP-BF539/ADSP-BF539F
TABLE OF CONTENTS
Features w................................................................ 1
Memory w............................................................... 1
Peripherals _............................................................ 1
General Description ................................................. 3
Low Power Architecture ......................................... 3
System Integration B............................................... 3
ADSP-BF539/ADSP-BF539F Processor Peripherals ....... 3
Blackfin Processor Core .......................................... 4
Memory Architecture B........................................... 5
DMA Controllers B................................................. 8
Real-Time Clock ................................................... 9
Watchdog Timer .................................................. 9
Timers ............................................................... 9
Serial Ports (SPORTS) .......................................... 10
Serial Peripheral Interface (SP1) Ports ...................... 10
2-Wire Interface _................................................ 10
UART Ports w..................................................... 10
Programmable I/O Pins ........................................ 11
Parallel Peripheral Interface ................................... 12
Controller Area Network (CAN) Interface ................ 12
Media Transceiver MAC layer (MXVR) ................... 13
Dynamic Power Management ................................ 13
Voltage Regulation .............................................. 15
Clock Signals T.................................................... 15
REVISION HISTORY
10/13-Rev. E to Rev. F
Updated Development Tools .................................... 17
Added notes to Table 32 in
Serial Ports-Enable and Three-State .......................... 43
Added Timer Clock Timing ...................................... 48
Revised Timer Cycle Timing ..................................... 48
To view product/process change notifications (PCNs) related to
this data sheet revision, please visit the processor's product page
on the website and use the View PCN link.
Rev. F l Page 2 of 60
Booting Modes ................................................... 16
Instruction Set Description .................................... 17
Development Tools .............................................. 17
Example Connections and Layout Considerations ....... 18
MXVR Board Layout Guidelines ............................. 18
Voltage Regulator Layout Guidelines ....................... 19
Additional Information _....................................... 20
Related Signal Chains ........................................... 20
Pin Descriptions B................................................... 21
Specifications B....................................................... 26
Operating Conditions ........................................... 26
Electrical Characteristics ....................................... 27
Absolute Maximum Ratings ................................... 30
ESD Sensitivity m.................................................. 30
Package Information ............................................ 30
Timing Specifications _.......................................... 31
Output Drive Currents ......................................... 50
Test Conditions _................................................. 52
Thermal Characteristics ........................................ 55
316-Ball CSP_BGA Ball Assignment ........................... 56
Outline Dimensions ................................................ 59
Surface-Mount Design .......................................... 59
Ordering Guide p.................................................... 60
October 2013
ADSP-BF539/ADSP-BF539F
GENERAL DESCRIPTION
The ADSP-BF539/ADSP-BF539F processors are members of
the Blackfino family of products, incorporating the Analog
Devices, Inc./Intel Micro Signal Architecture (MSA). Blackfin
processors combine a dual-MAC, state-of-the-art signal pro-
cessing engine, the advantages of a clean, orthogonal RISC-like
microprocessor instruction set, and single-instruction, multi-
ple-data (SIMD) multimedia capabilities into a single
instruction set architecture.
The ADSP-BF539/ADSP-BF539F processors are completely
code compatible with other Blacldin processors, differing only
with respect to performance, peripherals, and on-chip memory.
These features are shown in Table 1.
By integrating a rich set of industry-leading system peripherals
and memory, Blacldin processors are the platform of choice for
next generation applications that require RISC-like program-
mability, multimedia support, and leading edge signal
processing in one integrated package.
Table 1. Processor Features
Feature ADSP-BF539 ADSP-BF539F8
SPORTS 4 4
UARTs 3 3
SPI 3 3
TWI 2 2
CAN 1 1
MXVR 1 1
PPI 1 1
Internal 8M bit - 1
Parallel Flash
Instruction 16K bytes 16K bytes
SRAM/Cache
Instruction SRAM 64K bytes 64K bytes
Data SRAM/Cache 32K bytes 32K bytes
Data SRAM 32K bytes 32K bytes
Scratchpad 4K bytes 4K bytes
Maximum 533 MHz 533 MHz
Frequency 1066 MMACS 1066 MMACS
Package Option BC-316 BC-316
LOW POWER ARCHITECTURE
Blackfin processors provide world class power management and
performance. Blackfin processors are designed in a low power
and low voltage design methodology and feature dynamic
power management, the ability to vary both the voltage and fre-
quency of operation to significantly lower overall power
consumption. Varying the voltage and frequency can result in a
substantial reduction in power consumption, compared with
simply varying the frequency of operation. This translates into
longer battery life and lower heat dissipation.
Rev. F l Page 3 of 60
SYSTEM INTEGRATION
The ADSP-BF539/ADSP-BF539F processors are highly inte-
grated system-on-a-chip solutions for the next generation of
industrial and automotive applications including audio and
video signal processing. By combining advanced memory con-
figurations, such as on-chip flash memory, with industry-
standard interfaces with a high performance signal processing
core, users can develop cost-effective solutions quickly without
the need for costly external components. The system peripherals
include a MOST Network Media Transceiver (MXVR), three
UART ports, three SPI ports, four serial ports (SPORT), one
CAN interface, two 2-wire interfaces (TWI), four general-pur-
pose timers (three with PWM capability), a real-tinte clock, a
watchdog timer, a parallel peripheral interface, general-purpose
I/O, and general-purpose flag pins.
ADSP-BF539/ADSP-BF539F PROCESSOR
PERIPHERALS
The ADSP-BF539/ADSP-BIE39F processors contain a rich set
of peripherals connected to the core via several high bandwidth
buses, providing flexibility in system configuration as well as
excellent overall system performance (see Figure 1 on Page 1).
The general-purpose peripherals include functions such as
UART, timers with PWM (pulse-width modulation) and pulse
measurement capability, general-purpose flag I/O pins, a real-
time clock, and a watchdog timer. This set of functions satisfies
a wide variety of typical system support needs and is augmented
by the system expansion capabilities of the device. In addition to
these general-purpose peripherals, the processors contain high
speed serial and parallel ports for interfacing to a variety of
audio, video, and modem codec functions. An MXVR trans-
ceiver transmits and receives audio and video data and control
information on a MOST automotive multimedia network. A
CAN 2.0B controller is provided for automotive control net-
works. An interrupt controller manages interrupts from the on-
chip peripherals or external sources. And power management
control functions tailor the performance and power characterise
tics of the processor and system to many application scenarios.
All of the peripherals, GPIO, CAN, TWI, real-time clock, and
timers, are supported by a flexible DMA structure. There are
also four separate memory DMA channels dedicated to data
transfers between the processor's various memory spaces,
including external SDRAM and asynchronous memory. Multi-
ple on-chip buses running at up to 133 MHz provide enough
bandwidth to keep the processor core running along with activ-
ity on all of the on-chip and external peripherals.
The ADSP-BF539/ADSP-BF539F processors include an on-chip
voltage regulator in support of the processor's dynamic power
management capability. The voltage regulator provides a range
of core voltage levels from Vonm. The voltage regulator can be
bypassed at the user's discretion.
October 2013
ADSP-BF539/ADSP-BF539F
BLACKFIN PROCESSOR CORE
As shown in Figure 2, the Blackfin processor core contains two
16-bit multipliers, two 40-bit accumulators, two 40-bit ALUs,
four video ALUs, and a 40-bit shifter. The computation units
process 8-bit, 16-bit, or 32-bit data from the register file.
The compute register file contains eight 32-bit registers. When
performing compute operations on 16-bit operand data, the
register file operates as 16 independent 16-bit registers. All
operands for compute operations come from the multiported
register file and instruction constant fields.
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Figure 2. Blackfin Processor Core
Each MAC can perform a 16-bit by 16-bit multiply in each
cycle, accumulating the results into the 40-bit accumulators.
Signed and unsigned formats, rounding, and saturation are
supported.
The ALUs perform a traditional set of arithmetic and logical
operations on 16-bit or 32-bit data. In addition, many special
instructions are included to accelerate various signal processing
tasks. These include bit operations such as field extract and pop-
ulation count, modulo 232 multiply, divide primitives, saturation
and rounding, and sign/exponent detection. The set of video
instructions include byte alignment and packing operations
I6-bit and 8-bit adds with clipping, 8-bit average operations,
and 8-bit subtract/absolute value/accumulate (SAA) opera-
tions. Also provided are the compare/select and vector search
instructions.
Rev. F l Page 4 of 60
For certain instructions, two 16-bit ALU operations can be per-
formed simultaneously on register pairs (a I6-bit high half and
16-bit low half of a compute register). By also using the second
ALU, quad 16-bit operations are possible.
The 40-bit shifter can perform shifts and rotates and is used to
support normalization, field extract, and field deposit
instructions.
The program sequencer controls the flow of instruction execu-
tion, including instruction alignment and decoding. For
program flow control, the sequencer supports PC relative and
indirect conditional jumps (with static branch prediction), and
subroutine calls. Hardware is provided to support zero over-
head looping. The architecture is fully interlocked, meaning that
the programmer need not manage the pipeline when executing
instructions with data dependencies.
October 2013
