ADSP-BF532SBBZ400 ,400 MHz High Performance Blackfin ProcessorSpecifications subject to change without notice. No license is granted by implication www.analog.co ..
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ADSP-BF532SBST400 ,400 MHz High Performance Blackfin ProcessorSpecifications ....... 21System Integration ... 3 Clock and Reset Timing . 22ADSP-BF531/2/3 Process ..
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ADSP-BF531-ADSP-BF531SBBC400-ADSP-BF531SBBZ400-ADSP-BF531SBST400-ADSP-BF531SBSTZ400-ADSP-BF531-SBSTZ400-ADSP-BF532SBBC400-ADSP-BF532SBBZ400-ADSP-BF532SBST400-ADSP-BF533-ADSP-BF533SBBC500-ADSP-BF533SBBZ500-ADSP-BF533SKBC600
400 MHz Low Cost Blackfin Processor
Blackfin and the Blackfin logo are registered trademarks of Analog Devices, Inc.
Rev. 0
FEATURES
Up to 600MHz high performance Blackfin processor
Two 16-bit MACs, two 40-bit ALUs, four 8-bit video ALUs,
40-bit Shifter
RISC-like register and instruction model for ease of pro-
gramming and compiler-friendly support
Advanced debug, trace, and performance monitoring
0.8 V to 1.2 V core VDD with on-chip voltage regulation
3.3V and 2.5 V tolerant I/O
160-ball mini-BGA, 169-ball lead free PBGA, and 176-lead
LQFP packages
MEMORY
Up to 148Kbytes of on-chip memory:
16Kbytes of instruction SRAM/Cache
64Kbytes of instruction SRAM
32Kbytes of data SRAM/Cache
32Kbytes of data SRAMbytes of scratchpad SRAM
Two dual-channel memory DMA controllers
Memory Management Unit providing memory protection
External Memory Controller with glueless support for
SDRAM, SRAM, FLASH, and ROM
Flexible memory booting options from SPI and external
memory
PERIPHERALS
Parallel Peripheral Interface (PPI)/GPIO, supporting
ITU-R 656 video data formats
Two dual-channel, full duplex synchronous serial ports, sup-
porting eight stereo I2S channels
12-channel DMA controller
SPI compatible port
Three Timer/Counters with PWM support
UART with support for IrDA®
Event Handler
Real-Time Clock
Watchdog Timer
Debug/JTAG interface
On-chip PLL capable of 1x to 63x frequency multiplication
Core TimerFigure 1.Functional Block Diagram
TABLE OF CONTENTSGeneral Description ................................................. 3
Portable Low Power Architecture ............................. 3
System Integration ................................................ 3
ADSP-BF531/2/3 Processor Peripherals ..................... 3
Blackfin Processor Core .......................................... 3
Memory Architecture ............................................ 4
DMA Controllers .................................................. 8
Real-Time Clock ................................................... 8
Watchdog Timer .................................................. 9
Timers ............................................................... 9
Serial Ports (SPORTs) ............................................ 9
Serial Peripheral Interface (SPI) Port ......................... 9
UART Port ........................................................ 10
Programmable Flags (PFx) .................................... 10
Parallel Peripheral Interface ................................... 10
Dynamic Power Management ................................ 11
Voltage Regulation .............................................. 12
Clock Signals ..................................................... 12
Booting Modes ................................................... 13
Instruction Set Description ................................... 14
Development Tools ............................................. 14
Designing an Emulator Compatible Processor Board ... 15
Pin Descriptions .................................................... 16
Specifications ........................................................ 19
Recommended Operating Conditions ...................... 19
Electrical Characteristics ....................................... 19
Absolute Maximum Ratings .................................. 20
ESD Sensitivity ................................................... 20
Timing Specifications ........................................... 21
Clock and Reset Timing ..................................... 22
Asynchronous Memory Read Cycle Timing ............ 23
Asynchronous Memory Write Cycle Timing ........... 24
SDRAM Interface Timing .................................. 25
External Port Bus Request and Grant Cycle Timing .. 26
Parallel Peripheral Interface Timing ...................... 27
Serial Ports ..................................................... 28
Serial Peripheral Interface (SPI) Port
—Master Timing ........................................... 33
Serial Peripheral Interface (SPI) Port
—Slave Timing ............................................. 34
Universal Asynchronous Receiver-Transmitter
(UART) Port—Receive and Transmit Timing ...... 35
Programmable Flags Cycle Timing ....................... 36
Timer Cycle Timing .......................................... 37
JTAG Test And Emulation Port Timing ................. 38
Output Drive Currents ......................................... 39
Power Dissipation ............................................... 41
Test Conditions .................................................. 42
Environmental Conditions .................................... 45
160-Lead BGA Pinout ............................................. 46
169-Ball PBGA Pinout ............................................. 49
176-Lead LQFP Pinout ............................................ 51
Outline Dimensions ................................................ 53
Ordering Guide ..................................................... 56
REVISION HISTORYRevision 0: Initial Version
GENERAL DESCRIPTIONThe ADSP-BF531/2/3 processors are members of the Blackfin
family of products, incorporating the Analog Devices/Intel
Micro Signal Architecture (MSA). Blackfin processors combine
a dual-MAC state-of-the-art signal processing engine, the
advantages of a clean, orthogonal RISC-like microprocessor
instruction set, and single-instruction, multiple-data (SIMD)
multimedia capabilities into a single instruction-set
architecture.
The ADSP-BF531/2/3 processors are completely code and pin
compatible, differing only with respect to their performance and
on-chip memory. Specific performance and memory configura-
tions are shown in Table1.
By integrating a rich set of industry-leading system peripherals
and memory, Blackfin processors are the platform of choice for
next-generation applications that require RISC-like program-
mability, multimedia support, and leading-edge signal
processing in one integrated package.
PORTABLE LOW POWER ARCHITECTUREBlackfin processors provide world-class power management
and performance. Blackfin processors are designed in a low
power and low voltage design methodology and feature
Dynamic Power Management, the ability to vary both the volt-
age and frequency of operation to significantly lower overall
power consumption. Varying the voltage and frequency can
result in a substantial reduction in power consumption, com-
pared with just varying the frequency of operation. This
translates into longer battery life for portable appliances.
SYSTEM INTEGRATIONThe ADSP-BF531/2/3 processors are highly integrated system-
on-a-chip solutions for the next generation of digital communi-
cation and consumer multimedia applications. By combining
industry-standard interfaces with a high performance signal
processing core, users can develop cost-effective solutions
quickly without the need for costly external components. The
system peripherals include a UART port, an SPI port, two serial
ports (SPORTs), four general-purpose timers (three with PWM
ADSP-BF531/2/3 PROCESSOR PERIPHERALSThe ADSP-BF531/2/3 processor contains a rich set of peripher-
als connected to the core via several high bandwidth buses,
providing flexibility in system configuration as well as excellent
overall system performance (see the functional block diagram in
Figure1 on Page1). The general-purpose peripherals include
functions such as UART, Timers with PWM (Pulse-Width
Modulation) and pulse measurement capability, general-pur-
pose flag I/O pins, a Real-Time Clock, and a Watchdog Timer.
This set of functions satisfies a wide variety of typical system
support needs and is augmented by the system expansion capa-
bilities of the part. In addition to these general-purpose
peripherals, the ADSP-BF531/2/3 processor contains high speed
serial and parallel ports for interfacing to a variety of audio,
video, and modem codec functions; an interrupt controller for
flexible management of interrupts from the on-chip peripherals
or external sources; and power management control functions
to tailor the performance and power characteristics of the pro-
cessor and system to many application scenarios.
All of the peripherals, except for general-purpose I/O, Real-
Time Clock, and timers, are supported by a flexible DMA struc-
ture. There is also a separate memory DMA channel dedicated
to data transfers between the processor's various memory
spaces, including external SDRAM and asynchronous memory.
Multiple on-chip buses running at up to 133MHz provide
enough bandwidth to keep the processor core running along
with activity on all of the on-chip and external peripherals.
The ADSP-BF531/2/3 processor includes an on-chip voltage
regulator in support of the ADSP-BF531/2/3 processor
Dynamic Power Management capability. The voltage regulator
provides a range of core voltage levels from a single 2.25V to
3.6V input. The voltage regulator can be bypassed at the user's
discretion.
BLACKFIN PROCESSOR COREAs shown in Figure2 on Page5, the Blackfin processor core
contains two 16-bit multipliers, two 40-bit accumulators, two
40-bit ALUs, four video ALUs, and a 40-bit shifter. The compu-
tation units process 8-bit, 16-bit, or 32-bit data from the
registerfile.
The compute register file contains eight 32-bit registers. When
performing compute operations on 16-bit operand data, the
register file operates as 16 independent 16-bit registers. All
operands for compute operations come from the multiported
register file and instruction constant fields.
Each MAC can perform a 16-bit by 16-bit multiply in each
cycle, accumulating the results into the 40-bit accumulators.
Signed and unsigned formats, rounding, and saturation are
supported.
The ALUs perform a traditional set of arithmetic and logical
operations on 16-bit or 32-bit data. In addition, many special
instructions are included to accelerate various signal processing
Table 1.Processor Comparison
saturation and rounding, and sign/exponent detection. The set
of video instructions includes byte alignment and packing oper-
ations, 16-bit and 8-bit adds with clipping, 8-bit average
operations, and 8-bit subtract/absolute value/accumulate (SAA)
operations. Also provided are the compare/select and vector
search instructions.
For certain instructions, two 16-bit ALU operations can be per-
formed simultaneously on register pairs (a 16-bit high half and
16-bit low half of a compute register). By also using the second
ALU, quad 16-bit operations are possible.
The 40-bit shifter can perform shifts and rotates and is used to
support normalization, field extract, and field deposit
instructions.
The program sequencer controls the flow of instruction execu-
tion, including instruction alignment and decoding. For
program flow control, the sequencer supports PC relative and
indirect conditional jumps (with static branch prediction), and
subroutine calls. Hardware is provided to support zero-over-
head looping. The architecture is fully interlocked, meaning that
the programmer need not manage the pipeline when executing
instructions with data dependencies.
The address arithmetic unit provides two addresses for simulta-
neous dual fetches from memory. It contains a multiported
register file consisting of four sets of 32-bit Index, Modify,
Length, and Base registers (for circular buffering), and eight
additional 32-bit pointer registers (for C-style indexed stack
manipulation).
Blackfin processors support a modified Harvard architecture in
combination with a hierarchical memory structure. Level 1 (L1)
memories are those that typically operate at the full processor
speed with little or no latency. At the L1 level, the instruction
memory holds instructions only. The two data memories hold
data, and a dedicated scratchpad data memory stores stack and
local variable information.
In addition, multiple L1 memory blocks are provided, offering a
configurable mix of SRAM and cache. The Memory Manage-
ment Unit (MMU) provides memory protection for individual
tasks that may be operating on the core and can protect system
registers from unintended access.
The architecture provides three modes of operation: User mode,
Supervisor mode, and Emulation mode. User mode has
restricted access to certain system resources, thus providing a
protected software environment, while Supervisor mode has
unrestricted access to the system and core resources.
The Blackfin processor instruction set has been optimized so
that 16-bit opcodes represent the most frequently used instruc-
tions, resulting in excellent compiled code density. Complex
DSP instructions are encoded into 32-bit opcodes, representing
fully featured multifunction instructions. Blackfin processors
support a limited multi-issue capability, where a 32-bit instruc-
tion can be issued in parallel with two 16-bit instructions,
allowing the programmer to use many of the core resources in a
single instruction cycle.
The Blackfin processor assembly language uses an algebraic syn-
tax for ease of coding and readability. The architecture has been
optimized for use in conjunction with the C/C++compiler,
resulting in fast and efficient software implementations.
MEMORY ARCHITECTUREThe ADSP-BF531/2/3 processor views memory as a single uni-
fied 4Gbyte address space, using 32-bit addresses. All resources,
including internal memory, external memory, and I/O control
registers, occupy separate sections of this common address
space. The memory portions of this address space are arranged
in a hierarchical structure to provide a good cost/performance
balance of some very fast, low latency on-chip memory as cache
or SRAM, and larger, lower cost and performance off-chip
memory systems. See Figure3 on Page5, Figure4 on Page5,
and Figure5 on Page6.
The L1 memory system is the primary highest performance
memory available to the Blackfin processor. The off-chip mem-
ory system, accessed through the External Bus Interface Unit
(EBIU), provides expansion with SDRAM, flash memory, and
SRAM, optionally accessing up to 132Mbytes of physical
memory.
The memory DMA controller provides high bandwidth data-
movement capability. It can perform block transfers of code or
data between the internal memory and the external memory
spaces.
Internal (On-Chip) MemoryThe ADSP-BF531/2/3 processor has three blocks of on-chip
memory providing high bandwidth access to the core.
The first is the L1 instruction memory, consisting of up to
80Kbytes SRAM, of which 16Kbytes can be configured as a
four-way set-associative cache. This memory is accessed at full
processor speed.
The second on-chip memory block is the L1 data memory, con-
sisting of up to two banks of up to 32Kbytes each. Each memory
bank is configurable, offering both cache and SRAM functional-
ity. This memory block is accessed at full processor speed.
The third memory block is a 4Kbyte scratchpad SRAM which
runs at the same speed as the L1 memories, but is only accessible
as data SRAM and cannot be configured as cache memory.
External (Off-Chip) MemoryThe External Bus interface can be used with both asynchronous
devices such as SRAM, FLASH, EEPROM, ROM, and I/O
devices, and synchronous devices such as SDRAMs. The bus
width is always 16 bits. A1 is the least significant address of a
16-bit word. 8-bit peripherals should be addressed as if they
were 16-bit devices, where only the lower 8 bits of data should
be used.
The PC133-compliant SDRAM controller can be programmed
to interface to up to 128Mbytes of SDRAM. The SDRAM con-
troller allows one row to be open for each internal SDRAM
bank, for up to four internal SDRAM banks, improving overall
system performance.
Figure 2.Blackfin Processor Core
The asynchronous memory controller can be programmed to
control up to four banks of devices with very flexible timing
parameters for a wide variety of devices. Each bank occupies a byte segment regardless of the size of the devices used, so
that these banks will only be contiguous if each is fully popu-
lated with 1Mbyte of memory.
I/O Memory SpaceBlackfin processors do not define a separate I/O space. All
resources are mapped through the flat 32-bit address space.
On-chip I/O devices have their control registers mapped into
memory-mapped registers (MMRs) at addresses near the top of
the 4Gbyte address space. These are separated into two smaller
blocks, one of which contains the control MMRs for all core
functions, and the other of which contains the registers needed
for setup and control of the on-chip peripherals outside of the
core. The MMRs are accessible only in supervisor mode and
appear as reserved space to on-chip peripherals.
BootingThe ADSP-BF531/2/3 processor contains a small boot kernel,
which configures the appropriate peripheral for booting. If the
ADSP-BF531/2/3 processor is configured to boot from boot
ROM memory space, the processor starts executing from the
on-chip boot ROM. For more information, see Booting Modes
on Page13.
Event HandlingThe event controller on the ADSP-BF531/2/3 processor handles
all asynchronous and synchronous events to the processor. The
ADSP-BF531/2/3 processor provides event handling that sup-
ports both nesting and prioritization. Nesting allows multiple
event service routines to be active simultaneously. Prioritization
ensures that servicing of a higher priority event takes prece-
dence over servicing of a lower priority event. The controller
provides support for five different types of events: Emulation – An emulation event causes the processor to
enter emulation mode, allowing command and control of
the processor via the JTAG interface.Reset – This event resets the processor.Non-Maskable Interrupt (NMI) – The NMI event can be
generated by the software watchdog timer or by the NMI
input signal to the processor. The NMI event is frequently
used as a power-down indicator to initiate an orderly shut-
down of the system.Exceptions – Events that occur synchronously to program
flow (i.e., the exception will be taken before the instruction
is allowed to complete). Conditions such as data alignment
violations and undefined instructions cause exceptions.Interrupts – Events that occur asynchronously to program
flow. They are caused by input pins, timers, and other
peripherals, as well as by an explicit software instruction.
Each event type has an associated register to hold the return
address and an associated return-from-event instruction. When
an event is triggered, the state of the processor is saved on the
supervisor stack.
The ADSP-BF531/2/3 processor Event Controller consists of
two stages, the Core Event Controller (CEC) and the System
Interrupt Controller (SIC). The Core Event Controller works
with the System Interrupt Controller to prioritize and control all
system events. Conceptually, interrupts from the peripherals
enter into the SIC, and are then routed directly into the general-
purpose interrupts of the CEC.
Core Event Controller (CEC)The CEC supports nine general-purpose interrupts (IVG15–7),
in addition to the dedicated interrupt and exception events. Of
these general-purpose interrupts, the two lowest-priority inter-
rupts (IVG15–14) are recommended to be reserved for software
interrupt handlers, leaving seven prioritized interrupt inputs to
support the peripherals of the ADSP-BF531/2/3 processor.
Table2 describes the inputs to the CEC, identifies their names
in the Event Vector Table (EVT), and lists their priorities.
System Interrupt Controller (SIC)The System Interrupt Controller provides the mapping and
routing of events from the many peripheral interrupt sources to
the prioritized general-purpose interrupt inputs of the CEC.
Although the ADSP-BF531/2/3 processor provides a default
mapping, the user can alter the mappings and priorities of
Figure 5.ADSP-BF531 Internal/External Memory Map
interrupt events by writing the appropriate values into the Inter-
rupt Assignment Registers (IAR). Table3 describes the inputs
into the SIC and the default mappings into the CEC.
Event ControlThe ADSP-BF531/2/3 processor provides the user with a very
flexible mechanism to control the processing of events. In the
CEC, three registers are used to coordinate and control events.
Each register is 16 bits wide:CEC Interrupt Latch Register (ILAT) – The ILAT register
indicates when events have been latched. The appropriate
bit is set when the processor has latched the event and
cleared when the event has been accepted into the system.
This register is updated automatically by the controller, but
it may be written only when its corresponding IMASK bit
is cleared.CEC Interrupt Mask Register (IMASK) – The IMASK reg-
ister controls the masking and unmasking of individual
events. When a bit is set in the IMASK register, that event is
unmasked and will be processed by the CEC when asserted.
A cleared bit in the IMASK register masks the event, pre-
venting the processor from servicing the event even though
the event may be latched in the ILAT register. This register
may be read or written while in supervisor mode. (Note
that general-purpose interrupts can be globally enabled and
disabled with the STI and CLI instructions, respectively.)CEC Interrupt Pending Register (IPEND) – The IPEND
register keeps track of all nested events. A set bit in the
IPEND register indicates the event is currently active or
nested at some level. This register is updated automatically
by the controller but may be read while in supervisor mode.
The SIC allows further control of event processing by providing
three 32-bit interrupt control and status registers. Each register
contains a bit corresponding to each of the peripheral interrupt
events shown in Table3 on Page7.SIC Interrupt Mask Register (SIC_IMASK)– This register
controls the masking and unmasking of each peripheral
interrupt event. When a bit is set in the register, that
peripheral event is unmasked and will be processed by the
system when asserted. A cleared bit in the register masks
the peripheral event, preventing the processor from servic-
ing the event. SIC Interrupt Status Register (SIC_ISR) – As multiple
peripherals can be mapped to a single event, this register
allows the software to determine which peripheral event
source triggered the interrupt. A set bit indicates the
peripheral is asserting the interrupt, and a cleared bit indi-
cates the peripheral is not asserting the event.SIC Interrupt Wakeup Enable Register (SIC_IWR) – By
enabling the corresponding bit in this register, a peripheral
can be configured to wake up the processor, should the
core be idled when the event is generated. (For more infor-
Table 2.Core Event Controller (CEC)
Table 3.System Interrupt Controller (SIC)
Because multiple interrupt sources can map to a single general-
purpose interrupt, multiple pulse assertions can occur simulta-
neously, before or during interrupt processing for an interrupt
event already detected on this interrupt input. The IPEND reg-
ister contents are monitored by the SIC as the interrupt
acknowledgement.
The appropriate ILAT register bit is set when an interrupt rising
edge is detected (detection requires two core clock cycles). The
bit is cleared when the respective IPEND register bit is set. The
IPEND bit indicates that the event has entered into the proces-
sor pipeline. At this point the CEC will recognize and queue the
next rising edge event on the corresponding event input. The
minimum latency from the rising edge transition of the general-
purpose interrupt to the IPEND output asserted is three core
clock cycles; however, the latency can be much higher, depend-
ing on the activity within and the state of the processor.
DMA CONTROLLERSThe ADSP-BF531/2/3 processor has multiple, independent
DMA controllers that support automated data transfers with
minimal overhead for the processor core. DMA transfers can
occur between the ADSP-BF531/2/3 processor's internal memo-
ries and any of its DMA-capable peripherals. Additionally,
DMA transfers can be accomplished between any of the DMA-
capable peripherals and external devices connected to the exter-
nal memory interfaces, including the SDRAM controller and
the asynchronous memory controller. DMA-capable peripher-
als include the SPORTs, SPI port, UART, and PPI. Each
individual DMA-capable peripheral has at least one dedicated
DMA channel.
The ADSP-BF531/2/3 processor DMA controller supports both
1-dimensional (1D) and 2-dimensional (2D) DMA transfers.
DMA transfer initialization can be implemented from registers
or from sets of parameters called descriptor blocks.
The 2D DMA capability supports arbitrary row and column
sizes up to 64K elements by 64K elements, and arbitrary row
and column step sizes up to ±32K elements. Furthermore, the
column step size can be less than the row step size, allowing
implementation of interleaved data streams. This feature is
especially useful in video applications where data can be
de-interleaved on the fly.
Examples of DMA types supported by the ADSP-BF531/2/3
processor DMA controller include:A single, linear buffer that stops upon completionA circular, auto-refreshing buffer that interrupts on each
full or fractionally full buffer1-D or 2-D DMA using a linked list of descriptors2-D DMA using an array of descriptors, specifying only the
base DMA address within a common page
In addition to the dedicated peripheral DMA channels, there are
two memory DMA channels provided for transfers between the
various memories of the ADSP-BF531/2/3 processor system.
This enables transfers of blocks of data between any of the
memories—including external SDRAM, ROM, SRAM, and
DMA transfers can be controlled by a very flexible descriptor
based methodology or by a standard register based autobuffer
mechanism.
REAL-TIME CLOCKThe ADSP-BF531/2/3 processor Real-Time Clock (RTC) pro-
vides a robust set of digital watch features, including current
time, stopwatch, and alarm. The RTC is clocked by a
32.768KHz crystal external to the ADSP-BF531/2/3 processor.
The RTC peripheral has dedicated power supply pins so that it
can remain powered up and clocked even when the rest of the
processor is in a low-power state. The RTC provides several
programmable interrupt options, including interrupt per sec-
ond, minute, hour, or day clock ticks, interrupt on
programmable stopwatch countdown, or interrupt at a pro-
grammed alarm time.
The 32.768KHz input clock frequency is divided down to a Hz signal by a prescaler. The counter function of the timer
consists of four counters: a 60-second counter, a 60-minute
counter, a 24-hour counter, and a 32,768-day counter.
When enabled, the alarm function generates an interrupt when
the output of the timer matches the programmed value in the
alarm control register. There are two alarms: The first alarm is
for a time of day. The second alarm is for a day and time of that
day.
The stopwatch function counts down from a programmed
value, with one-second resolution. When the stopwatch is
enabled and the counter underflows, an interrupt is generated.
Like other peripherals, the RTC can wake up the processor from
Sleep mode upon generation of any RTC wakeup event.
Additionally, an RTC wakeup event can wake up the processor
from Deep Sleep mode, and wake up the on-chip internal volt-
age regulator from a powered-down state.
Connect RTC pins RTXI and RTXO with external components
as shown in Figure6.
Figure 6.External Components for RTC
WATCHDOG TIMERThe ADSP-BF531/2/3 processor includes a 32-bit timer that can
be used to implement a software watchdog function. A software
watchdog can improve system availability by forcing the proces-
sor to a known state through generation of a hardware reset,
non-maskable interrupt (NMI), or general-purpose interrupt, if
the timer expires before being reset by software. The program-
mer initializes the count value of the timer, enables the
appropriate interrupt, then enables the timer. Thereafter, the
software must reload the counter before it counts to zero from
the programmed value. This protects the system from remain-
ing in an unknown state where software, which would normally
reset the timer, has stopped running due to an external noise
condition or software error.
If configured to generate a hardware reset, the watchdog timer
resets both the core and the ADSP-BF531/2/3 processor periph-
erals. After a reset, software can determine if the watchdog was
the source of the hardware reset by interrogating a status bit in
the watchdog timer control register.
The timer is clocked by the system clock (SCLK), at a maximum
frequency of fSCLK.
TIMERSThere are four general-purpose programmable timer units in
the ADSP-BF531/2/3 processor. Three timers have an external
pin that can be configured either as a Pulse-Width Modulator
(PWM) or timer output, as an input to clock the timer, or as a
mechanism for measuring pulse-widths and periods of external
events. These timers can be synchronized to an external clock
input to the PF1 pin, an external clock input to the PPI_CLK
pin, or to the internal SCLK.
The timer units can be used in conjunction with the UART to
measure the width of the pulses in the data stream to provide an
auto-baud detect function for a serial channel.
The timers can generate interrupts to the processor core provid-
ing periodic events for synchronization, either to the system
clock or to a count of external signals.
In addition to the three general-purpose programmable timers,
a fourth timer is also provided. This extra timer is clocked by the
internal processor clock and is typically used as a system tick
clock for generation of operating system periodic interrupts.
SERIAL PORTS (SPORTS)The ADSP-BF531/2/3 processor incorporates two dual-channel
synchronous serial ports (SPORT0 and SPORT1) for serial and
multiprocessor communications. The SPORTs support the fol-
lowing features:2S capable operation.Bidirectional operation – Each SPORT has two sets of inde-
pendent transmit and receive pins, enabling eight channels
of I2S stereo audio.Buffered (8-deep) transmit and receive ports – Each port
has a data register for transferring data words to and from Clocking – Each transmit and receive port can either use an
external serial clock or generate its own, in frequencies
ranging from (fSCLK/131,070)Hz to (fSCLK/2)Hz.Word length – Each SPORT supports serial data words
from 3 to 32bits in length, transferred most-significant-bit
first or least-significant-bit first.Framing – Each transmit and receive port can run with or
without frame sync signals for each data word. Frame sync
signals can be generated internally or externally, active high
or low, and with either of two pulse widths and early or late
frame sync.Companding in hardware – Each SPORT can perform
A-law or µ-law companding according to ITU recommen-
dation G.711. Companding can be selected on the transmit
and/or receive channel of the SPORT without additional
latencies.DMA operations with single-cycle overhead – Each SPORT
can automatically receive and transmit multiple buffers of
memory data. The processor can link or chain sequences of
DMA transfers between a SPORT and memory.Interrupts – Each transmit and receive port generates an
interrupt upon completing the transfer of a data-word or
after transferring an entire data buffer or buffers through
DMA.Multichannel capability – Each SPORT supports 128 chan-
nels out of a 1024-channel window and is compatible with
the H.100, H.110, MVIP-90, and HMVIP standards.
SERIAL PERIPHERAL INTERFACE (SPI) PORTThe ADSP-BF531/2/3 processor has an SPI-compatible port
that enables the processor to communicate with multiple SPI-
compatible devices.
The SPI interface uses three pins for transferring data: two data
pins (Master Output-Slave Input, MOSI, and Master Input-
Slave Output, MISO) and a clock pin (Serial Clock, SCK). An
SPI chip select input pin (SPISS) lets other SPI devices select the
processor, and seven SPI chip select output pins (SPISEL7–1) let
the processor select other SPI devices. The SPI select pins are
reconfigured Programmable Flag pins. Using these pins, the SPI
port provides a full-duplex, synchronous serial interface, which
supports both master/slave modes and multimaster
environments.
The SPI port’s baud rate and clock phase/polarities are pro-
grammable, and it has an integrated DMA controller,
configurable to support transmit or receive data streams. The
SPI’s DMA controller can only service unidirectional accesses at
any given time.
The SPI port’s clock rate is calculated as:
Where the 16-bit SPI_Baud register contains a value of 2 to
65,535.
SPI Clock RatefSCLKSPI_Baud×---------------------------------=
During transfers, the SPI port simultaneously transmits and
receives by serially shifting data in and out on its two serial data
lines. The serial clock line synchronizes the shifting and sam-
pling of data on the two serial data lines.
UART PORTThe ADSP-BF531/2/3 processor provides a full-duplex Univer-
sal Asynchronous Receiver/Transmitter (UART) port, which is
fully compatible with PC-standard UARTs. The UART port
provides a simplified UART interface to other peripherals or
hosts, supporting full-duplex, DMA-supported, asynchronous
transfers of serial data. The UART port includes support for 5 to data bits, 1 or 2stop bits, and none, even, or odd parity. The
UART port supports two modes of operation:PIO (Programmed I/O) – The processor sends or receives
data by writing or reading I/O-mapped UART registers.
The data is double-buffered on both transmit and receive.DMA (Direct Memory Access) – The DMA controller
transfers both transmit and receive data. This reduces the
number and frequency of interrupts required to transfer
data to and from memory. The UART has two dedicated
DMA channels, one for transmit and one for receive. These
DMA channels have lower default priority than most DMA
channels because of their relatively low service rates.
The UART port's baud rate, serial data format, error code gen-
eration and status, and interrupts are programmable:Supporting bit rates ranging from (fSCLK/ 1,048,576) to
(fSCLK/16) bits per second.Supporting data formats from 7 to12bits per frame.Both transmit and receive operations can be configured to
generate maskable interrupts to the processor.
The UART port’s clock rate is calculated as:
Where the 16-bit UART_Divisor comes from the DLH register
(most significant 8 bits) and DLL register (least significant
8bits).
In conjunction with the general-purpose timer functions, auto-
baud detection is supported.
The capabilities of the UART are further extended with support
for the Infrared Data Association (IrDA®) Serial Infrared Physi-
cal Layer Link Specification (SIR) protocol.
PROGRAMMABLE FLAGS (PFX) The ADSP-BF531/2/3 processor has 16 bidirectional, general-
purpose Programmable Flag (PF15–0) pins. Each programma-
ble flag can be individually controlled by manipulation of the
flag control, status and interrupt registers:Flag Direction Control Register – Specifies the direction of
each individual PFx pin as input or output.Flag Control and Status Registers – The ADSP-BF531/2/3
processor employs a “write one to modify” mechanism that
allows any combination of individual flags to be modified
in a single instruction, without affecting the level of any
other flags. Four control registers are provided. One regis-
ter is written in order to set flag values, one register is
written in order to clear flag values, one register is written
in order to toggle flag values, and one register is written in
order to specify a flag value. Reading the flag status register
allows software to interrogate the sense of the flags.Flag Interrupt Mask Registers – The two Flag Interrupt
Mask Registers allow each individual PFx pin to function as
an interrupt to the processor. Similar to the two Flag Con-
trol Registers that are used to set and clear individual flag
values, one Flag Interrupt Mask Register sets bits to enable
interrupt function, and the other Flag Interrupt Mask reg-
ister clears bits to disable interrupt function. PFx pins
defined as inputs can be configured to generate hardware
interrupts, while output PFx pins can be triggered by soft-
ware interrupts.Flag Interrupt Sensitivity Registers – The two Flag Inter-
rupt Sensitivity Registers specify whether individual PFx
pins are level- or edge-sensitive and specify—if edge-sensi-
tive—whether just the rising edge or both the rising and
falling edges of the signal are significant. One register
selects the type of sensitivity, and one register selects which
edges are significant for edge-sensitivity.
PARALLEL PERIPHERAL INTERFACEThe processor provides a Parallel Peripheral Interface (PPI) that
can connect directly to parallel A/D and D/A converters, ITU-R
601/656 video encoders and decoders, and other general-pur-
pose peripherals. The PPI consists of a dedicated input clock
pin, up to 3 frame synchronization pins, and up to 16 data pins.
The input clock supports parallel data rates up to half the system
clock rate.
In ITU-R 656 modes, the PPI receives and parses a data stream
of 8-bit or 10-bit data elements. On-chip decode of embedded
preamble control and synchronization information is
supported.
Three distinct ITU-R 656 modes are supported:Active Video Only - The PPI does not read in any data
between the End of Active Video (EAV) and Start of Active
Video (SAV) preamble symbols, or any data present during
UART Clock RatefSCLKUART_Divisor×------------------------------------------------=
the vertical blanking intervals. In this mode, the control
byte sequences are not stored to memory; they are filtered
by the PPI.Vertical Blanking Only - The PPI only transfers Vertical
Blanking Interval (VBI) data, as well as horizontal blanking
information and control byte sequences on VBI lines.Entire Field - The entire incoming bitstream is read in
through the PPI. This includes active video, control pream-
ble sequences, and ancillary data that may be embedded in
horizontal and vertical blanking intervals.
Though not explicitly supported, ITU-R 656 output functional-
ity can be achieved by setting up the entire frame structure
(including active video, blanking, and control information) in
memory and streaming the data out the PPI in a frame sync-less
mode. The processor’s 2D DMA features facilitate this transfer
by allowing the static frame buffer (blanking and control codes)
to be placed in memory once, and simply updating the active
video information on a per-frame basis.
The general-purpose modes of the PPI are intended to suit a
wide variety of data capture and transmission applications. The
modes are divided into four main categories, each allowing up
to 16 bits of data transfer per PPI_CLK cycle:Data Receive with Internally Generated Frame SyncsData Receive with Externally Generated Frame SyncsData Transmit with Internally Generated Frame SyncsData Transmit with Externally Generated Frame Syncs
These modes support ADC/DAC connections, as well as video
communication with hardware signaling. Many of the modes
support more than one level of frame synchronization. If
desired, a programmable delay can be inserted between asser-
tion of a frame sync and reception/transmission of data.
DYNAMIC POWER MANAGEMENTThe ADSP-BF531/2/3 processor provides five operating modes,
each with a different performance/power profile. In addition,
Dynamic Power Management provides the control functions to
dynamically alter the processor core supply voltage, further
reducing power dissipation. Control of clocking to each of the
ADSP-BF531/2/3 processor peripherals also reduces power con-
sumption. See Table4 for a summary of the power settings for
each mode.
Full-On Operating Mode—Maximum PerformanceIn the Full-On mode, the PLL is enabled and is not bypassed,
providing capability for maximum operational frequency. This
is the power-up default execution state in which maximum per-
formance can be achieved. The processor core and all enabled
peripherals run at full speed.
Active Operating Mode—Moderate Power SavingsIn the Active mode, the PLL is enabled but bypassed. Because
the PLL is bypassed, the processor’s core clock (CCLK) and sys-
tem clock (SCLK) run at the input clock (CLKIN) frequency. In
this mode, the CLKIN to CCLK multiplier ratio can be changed,
although the changes are not realized until the Full-On mode is
entered. DMA access is available to appropriately configured L1
memories.
In the Active mode, it is possible to disable the PLL through the
PLL Control register (PLL_CTL). If disabled, the PLL must be
re-enabled before transitioning to the Full-On or Sleep modes.
Hibernate Operating Mode—Maximum Static Power
SavingsThe Hibernate mode maximizes static power savings by dis-
abling the voltage and clocks to the processor core (CCLK) and
to all the synchronous peripherals (SCLK). The internal voltage
regulator for the processor can be shut off by writing b#00 to the
FREQ bits of the VR_CTL register. This disables both CCLK
and SCLK. Furthermore, it sets the internal power supply volt-
age (VDDINT) to 0 V to provide the lowest static power
dissipation. Any critical information stored internally (memory
contents, register contents, etc.) must be written to a non-vola-
tile storage device prior to removing power if the processor state
is to be preserved. Since VDDEXT is still supplied in this mode, all
of the external pins tri-state, unless otherwise specified. This
allows other devices that may be connected to the processor to
have power still applied without drawing unwanted current.
The internal supply regulator can be woken up either by a Real-
Time Clock wakeup or by asserting the RESET pin.
Sleep Operating Mode—High Dynamic Power SavingsThe Sleep mode reduces dynamic power dissipation by dis-
abling the clock to the processor core (CCLK). The PLL and
system clock (SCLK), however, continue to operate in this
mode. Typically an external event or RTC activity will wake up
the processor. When in the Sleep mode, assertion of wakeup will
cause the processor to sense the value of the BYPASS bit in the
PLL Control register (PLL_CTL). If BYPASS is disabled, the
processor will transition to the Full On mode. If BYPASS is
enabled, the processor will transition to the Active mode.
When in the Sleep mode, system DMA access to L1 memory is
not supported.
Deep Sleep Operating Mode—Maximum Dynamic Power
SavingsThe Deep Sleep mode maximizes dynamic power savings by
disabling the clocks to the processor core (CCLK) and to all syn-
Table 4.Power Settings
as the RTC, may still be running but will not be able to access
internal resources or external memory. This powered-down
mode can only be exited by assertion of the reset interrupt
(RESET) or by an asynchronous interrupt generated by the
RTC. When in Deep Sleep mode, an RTC asynchronous inter-
rupt causes the processor to transition to the Active mode.
Assertion of RESET while in Deep Sleep mode causes the pro-
cessor to transition to the Full-On mode.
Power SavingsAs shown in Table5, the ADSP-BF531/2/3 processor supports
three different power domains. The use of multiple power
domains maximizes flexibility, while maintaining compliance
with industry standards and conventions. By isolating the inter-
nal logic of the ADSP-BF531/2/3 processor into its own power
domain, separate from the RTC and other I/O, the processor
can take advantage of Dynamic Power Management, without
affecting the RTC or other I/O devices. There are no sequencing
requirements for the various power domains.
The power dissipated by a processor is largely a function of the
clock frequency of the processor and the square of the operating
voltage. For example, reducing the clock frequency by 25%
results in a 25% reduction in dynamic power dissipation, while
reducing the voltage by 25% reduces dynamic power dissipation
by more than 40%. Further, these power savings are additive, in
that if the clock frequency and supply voltage are both reduced,
the power savings can be dramatic.
The Dynamic Power Management feature of the ADSP-
BF531/2/3 processor allows both the processor’s input voltage
(VDDINT) and clock frequency (fCCLK) to be dynamically
controlled.
The savings in power dissipation can be modeled using the
Power Savings Factor and %Power Savings calculations.
The Power Savings Factor is calculated as:
where the variables in the equations are:
•fCCLKNOM is the nominal core clock frequency
•fCCLKRED is the reduced core clock frequency
•VDDINTNOM is the nominal internal supply voltage
•VDDINTRED is the reduced internal supply voltage
•TNOM is the duration running at fCCLKNOM
•TRED is the duration running at fCCLKRED
The percent power savings is calculated as:
VOLTAGE REGULATIONThe Blackfin processor provides an on-chip voltage regulator
that can generate processor core voltage levels 0.85V(-5% /
+10%) to 1.2V(-5% / +10%) from an external 2.25V to 3.6V
supply. Figure7 shows the typical external components
required to complete the power management system.* The regu-
lator controls the internal logic voltage levels and is
programmable with the Voltage Regulator Control Register
(VR_CTL) in increments of 50mV. To reduce standby power
consumption, the internal voltage regulator can be programmed
to remove power to the processor core while keeping I/O power
(VDDEXT) supplied. While in hibernation, VDDEXT can still be
applied, eliminating the need for external buffers. The voltage
regulator can be activated from this power-down state either
through an RTC wakeup or by asserting RESET, which will then
initiate a boot sequence. The regulator can also be disabled and
bypassed at the user’s discretion.
CLOCK SIGNALSThe ADSP-BF531/2/3 processor can be clocked by an external
crystal, a sine wave input, or a buffered, shaped clock derived
from an external clock oscillator.
If an external clock is used, it should be a TTL compatible signal
and must not be halted, changed, or operated below the speci-
fied frequency during normal operation. This signal is
connected to the processor’s CLKIN pin. When an external
clock is used, the XTAL pin must be left unconnected.
Table 5.Power DomainsPower Savings Factor
fCCLKRED
fCCLKNOM---------------------VDDINTRED
VDDINTNOM--------------------------2×TRED
TNOM-------------×=
Figure 7.Voltage Regulator Circuit
% Power Savings1Power Savings Factor–()100%×=
Alternatively, because the ADSP-BF531/2/3 processor includes
an on-chip oscillator circuit, an external crystal may be used.
The crystal should be connected across the CLKIN and XTAL
pins, with two capacitors connected as shown in Figure8.
Capacitor values are dependent on crystal type and should be
specified by the crystal manufacturer. A parallel-resonant,
fundamental frequency, microprocessor-grade crystal should be
used.
As shown in Figure9 on Page13, the core clock (CCLK) and
system peripheral clock (SCLK) are derived from the input
clock (CLKIN) signal. An on-chip PLL is capable of multiplying
the CLKIN signal by a user programmable 1x to 63x multiplica-
tion factor (bounded by specified minimum and maximum
VCO frequencies). The default multiplier is 10x, but it can be
modified by a software instruction sequence. On-the-fly fre-
quency changes can be effected by simply writing to the
PLL_DIV register.
All on-chip peripherals are clocked by the system clock (SCLK).
The system clock frequency is programmable by means of the
SSEL3–0 bits of the PLL_DIV register. The values programmed
into the SSEL fields define a divide ratio between the PLL output
(VCO) and the system clock. SCLK divider values are 1 through
15. Table6 illustrates typical system clock ratios.
The maximum frequency of the system clock is fSCLK. Note that
the divisor ratio must be chosen to limit the system clock fre-
quency to its maximum of fSCLK. The SSEL value can be changed
dynamically without any PLL lock latencies by writing the
appropriate values to the PLL divisor register (PLL_DIV).
The core clock (CCLK) frequency can also be dynamically
changed by means of the CSEL1–0 bits of the PLL_DIV register.
Supported CCLK divider ratios are 1, 2, 4, and 8, as shown in
Table7. This programmable core clock capability is useful for
fast core frequency modifications.
BOOTING MODESThe ADSP-BF531/2/3 processor has two mechanisms (listed in
Table8) for automatically loading internal L1 instruction mem-
ory after a reset. A third mode is provided to execute from
external memory, bypassing the boot sequence.
Figure 8.External Crystal Connections
Figure 9.Frequency Modification Methods
Table 6.Example System Clock Ratios
Table 7.Core Clock Ratios
Table 8.Booting Modes
The BMODE pins of the Reset Configuration Register, sampled
during power-on resets and software-initiated resets, imple-
ment the following modes:Execute from 16-bit external memory – Execution starts
from address 0x2000 0000 with 16-bit packing. The boot
ROM is bypassed in this mode. All configuration settings
are set for the slowest device possible (3-cycle hold time;
15-cycle R/W access times; 4-cycle setup).Boot from 8-bit or 16-bit external FLASH memory – The
FLASH boot routine located in boot ROM memory space is
set up using Asynchronous Memory Bank 0. All configura-
tion settings are set for the slowest device possible (3-cycle
hold time; 15-cycle R/W access times; 4-cycle setup).Boot from SPI serial EEPROM (8, 16, or 24-bit
addressable) – The SPI uses the PF2 output pin to select a
single SPI EEPROM device, submits successive read com-
mands at addresses 0x00, 0x0000, and 0x000000 until a
valid 8, 16, or 24-bit addressable EEPROM is detected, and
begins clocking data into the beginning of L1 instruction
memory.
For each of the boot modes, an 10-byte header is first read from
an external memory device. The header specifies the number of
bytes to be transferred and the memory destination address.
Multiple memory blocks may be loaded by any boot sequence.
Once all blocks are loaded, program execution commences from
the start of L1 instruction SRAM.
In addition, bit 4 of the Reset Configuration Register can be set
by application code to bypass the normal boot sequence during
a software reset. For this case, the processor jumps directly to
the beginning of L1 instruction memory.
INSTRUCTION SET DESCRIPTIONThe Blackfin processor family assembly language instruction set
employs an algebraic syntax designed for ease of coding and
readability. The instructions have been specifically tuned to pro-
vide a flexible, densely encoded instruction set that compiles to
a very small final memory size. The instruction set also provides
fully featured multifunction instructions that allow the pro-
grammer to use many of the processor core resources in a single
instruction. Coupled with many features more often seen on
microcontrollers, this instruction set is very efficient when com-
piling C and C++ source code. In addition, the architecture
supports both user (algorithm/application code) and supervisor
(O/S kernel, device drivers, debuggers, ISRs) modes of opera-
tion, allowing multiple levels of access to core processor
resources.
The assembly language, which takes advantage of the proces-
sor’s unique architecture, offers the following advantages:Seamlessly integrated DSP/CPU features are optimized for
both 8-bit and 16-bit operations.A multi-issue load/store modified-Harvard architecture,
which supports two 16-bit MAC or four 8-bit ALU + two
load/store + two pointer updates per cycle.All registers, I/O, and memory are mapped into a unified byte memory space, providing a simplified program-
ming model.Microcontroller features, such as arbitrary bit and bit-field
manipulation, insertion, and extraction; integer operations
on 8-, 16-, and 32-bit data-types; and separate user and
supervisor stack pointers.Code density enhancements, which include intermixing of
16- and 32-bit instructions (no mode switching, no code
segregation). Frequently used instructions are encoded in
16 bits.
DEVELOPMENT TOOLSThe ADSP-BF531/2/3 processor is supported with a complete
set of CROSSCORE®† software and hardware development
tools, including Analog Devices emulators and VisualDSP++®‡
development environment. The same emulator hardware that
supports other Blackfin processors also fully emulates the
ADSP-BF531/2/3 processor.
The VisualDSP++ project management environment lets pro-
grammers develop and debug an application. This environment
includes an easy to use assembler (which is based on an alge-
braic syntax), an archiver (librarian/library builder), a linker, a
loader, a cycle-accurate instruction-level simulator, a C/C++
compiler, and a C/C++ runtime library that includes DSP and
mathematical functions. A key point for these tools is C/C++
code efficiency. The compiler has been developed for efficient
translation of C/C++ code to processor assembly. The processor
has architectural features that improve the efficiency of com-
piled C/C++ code.
The VisualDSP++ debugger has a number of important fea-
tures. Data visualization is enhanced by a plotting package that
offers a significant level of flexibility. This graphical representa-
tion of user data enables the programmer to quickly determine
the performance of an algorithm. As algorithms grow in com-
plexity, this capability can have increasing significance on the
designer’s development schedule, increasing productivity. Sta-
tistical profiling enables the programmer to nonintrusively poll
the processor as it is running the program. This feature, unique
to VisualDSP++, enables the software developer to passively
gather important code execution metrics without interrupting
the real-time characteristics of the program. Essentially, the
developer can identify bottlenecks in software quickly and effi-
ciently. By using the profiler, the programmer can focus on
those areas in the program that impact performance and take
corrective action.
Debugging both C/C++ and assembly programs with the
VisualDSP++ debugger, programmers can:View mixed C/C++ and assembly code (interleaved source
and object information).Insert breakpoints.
Set conditional breakpoints on registers, memory, andstacks.Trace instruction execution.Perform linear or statistical profiling of program execution.Fill, dump, and graphically plot the contents of memory.Perform source level debugging.Create custom debugger windows.
The VisualDSP++ IDDE lets programmers define and manage
software development. Its dialog boxes and property pages let
programmers configure and manage all of the Blackfin develop-
ment tools, including the color syntax highlighting in the
VisualDSP++ editor. This capability permits programmers to:Control how the development tools process inputs and
generate outputs.Maintain a one-to-one correspondence with the tool’s
command line switches.
The VisualDSP++ Kernel (VDK) incorporates scheduling and
resource management tailored specifically to address the mem-
ory and timing constraints of DSP programming. These
capabilities enable engineers to develop code more effectively,
eliminating the need to start from the very beginning, when
developing new application code. The VDK features include
Threads, Critical and Unscheduled regions, Semaphores,
Events, and Device flags. The VDK also supports Priority-based,
Preemptive, Cooperative, and Time-Sliced scheduling
approaches. In addition, the VDK was designed to be scalable. If
the application does not use a specific feature, the support code
for that feature is excluded from the target system.
Because the VDK is a library, a developer can decide whether to
use it or not. The VDK is integrated into the VisualDSP++
development environment, but can also be used via standard
command line tools. When the VDK is used, the development
environment assists the developer with many error-prone tasks
and assists in managing system resources, automating the gen-
eration of various VDK based objects, and visualizing the
system state, when debugging an application that uses the VDK.
VCSE is Analog Devices technology for creating, using, and
reusing software components (independent modules of sub-
stantial functionality) to quickly and reliably assemble software
applications. Download components from the Web and drop
them into the application. Publish component archives from
within VisualDSP++. VCSE supports component implementa-
tion in C/C++ or assembly language.
Use the Expert Linker to visually manipulate the placement of
code and data on the embedded system. View memory utiliza-
tion in a color-coded graphical form, easily move code and data
to different areas of the processor or external memory with the
drag of the mouse, examine run time stack and heap usage. The
Expert Linker is fully compatible with existing Linker Definition
File (LDF), allowing the developer to move between the graphi-
cal and textual environments.
Analog Devices emulators use the IEEE 1149.1 JTAG Test
lator provides full speed emulation, allowing inspection and
modification of memory, registers, and processor stacks. Non-
intrusive in-circuit emulation is assured by the use of the
processor’s JTAG interface—the emulator does not affect target
system loading or timing.
In addition to the software and hardware development tools
available from Analog Devices, third parties provide a wide
range of tools supporting the Blackfin processor family. Hard-
ware tools include Blackfin processor PC plug-in cards. Third
party software tools include DSP libraries, real-time operating
systems, and block diagram designtools.
DESIGNING AN EMULATOR COMPATIBLE
PROCESSOR BOARDThe Analog Devices family of emulators are tools that every sys-
tem developer needs to test and debug hardware and software
systems. Analog Devices has supplied an IEEE 1149.1 JTAG
Test Access Port (TAP) on each JTAG processor. The emulator
uses the TAP to access the internal features of the processor,
allowing the developer to load code, set breakpoints, observe
variables, observe memory, and examine registers. The proces-
sor must be halted to send data and commands, but once an
operation has been completed by the emulator, the processor
system is set running at full speed with no impact on system
timing.
To use these emulators, the target board must include a header
that connects the processor’s JTAG port to the emulator.
For details on target board design issues including mechanical
layout, single processor connections, multiprocessor scan
chains, signal buffering, signal termination, and emulator pod
logic, see the EE-68: Analog Devices JTAG Emulation Technical
Reference on the Analog Devices web site ()—
use site search on “EE-68.” This document is updated regularly
to keep pace withimprovements to emulator support.
PIN DESCRIPTIONSADSP-BF531/2/3 processor pin definitions are listed in Table9.
All pins are three-stated during and immediately after reset,
except the Memory Interface, Asynchronous Memory Control,
and Synchronous Memory Control pins, which are driven high.
If BR is active, then the memory pins are also three-stated. All
unused I/O pins have their input buffers disabled with the
exception of the pins that need pullups or pulldowns as noted in
the table footnotes.
In order to maintain maximum functionality and reduce pack-
age size and pin count, some pins have dual, multiplexed
functionality. In cases where pin functionality is reconfigurable,
the default state is shown in plain text, while alternate function-
ality is shown in italics.
Table 9.Pin Descriptions
Table 9.Pin Descriptions (Continued)
Refer to Figure26 on Page39 to Figure30 on Page40.2See Figure25 and Figure26 on Page39This pin should be pulled HIGH when not used.
4See Figure27 and Figure28 on Page39See Figure29 and Figure30 on Page40See Figure31 and Figure32 on Page40This pin should always be pulled HIGH through a 4.7K Ohm resistor if booting via the SPI port.
8This pin should always be pulled LOW when not used.This pin should be pulled LOW if the JTAG port will not be used.
Table 9.Pin Descriptions (Continued)
SPECIFICATIONSComponent specifications are subject to change
without notice.
RECOMMENDED OPERATING CONDITIONS
ELECTRICAL CHARACTERISTICS The ADSP-BF531/2/3 processor is 3.3 V tolerant (always accepts up to 3.6 V maximum VIH), but voltage compliance (on outputs, VOH) depends on the input VDDEXT, because
VOH (maximum) approximately equals VDDEXT (maximum). This 3.3 V tolerance applies to bidirectional pins (DATA15–0, TMR2–0, PF15–0, PPI3–0, RSCLK1–0,
TSCLK1–0, RFS1–0, TFS1–0, MOSI, MISO, SCK) and input only pins (BR, ARDY, PPI_CLK, DR0PRI, DR0SEC, DR1PRI, DR1SEC, RX, RTXI, TCK, TDI, TMS, TRST,
CLKIN, RESET, NMI, and BMODE1–0).Parameter value applies to all input and bidirectional pins except CLKIN.Parameter value applies to CLKIN pin only.Parameter value applies to all input and bidirectional pins.Applies to output and bidirectional pins.Applies to input pins except JTAG inputs.Applies to JTAG input pins (TCK, TDI, TMS, TRST).Applies to three-statable pins.Applies to all signal pins.Guaranteed, but not tested.
ABSOLUTE MAXIMUM RATINGSStresses greater than those listed in the table may cause perma-
nent damage to the device. These are stress ratings only.
Functional operation of the device at these or any other condi-
tions greater than those indicated in the operational sections of
this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device
reliability.
For proper SDRAM controller operation, the maximum load
capacitance is 50 pF (at 3.3V) or 30 pF (at 2.5 V) for
ADDR19–1, DATA15–0, ABE1–0/SDQM1–0, CLKOUT,
SCKE, SA10, SRAS, SCAS, SWE, and SMS.
ESD SENSITIVITY
CAUTIONESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the ADSP-BF531/2/3 processor features proprietary ESD protection circuitry, permanent damage
may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
TIMING SPECIFICATIONSTable10 through Table14 describe the timing requirements for
the ADSP-BF531/2/3 processor clocks. Take care in selecting
MSEL, SSEL, and CSEL ratios so as not to exceed the maximum
core clock and system clock as described in Absolute Maximum
Ratings on Page20, and the Voltage Controlled Oscillator
(VCO) operating frequencies described in Table13. Table13
describes Phase-Locked Loop operating conditions.
Table 10.Core and System Clock Requirements—ADSP-BF533SKBC600
Table 11.Core and System Clock Requirements—ADSP-BF533SBBC500 and ADSP-BF533SBBZ500
Table 12.Core and System Clock Requirements—ADSP-BF532/531 All Package Types
Table 13.Phase-Locked Loop Operating Conditions
Table 14.Maximum SCLK Conditions Set bit 7 (output delay) of PLL_CTL register.
Clock and Reset TimingTable15 and Figure10 describe clock and reset operations. Per
Absolute Maximum Ratings on Page20, combinations of
CLKIN and clock multipliers must not select core/peripheral
clocks in excess of 600/133 MHz.
Table 15.Clock and Reset TimingApplies to bypass mode and non-bypass mode.
2Applies after power-up sequence is complete. At power-up, the processor’s internal phase-locked loop requires no more than 2000 CLKIN cycles, while RESET is asserted,
assuming stable power supplies and CLKIN (not including start-up time of external clock oscillator).
Figure 10.Clock and Reset Timing
Asynchronous Memory Read Cycle Timing
Table 16.Asynchronous Memory Read Cycle Timing Output pins include AMS3–0, ABE1–0, ADDR19–1, AOE, ARE.
Figure 11.Asynchronous Memory Read Cycle Timing
Asynchronous Memory Write Cycle Timing
Table 17.Asynchronous Memory Write Cycle Timing Output pins include AMS3–0, ABE1–0, ADDR19–1, DATA15–0, AOE, AWE.
Figure 12.Asynchronous Memory Write Cycle Timing
SDRAM Interface Timing
Table 18.SDRAM Interface Timing1For VDDINT = 1.2 V.Command pins include: SRAS, SCAS, SWE, SDQM, SMS, SA10, SCKE.
Figure 13.SDRAM Interface Timing
External Port Bus Request and Grant Cycle TimingTable19 and Figure14 describe external port bus request and
bus grant operations.
Table 19.External Port Bus Request and Grant Cycle TimingThese are preliminary timing parameters that are based on worst-case operating conditions.The pad loads for these timing parameters are 20pF.
Figure 14.External Port Bus Request and Grant Cycle Timing
Parallel Peripheral Interface TimingTable20 and Figure15 on Page27 describe Parallel Peripheral
Interface operations.
Table 20.Parallel Peripheral Interface TimingPPI_CLK frequency cannot exceed fSCLK/2
Figure 15.GP Output Mode and Frame Capture Timing
Serial PortsTable21 through Table26 on Page29 and Figure16 on Page30
through Figure18 on Page32 describe Serial Port operations.
Table 21.Serial Ports—External Clock Referenced to sample edge.
Table 22.Serial Ports—Internal Clock 1Referenced to sample edge.
Table 23.Serial Ports—External Clock Referenced to drive edge.
Table 24.Serial Ports—Internal Clock Referenced to drive edge.
