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AM26C32CD ,Quadruple Differential Line ReceiverTable of Contents8.2 Functional
ADSP-21MOD980N-000
MultiPort Internet Gateway Processor
MultiPort Internet
Gateway ProcessorREV. PrB 6/2001
PERFORMANCE FEATURES
Complete Single Device Multi-Port Internet Gateway
Processor (No External Memory Required)
Implements Sixteen Modem Channels or Forty Voice
Channels in One Package
Each DSP Can Implement two V.34/V.90 Data/Fax
Modem Channels (includes Datapump and
Controller)
Low Power Version: 640 MIPS Sustained Performance,
12.5 ns Instruction Time @ 1.9 Volts nominal
(internal)
Open Architecture Extensible to Voice-over-Network
(VoN) and Other Applications
Low Power Dissipation, 25 mW (typical) per Channel
Powerdown Mode Featuring Low CMOS Standby Power
Dissipation
INTEGRATION FEATURES
ADSP-2100 Family Code-Compatible, with Instruction
Set Extensions
16 Mbits of On-Chip SRAM, Configured as 9 Mbits of
Program Memory and 7 Mbits of Data Memory
Dual-Purpose Program Memory, for Both Instruction
and Data Storage
352-Ball PBGA with a 35mm � 35mm footprint
SYSTEM CONFIGURATION FEATURES
16-Bit Internal DMA Port for High-Speed Access to
On-Chip Memory (Mode-Selectable)
Programmable Multichannel Serial Port Supports 24/32
Channelswo Double-Buffered Serial Ports with Companding
Hardware and Automatic Data Buffering
Separate Reset Pins for Each Internal Processor Figure 1. MOD980N MultiPort Internet Gateway Processor Block Diagram
PRELIMINARY TECHNICAL DATA
GENERAL DESCRIPTIONThe ADSP-21mod980N is a multi-port Internet gateway
processor optimized for implementation of a complete
V.34/V.90 digital modem. All datapump and controller
functions can be implemented on a single device, offering
the lowest power consumption and highest possible modem
port density.
The ADSP-21mod980N combines the ADSP-2100 Family
base architecture (three computational units, data address
generators, and a program sequencer) with two serial ports,
a 16-bit internal DMA port, a byte DMA port, a program-
mable timer, Flag I/O, extensive interrupt capabilities, and
on-chip program and data memory.
The ADSP-21mod980N integrates 16 Mbits of on-chip
memory, configured as 384 Kwords (24-bit) of program
RAM, and 448 Kwords (16-bit) of data RAM. Power-down
circuitry is also provided to reduce the average and standby
power consumption of equipment which in turn reduces
equipment cooling requirements. The ADSP-21mod980N
is available in a 35 mm x 35 mm, 352-lead PBGA package.
Fabricated in a high-speed, low-power, CMOS process, the
ADSP-21mod980N operates with a 12.5 ns instruction
cycle time. Every instruction can execute in a single proces-
sor cycle.
The ADSP-21mod980N’s flexible architecture and com-
prehensive instruction set allow the processor to perform
multiple operations in parallel. In one processor cycle, the
ADSP-21mod980N can:Generate the next program addressFetch the next instructionPerform one or two data movesUpdate one or two data address pointersPerform a computational operation
This takes place while the processor continues to:Receive and transmit data through the two serial portsReceive and/or transmit data through the internal
DMA portReceive and/or transmit data through the byte DMA
portDecrement timer
MODEM SOFTWARE The following software is available as object code from
Analog Devices Inc.ADSP-21mod Family Dynamic Internet Voice
AccessTM (DIVA) Voice Over Network Solution.ADSP-21mod980-210N Multiport Internet Gateway
Processor Modem Solution.
A complete system implementation requires the
ADSP-21mod980N device plus modem or voice software.
The modem software executes general modem control,
command sets, error correction, and data compression,
data modulations (for example, V.34 and V.90), and host
interface functions.The host interface allows system access
to modem statistics, such as call progress, connect speed,
retrain count, symbol rate, and other modulation
parameters.
The modem datapump and controller software reside in
on-chip SRAM and do not require additional memory. You
can configure the ADSP-21mod980N dynamically by
downloading software from the host through the 16-bit
IDMA interface. This SRAM-based architecture provides a
software upgrade path to other applications, such as
voice-over-IP, and to future standards.
DEVELOPMENT SYSTEMAnalog Devices' wide range of software and hardware devel-
opment tools supports the ADSP-218x N Series. The DSP
tools include an integrated development environment
(IDE), an evaluation kit, and a serial port emulator.
VisualDSP® is an integrated development environment,
allowing for fast and easy development, debug and deploy-
ment. The VisualDSP project management environment
lets programmers develop and debug an application. This
environment includes an easy-to-use assembler that is based
on an algebraic syntax; an archiver (librarian/library
builder); a linker; a loader; a cycle-accurate, instruc-
tion-level simulator; a C compiler; and a C run-time library
that includes DSP and mathematical functions.
Debugging both C and assembly programs with the Visu-
alDSP debugger, programmers can:View mixed C and assembly code (interleaved source and
object information)Insert break pointsSet conditional breakpoints on registers, memory, and
stacksTrace instruction executionFill and dump memorySource level debugging
PRELIMINARY TECHNICAL DATAThe VisualDSP IDE lets programmers define and manage
DSP software development. The dialog boxes and property
pages let programmers configure and manage all of the
ADSP-218x development tools, including the syntax high-
lighting in the VisualDSP editor. This capability controls
how the development tools process inputs and generate
outputs.
The ADSP-218x EZ-ICE ® Emulator provides an easier
and more cost-effective method for engineers to develop
and optimize DSP systems, shortening product develop-
ment cycles for faster time-to-market. The
ADSP-21mod980N integrates on-chip emulation support
with a 14-pin ICE-Port interface. This interface provides a
simpler target board connection that requires fewer
mechanical clearance considerations than other
ADSP-2100 Family EZ-ICEs. The ADSP-21mod980N
device need not be removed from the target system when
using the EZ-ICE, nor are any adapters needed. Due to the
small footprint of the EZ-ICE connector, emulation can be
supported in final board designs.The EZ-ICE performs a
full range of functions, including:In-target operationUp to 20 breakpointsSingle-step or full-speed operationRegisters and memory values can be examined and
alteredPC upload and download functionsInstruction-level emulation of program booting and
executionComplete assembly and disassembly of instructionsC source-level debugging
ADDITIONAL INFORMATIONThis data sheet provides a general overview of
ADSP-21mod980N functionality. For specific information
about the modem processors, refer to the ADSP-2188N
data sheet. For additional information on the architecture
and instruction set of the modem processors, refer to the
ADSP-2100 Family User’s Manual (3rd edition). For more
information about the development tools, refer to the
ADSP-2100 Family Development Tools Data Sheet.
PRELIMINARY TECHNICAL DATA
ARCHITECTURE OVERVIEWFigure 2 on page 4 is a functional block diagram of the
ADSP-21mod980N. It contains eight independent digital
signal processors.
Every modem processor has:A DSP core256K bytes of RAMTwo serial portsAn IDMA host.
The signals of each modem processor are accessed through
the external pins of the ADSP-21mod980N. Some signals
accessed through a single external pin. Other signals remain
separate and they are accessed through separate external
pins for each processor.
The arrangement of the eight modem processors in the
ADSP-21mod980N makes one basic configuration possi-
ble: a slave configuration. In this configuration, the data
pins of all eight processors connect to a single bus structure.
Figure 2. ADSP-21mod980N Functional Block Diagram
PRELIMINARY TECHNICAL DATAAll eight modem processors have identical functions and
have equal status. Each of the modem processors is con-
nected to a common IDMA bus and each modem processor
is configured to operate in the same mode (see the slave
mode and the memory mode descriptions in “Memory
Architecture” on page10). The slave mode is considered to
be the only mode of operation in the ADSP-21mod980N
modem pool.
SERIAL PORTSThe ADSP-21mod980N has a multichannel serial port
(SPORT) connected to each internal digital modem pro-
cessor for serial communications.
The following is a brief list of ADSP-21mod980N SPORT
features. For additional information on the internal Serial
Ports, refer to the ADSP-2100 Family User’s Manual. Each
SPORT:is bidirectional and has a separate, double-buffered
transmit and receive section.can use an external serial clock or generate its own
serial clock internally.has independent framing for the receive and transmit
sections. Sections run in a frameless mode or with
frame synchronization signals internally or externally
generated. Frame sync signals are active high or
inverted, with either of two pulse widths and timings.supports serial data word lengths from 3 to 16 bits and
provides optional A-law and µ-law companding accord-
ing to CCITT recommendation G.711.receive and transmit sections can generate unique
interrupts on completing a data word transfer.can receive and transmit an entire circular buffer of
data with one overhead cycle per data word. An inter-
rupt is generated after a data buffer transfer.
A multichannel interface selectively receives and transmits a
24 or 32 word, time-division multiplexed, serial bitstream.
PIN DESCRIPTIONSThe ADSP-21mod980N is available in a 352-lead PBGA
package. In order to maintain maximum functionality and
reduce package size and pin count, some serial port, pro-
grammable flag, interrupt and external bus pins have dual,
multiplexed functionality. The external bus pins are config-
ured during RESET only, while serial port pins are software
configurable during program execution. Flag and interrupt
functionality is retained concurrently on multiplexed pins.
Table on page6 lists the pin names and their functions. In
cases where pin functionality is reconfigurable, the default
state is shown in plain text; alternate functionality is shown
in italics.
PRELIMINARY TECHNICAL DATA
MEMORY INTERFACE PINSThe ADSP-21mod980N modem pool is used in Slave
Mode. In Slave Mode, the Modem Processors operate in
host configuration. The operating mode is determined by
the state of the Mode C pin during RESET and cannot be
changed while the modem pool is running. See the “Mem-
ory Architecture” section for more information.
Table 1. Common Mode PinsInterrupt/Flag Pins retain both functions concurrently. If IMASK is set to enable the corresponding interrupts, then the ADSP-21mod980N will vector
to the appropriate interrupt vector address when the pin is asserted, either by external devices, or set as a programmable flag.SPORT configuration determined by the ADSP-21mod980N System Control Register. Software configurable.
PRELIMINARY TECHNICAL DATA
INTERRUPTSThe interrupt controller allows each modem processor in
the modem pool to respond individually to eleven possible
interrupts and RESET with minimum overhead. The
ADSP-21mod980N provides four dedicated external inter-
rupt input pins, IRQ2, IRQL1, IRQL0, and IRQE (shared
with the PF[7:4] pins) for each modem processor. The
ADSP-21mod980N also supports internal interrupts from
the timer, the byte DMA port, the serial port, software, and
the power-down control circuit. The interrupt levels are
internally prioritized and individually maskable (except
power down and RESET). The IRQ2, IRQ1, and IRQ0
input pins can be programmed to be either level- or
edge-sensitive. IRQL0 and IRQL1 are level-sensitive and
IRQE is edge sensitive. The priorities and vector addresses
of all interrupts are shown in Table on page7. When the
modem pool is reset, interrupt servicing is disabled.
LOW POWER OPERATIONThe ADSP-21mod980N has three low power modes that
significantly reduce the power dissipation when the device
operates under standby conditions. These modes are:Power DownIdleSlow Idle
The CLKOUT pin may also be disabled to reduce external
power dissipation.
POWER DOWNThe ADSP-21mod980N modem pool has a low power fea-
ture that lets the modem pool enter a very low power
dormant state through software control. Here is a brief list
Table 2. Host Pins (Mode C = 1) Modem Processors 1-8There are two distinct IAD buses. One addresses DSPs 1-4 and the other
communicates with DSPs 5-8. See Figure 2 for details.
Table 3. Interrupt Priority and Interrupt Vector
Addresses
PRELIMINARY TECHNICAL DATAof power-down features. Refer to the ADSP-2100 Family
User’s Manual, “System Interface” chapter, for detailed
information about the power-down feature.Quick recovery from power down. The modem pool
begins executing instructions in as few as 200 CLKIN
cycles.Support for an externally generated TTL or CMOS
processor clock. The external clock can continue run-
ning during power down without affecting the lowest
power rating and 200 CLKIN cycle recovery.Power down is initiated by the software power-down
force bit. Interrupt support allows an unlimited num-
ber of instructions to be executed before optionally
powering down. Context clear/save control allows the modem pool to
continue where it left off or start with a clean context
when leaving the power down state.The RESET pin also can be used to terminate power
down.
IDLEWhen the ADSP-21mod980N is in the Idle Mode, the
modem pool waits indefinitely in a low power state until an
interrupt occurs. When an unmasked interrupt occurs, it is
serviced; execution then continues with the instruction fol-
lowing the IDLE instruction. In Idle mode IDMA, BDMA
and autobuffer cycle steals still occur.
SLOW IDLEThe IDLE instruction is enhanced on the
ADSP-21mod980N to let the modem pool’s internal clock
signal be slowed, further reducing power consumption. The
reduced clock frequency, a programmable fraction of the
normal clock rate, is specified by a selectable divisor given
in the IDLE instruction.
The format of the instruction is:
IDLE (n);
where n = 16, 32, 64, or 128. This instruction keeps the
modem pool fully functional, but operating at the slower
clock rate. While it is in this state, the modem pool’s other
internal clock signals, such as SCLK, CLKOUT, and timer
clock, are reduced by the same ratio. The default form of
the instruction, when no clock divisor is given, is the stan-
dard IDLE instruction.
When the IDLE (n) instruction is used, it effectively slows
down the modem pool’s internal clock and thus its response
time to incoming interrupts. The one-cycle response time
of the standard idle state is increased by n, the clock divisor.
When an enabled interrupt is received, the
ADSP-21mod980N will remain in the idle state for up to a
maximum of n modem pool cycles (n = 16, 32, 64, or 128)
before resuming normal operation.
When the IDLE (n) instruction is used in systems that have
an externally generated serial clock (SCLK), the serial clock
rate may be faster than the modem pool’s reduced internal
clock rate. Under these conditions, interrupts must not be
generated at a faster rate than can be serviced, due to the
additional time the modem pool takes to come out of the
idle state (a maximum of n cycles).
SYSTEM CONFIGURATIONFigure on page9 shows the hardware interfaces for a typi-
cal multichannel modem configuration with the
ADSP-21mod980N. Other system design considerations
such as host processing requirements, electrical loading,
and overall bus timing must all be met. A line interface can
be used to connect the multichannel subscriber or client
data stream to the multichannel serial port of the
ADSP-21mod980N. The IDMA port of the
ADSP-21mod980N is used to give a host processor full
access to the internal memory of the ADSP-21mod980N.
This lets the host dynamically configure the
ADSP-21mod980N by loading code and data into its inter-
nal memory. This configuration also lets the host access
server data directly from the ADSP-21mod980N’s internal
memory. In this configuration, the Modem Processors
should be put into host memory mode where Mode C = 1,
Mode B = 0, and Mode A = 1.
PRELIMINARY TECHNICAL DATA
CLOCK SIGNALSThe ADSP-21mod980N is clocked by a TTL-compatible
clock signal that runs at half the instruction rate; a 40 MHz
input clock yields a 12.5 ns processor cycle, which is equiv-
alent to 80 MHz. Normally, instructions are executed in a
single processor cycle. All device timing is relative to the
internal instruction clock rate, which is indicated by the
CLKOUT signal when enabled. The clock input signal is
The CLKIN input cannot be halted, changed during oper-
ation, or operated below the specified frequency during
normal operation. The only exception is while the processor
is in the power down state. For additional information, refer
to Chapter 9, ADSP-2100 Family User’s Manual for a
detailed explanation of this power down feature.
Figure 3. Multichannel Modem Configuration
PRELIMINARY TECHNICAL DATAA clock output (CLKOUT) signal is generated by the pro-
cessor at the processor’s cycle rate. This can be enabled and
disabled by the CLKODIS bit in the SPORT0 Autobuffer
Control Register.
RESETThe RESET signals initiate a reset of each modem proces-
sor in the ADSP-21mod980N. The RESET signals must be
asserted during the power-up sequence to assure proper ini-
tialization. RESET during initial power-up must be held
long enough to let the internal clocks stabilize. If RESETs
are activated any time after power up, the clocks continue to
run and do not require stabilization time.
The power-up sequence is defined as the total time required
for the oscillator circuits to stabilize after a valid VDD is
applied to the processors, and for the internal phase-locked
loops (PLL) to lock onto the specific frequency. A mini-
mum of 2000 CLKIN cycles ensures that the PLLs have
locked, but this does not include the oscillators’ start-up
time. During this power-up sequence, the RESET signals
should be held low. On any subsequent resets, the RESET
signals must meet the minimum pulse width specification,
tRSP.
The RESET input contains some hysteresis; however, if you
use an RC circuit to generate your RESET signals, the use
of an external Schmidt triggers are recommended.
The RESET for each individual modem processor sets the
internal stack pointers to the empty stack condition, masks
all interrupts and clears the MSTAT register. When a
RESET is released, if there is no pending bus request and
the modem processor is configured for booting, the
boot-loading sequence is performed. The first instruction is
fetched from on-chip program memory location 0x0000
once boot loading completes.
MEMORY ARCHITECTUREThe ADSP-21mod980N provides a variety of memory and
peripheral interface options for Modem Processor 1. The
key functional groups are Program Memory, Data Memory,
Byte Memory, and I/O. Refer to the following figures and
tables for PM and DM memory allocations in the
ADSP-21mod980N.
The ADSP-21mod980N modem pool operates in one
memory mode: Slave Mode. The following figures and
tables describe the memory of the ADSP-21mod980N:Figure on page10 shows Program MemoryTable on page10 shows the generation of address bits
based on the PMOVLAY valuesFigure on page11 shows Data MemoryTable on page11 shows the generation of address bits
based on the DMOVLAY values. Access to external
memory is not available
Figure 4. Program Memory Map
Table 4. PMOVLAY bits
PRELIMINARY TECHNICAL DATA
MEMORY MAPPED REGISTERS (NEW TO THE
ADSP-21MOD980N)The ADSP-21mod980N has three memory mapped regis-
ters that differ from other ADSP-21xx Family DSPs. See
“Waitstate Control Register” on page11. See
“Programmable Flag & Composite Select Control Regis-
ter” on page12. See “System Control Register” on
page12. The slight modifications to these registers provide
the ADSP-21mod980N’s waitstate and BMS control
features.
Figure 5. Data Memory Map
Table 5. DMOVLAY bitsFigure 6. Waitstate Control Register
PRELIMINARY TECHNICAL DATA
SLAVE MODEThis section describes the Slave Mode memory configura-
tion of the Modem Processors.
INTERNAL MEMORY DMA PORT (IDMA PORT)The IDMA Port provides an efficient way for a host system
and the ADSP-21mod980N to communicate. The port is
used to access the on-chip program memory and data mem-
ory of each modem processor with only one processor cycle
Figure 7. Programmable Flag1 & Composite Select Control RegisterSince they are multiplexed within the ADSP-21mod980N, PF[2:0] should be configured as an output for only one processor at a time. Bit [3] of DM
(0x3FE6) must also be 0 to ensure that PF[3] is never an output.
Figure 8. System Control Register
Table 6. ADSP-21mod980N Mode of OperationConsidered standard operating settings. These configurations simplify your design and improve memory management.IDMA timing details and the correct usage of IACK are described in the ADSP-2100 Family User’s Manual.
PRELIMINARY TECHNICAL DATAever, to write to the processor’s memory-mapped control
registers. A typical IDMA transfer process is described as
follows:Host starts IDMA transferHost uses IS and IAL control lines to latch either the
DMA starting address (IDMAA) or the PM/DM
OVLAY selection into the processor’s IDMA control
registers.
If IAD [15] = 1, the value of IAD [7:0] represents the
IDMA overlay: IAD[14:8] must be set to 0.
If IAD [15] = 0, the value of IAD [13:0] represents the
starting address of internal memory to be accessed and
IAD [14] reflects PM or DM for access.Host uses IS and IRD (or IWR) to read (or write) pro-
cessor internal memory (PM or DM).Host ends IDMA transfer.
The IDMA port has a 16-bit multiplexed address and data
bus and supports 24-bit program memory. The IDMA port
is completely asynchronous and can be written to, while the
ADSP-21mod980N is operating at full speed.
The processor memory address is latched and then auto-
matically incremented after each IDMA transaction. An
external device can therefore access a block of sequentially
addressed memory by specifying only the starting address of
the block. This increases throughput as the address does
not have to be sent for each memory access.
IDMA Port access occurs in two phases. The first is the
IDMA Address Latch cycle. When the acknowledge is
asserted, a 14-bit address and 1-bit destination type can be
driven onto the bus by an external device. The address
specifies an on-chip memory location, the destination type
specifies whether it is a DM or PM access. The falling edge
of the address latch signal latches this value into the
IDMAA register.
Once the address is stored, data can then be either read
from, or written to, the ADSP-21mod980N’s on-chip
memory. Asserting the select line (IS) and the appropriate
read or write line (IRD and IWR respectively) signals the
ADSP-21mod980N that a particular transaction is
required. In either case, there is a one-processor-cycle delay
for synchronization. The memory access consumes one
additional processor cycle.
Once an access has occurred, the latched address is auto-
matically incremented, and another access can occur.
Through the IDMAA register, the processor can also spec-
ify the starting address and data format for DMA operation.
Asserting the IDMA port select (IS) and address latch
enable (IAL) directs the ADSP-21mod980N to write the
address onto the IAD [14:0] bus into the IDMA Control
Register. If IAD [15] is set to 0, IDMA latches the address.
If IAD [15] is set to 1, IDMA latches OVLAY memory. The
IDMAA register is memory mapped at address DM
(0x3FE0). Note that the latched address (IDMAA) or over-
lay register cannot be read back by the host. The IDMA
OVERLAY register is memory mapped at address
DM(0x3FE7). See Figure on page13 for more informa-
tion on IDMA memory mapping. When bit 14 in 0x3FE7
is set to 1, then timing in Figure on page35 applies for
short reads. When bit 14 in 0x3FE7 is set to zero short
reads use the timing shown in Figure on page34.
Figure 9. IDMA Control/OVLAY Registers
PRELIMINARY TECHNICAL DATAFigure 10. Direct Memory Access - PM and DM Memory Maps
PRELIMINARY TECHNICAL DATA
IDMA PORT BOOTINGThe ADSP-21mod980N boots programs through its Inter-
nal DMA port.When Mode C = 1, Mode B = 0, and Mode
A = 1, the ADSP-21mod980N boots from the IDMA port.
IDMA feature can load as much on-chip memory as
desired. Program execution is held off until on-chip pro-
gram memory location 0 is written to.
FLAG I/O PINSEach modem processor has eight general purpose program-
mable input/output flag pins. They are controlled by two
memory mapped registers. The PFTYPE register deter-
mines the direction, 1 = output and 0 = input. The
PFDATA register is used to read and write the values on the
pins. Data being read from a pin configured as an input is
synchronized to the ADSP-21mod980N’s clock. Bits that
are programmed as outputs will read the value being out-
put. The PF pins default to input during RESET.
Note: Pins PF0, PF1, and PF2 are also used for device con-
figuration during RESET. Since they are multiplexed
within the ADSP-21mod980N, PF[2:0] should be config-
ured as an output for only one processor at a time.
PRELIMINARY TECHNICAL DATA
DESIGNING AN EZ-ICE-COMPATIBLE SYSTEMThe ADSP-21mod980N has on-chip emulation support
and an ICE-Port, a special set of pins that interface to the
EZ-ICE. These features allow in-circuit emulation without
replacing the target system processor by using only a 14-pin
connection from the target system to the EZ-ICE. Target
systems must have a 14-pin connector to accept the
EZ-ICE’s in-circuit probe, a 14-pin plug.
The EZ-ICE can emulate only one modem processor at a
time. You must include hardware to select which processor
in the ADSP-21mod980N you want to emulate. Figure on
page16 is a functional representation of the modem proces-
sor selection hardware. You can use one ICE-Port
connector with two ADSP-21mod980N processors without
using additional buffers.
Issuing the “chip reset” command during emulation causes
the modem processor to perform a full chip reset, including
mode pins are set correctly PRIOR to issuing a chip reset
command from the emulator user interface. As the mode
Figure 11. Selecting a Modem Processor in the ADSP-21mod980N
PRELIMINARY TECHNICAL DATAADSP-21mod980N, it may be necessary to reset the target
hardware separately to insure the proper mode selection
state on emulator chip reset. See the ADSP-2100 Family
EZ-Tools data sheet for complete information on ICE
products.
The ICE-Port interface consists of the following
ADSP-21mod980N pins:
EBR
EINT
EBG
ECLK
ERESET
ELIN
EMS
ELOUT
These ADSP-21mod980N pins must be connected only to
the EZ-ICE connector in the target system. These pins have
no function except during emulation, and do not require
pull-up or pull-down resistors. The traces for these signals
between the ADSP-21mod980N and the connector must
be kept as short as possible—no longer than 3 inches.
The following pins are also used by the EZ-ICE:BRBGRESETGND
The EZ-ICE uses the EE (emulator enable) signal to take
control of the ADSP-21mod980N in the target system.
This causes the processor to use its ERESET, EBR, and
EBG pins instead of the RESET, BR, and BG pins. The BG
output is three-stated. These signals do not need to be
jumper-isolated in your system.
The EZ-ICE connects to your target system via a ribbon
cable and a 14-pin female plug. The female plug is plugged
onto the 14-pin connector (a pin strip header) on the target
board.
TARGET BOARD CONNECTOR FOR EZ-ICE PROBEThe EZ-ICE connector (a standard pin strip header) is
shown in Figure on page17. You must add this connector
to your target board design if you intend to use the EZ-ICE.
Be sure to allow enough room in your system to fit the
EZ-ICE probe onto the 14-pin connector.
The 14-pin, 2-row pin strip header is keyed at the Pin 7
location—you must remove Pin 7 from the header. The pins
must be 0.025 inch square and at least 0.20 inch in length.
Pin spacing should be 0.1 � 0.1 inches. The pin strip
header must have at least 0.15 inch clearance on all sides to
accept the EZ-ICE probe plug.
Pin strip headers are available from vendors such as 3M,
McKenzie, and Samtec.
TARGET MEMORY INTERFACEFor your target system to be compatible with the EZ-ICE
emulator, it must comply with the memory interface guide-
lines listed below.
TARGET SYSTEM INTERFACE SIGNALS When the EZ-ICE board is installed, the performance on
some system signals change. Design your system to be com-
patible with the following system interface signal changes
introduced by the EZ-ICE board:EZ-ICE emulation introduces an 8 ns propagation
delay between your target circuitry and the processor
on the RESET signal.EZ-ICE emulation introduces an 8 ns propagation
delay between your target circuitry and the processor
on the BR signal.EZ-ICE emulation ignores RESET and BR when
single-stepping.EZ-ICE emulation ignores RESET and BR when in
Emulator Space (processor halted).EZ-ICE emulation ignores the state of target BR in cer-
tain modes. As a result, the target system may take
control of the processor’s external memory bus only if
bus grant (BG) is asserted by the EZ-ICE board’s
processor.
Figure 12. Target Board Connector for EZ-ICE
PRELIMINARY TECHNICAL DATA
ELECTRICAL SPECIFICATIONS
RECOMMENDED OPERATING CONDITIONS
ELECTRICAL CHARACTERISTICS
PRELIMINARY TECHNICAL DATABidirectional pins: RFS0, RFS1, SCLK0, SCLK1, TFS0, TFS1, IAD [15:0], PF[2:0], PF[7:4].Input only pins: RESET, BR, DR0, DR1, IS, IAL,IRD, IWR.Input only pins: CLKIN, RESET, BR, DR0, DR1.Output pins: BG, A0, DT0, DT1, CLKOUT, IACK.Although specified for TTL outputs, all ADSP-21mod980N outputs are CMOS-compatible and will drive to VDDEXT and GND, assuming no DC
loads.Guaranteed but not tested.Three-statable pins: DT0, DT1, SCLK0, SCLK1, TFS0, TFS1, RFS0, RSF1, IAD[15:0].0 Volts on BR.Vin = 0V and 3V. For typical supply current figures refer to “Power Dissipation” section.See the ADSP-2100 Family User’s Manual for details. Output pin capacitance is the capacitive load for any three-stated output pin
ELECTRICAL CHARACTERISTICS (CONTINUED)
PRELIMINARY TECHNICAL DATA
ABSOLUTE MAXIMUM RATINGSApplies to bidirectional pins (D0:D23, RFS0, RFS1, SCLK0, SCLK1, TFS0, TFS1, A1:A13, PF0:PF7) and input only pins (CLKIN, RESET, BR,
DR0, DR1).Applies to output pins (BG, PWDACK, A0, DT0, DT1, CLKOUT).
ESD SENSITIVITYCAUTION: ESD (electrostatic discharge) sensitive device. Electrostatic charges as high
as 4000V readily accumulate on the human body and test equipment and can discharge
without detection. Although the device features proprietary ESD protection circuitry,
permanent damage may occur on devices subjected to high-energy electrostatic dis-
charges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
PRELIMINARY TECHNICAL DATA
POWER DISSIPATIONo determine total power dissipation in a specific applica-
tion, the following equation should be applied for each
output:
C � VDD2 � f
C = load capacitance
f = output switching frequency
Example:
In an application where an external host is accessing inter-
nal memory and no other outputs are active, power
dissipation is calculated as follows:
Assumptions:
Assumptions:External data memory is accessed every fourth cycle
with 50% of the address pins switching.External data memory writes occur every fourth cycle
with 50% of the data pins switching.Each address and data pin has a 64 pF total load at the
pin.Application operates at VDDEXT = 3.3 V and tCK = 30 ns.otal Power Dissipation = PINT + (C �VDDEXT2 � f)
P INT= internal power dissipation from Figure15
(C � VDDEXT2 � f) is calculated for each output, as in the
example in Table7.otal power dissipation for this example is:
PD = PINT + 222.7 mW
Table 7. Example Power Dissipation Calculation222.7
