ADSP-21MOD870-000 ,Internet Gateway Processorspecifications of the EZ-ICE targetThe modem software is available as object code.board connector.D ..
ADSP21MOD870-000 ,Internet Gateway Processoroverview of ADSP-21mod870rect addressing), it is post-modified by the value of one of fourfunctiona ..
ADSP-21MOD870-110 ,16-Bit, First Complete Digital Modem on a Single ChipGENERAL DESCRIPTIONOn-Chip Program Memory RAM and 32K Words On-The ADSP-21mod870 is a single-chip I ..
ADSP-21MOD980N-000 ,MultiPort Internet Gateway Processorapplications, such as cycle time. Every instruction can execute in a single proces-voice-over-IP, a ..
ADSP-21MSP59 ,DSP MicrocomputersOVERVIEWThe two address buses (PMA, DMA) share a single external ad-Figure 1 is an overall block di ..
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AM26C31IDBRG4 ,Quadruple Differential Line Driver 16-SSOP -40 to 85Features 3 DescriptionThe AM26C31 device is a differential line driver with1• Meets or Exceeds the ..
AM26C31IDG4 ,Quadruple Differential Line Driver 16-SOIC -40 to 85Block Diagrams. 103 Description....... 18.3 Feature Description.... 114 Revision History........ 28 ..
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ADSP-21MOD870-000-ADSP21MOD870-000
Internet Gateway Processor
REV.0
Internet Gateway Processor
FUNCTIONAL BLOCK DIAGRAM
FEATURES
PERFORMANCE
Complete Single-Chip Internet Gateway Processor (No
External Memory Required)
Implements V.34/V.90 Data/FAX Modem Including
Controller and Datapump
19 ns Instruction Cycle Time @ 3.3 V, 52 MIPS Sustained
Performance
Open Architecture Platform Extensible to Voice Over IP
and Other Applications
Low Power Dissipation, 80 mW (Typical) for Digital
Modem
Power-Down Mode Featuring Low CMOS Standby
Power Dissipation
INTEGRATION
ADSP-2100 Family Code Compatible, with Instruction
Set Extensions
160K Bytes of On-Chip RAM, Configured as 32K Words
On-Chip Program Memory RAM and 32K Words On-
Chip Data Memory RAM
Dual Purpose Program Memory for Both Instruction
and Data Storage
Independent ALU, Multiplier/Accumulator and Barrel
Shifter Computational Units
Two Independent Data Address Generators
Powerful Program Sequencer Provides Zero Overhead
Looping Conditional Instruction Execution
Programmable 16-Bit Interval Timer with Prescaler
100-Lead LQFP with 0.4 Square Inch (256 mm2) Footprint
SYSTEM INTERFACE
16-Bit Internal DMA Port for High Speed Access to On-
Chip Memory (Mode Selectable)
Two Double-Buffered Serial Ports with Companding
Hardware and Automatic Data Buffering
Programmable Multichannel Serial Port Supports
24/32 Channels
Automatic Booting of On-Chip Program Memory
Through Internal DMA Port
Six External Interrupts
13 Programmable Flag Pins Provide Flexible System
Signaling
ICE-Port™ Emulator Interface Supports Debugging in
Final Systems
GENERAL DESCRIPTIONThe ADSP-21mod870 is a single-chip Internet gateway pro-
cessor optimized for implementation of a complete V.34/56K
modem. All data pump and controller functions can be imple-
mented on a single chip, offering the lowest power consumption
and highest possible modem port density.
The ADSP-21mod870, shown in the Functional Block Dia-
gram, combines the ADSP-2100 family base architecture (three
computational units, data address generators and a program
sequencer) with two serial ports, a 16-bit internal DMA port, a
byte DMA port, a programmable timer, Flag I/O, extensive
interrupt capabilities and on-chip program and data memory.
The ADSP-21mod870 integrates 160K bytes of on-chip
memory configured as 32K words (24-bit) of program RAM,
and 32K words (16-bit) of data RAM. Power-down circuitry is
also provided to meet the low power needs of battery operated
portable equipment. The ADSP-21mod870 is available in
100-lead LQFP package.
Fabricated in a high speed, low power, CMOS process, the
ADSP-21mod870 operates with a 19 ns instruction cycle time.
Every instruction can execute in a single processor cycle.
The ADSP-21mod870’s flexible architecture and comprehen-
sive instruction set allow the processor to perform multiple
operations in parallel. In one processor cycle the ADSP-21mod870
can:Generate the next program addressFetch the next instructionPerform one or two data movesUpdate one or two data address pointersPerform a computational operationICE-Port is a trademark of Analog Devices, Inc.
All other trademarks are the property of their respective holders.
ADSP-21mod870This takes place while the processor continues to:Receive and transmit data through the two serial portsReceive and/or transmit data through the internal DMA portReceive and/or transmit data through the byte DMA portDecrement timer
Modem SoftwareThe modem software executes general modem control, com-
mand sets, error correction and data compression, data modula-
tions (for example, V.90 and V.34), and host interface functions.
The host interface allows system access to modem statistics
such as call progress, connect speed, retrain count, symbol rate
and other modulation parameters.
The modem data pump and controller software reside in on-
chip SRAM and do not require external memory. You can
configure the ADSP-21mod870 dynamically by downloading
software from the host through the 16-bit DMA interface. This
SRAM-based architecture provides a software upgrade path to
future standards and applications, such as voice over IP.
The modem software is available as object code.
DEVELOPMENT SYSTEMThe ADSP-2100 Family Development Software, a complete set
of tools for software and hardware system development, sup-
ports the ADSP-21mod870. The System Builder provides a
high level method for defining the architecture of systems under
development. The Assembler has an algebraic syntax that is
easy to program and debug. The Linker combines object files
into an executable file. The Simulator provides an interactive
instruction-level simulation with a reconfigurable user interface
to display different portions of the hardware environment.
A PROM Splitter generates PROM programmer compatible
files. The C Compiler, based on the Free Software Foundation’s
GNU C Compiler, generates ADSP-21mod870 assembly source
code. The source code debugger allows programs to be cor-
rected in the C environment. The Runtime Library includes
over 100 ANSI-standard mathematical and DSP-specific
functions.
The ADSP-218x EZ-ICE® Emulator aids in the hardware de-
bugging of an ADSP-21mod870 system. The emulator consists
of hardware, host computer resident software, and the target
board connector. The ADSP-21mod870 integrates on-chip
emulation support with a 14-pin ICE-Port interface. This
interface provides a simpler target board connection that
requires fewer mechanical clearance considerations than other
ADSP-2100 Family EZ-ICEs. The ADSP-21mod870 device
need not be removed from the target system when using the EZ-
ICE, nor are any adapters needed. Due to the small footprint of
the EZ-ICE connector, emulation can be supported in final
board designs.
The EZ-ICE performs a full range of functions, including:In-target operationUp to 20 breakpointsSingle-step or full speed operationRegisters and memory values can be examined and alteredPC upload and download functionsInstruction-level emulation of program booting and executionComplete assembly and disassembly of instructionsC source-level debugging
See Designing An EZ-ICE-Compatible Target System in the
ADSP-2100 Family EZ-Tools Manual (ADSP-2181 sections) as
well as the Designing an EZ-ICE Compatible System section of
this data sheet for the exact specifications of the EZ-ICE target
board connector.
ADSP-21mod870 Reference Design/Evaluation KitThe ADSP-21mod870-EV1 is a reference design/evaluation kit
that includes an ISA bus PC card that has an ADSP-21061L
SHARC® processor as a host, four ADSP-21mod870 Internet
gateway processors and a T1 interface. The board is shipped
with an evaluation copy of the modem software and software
that runs on the PC. The PC software provides a user interface
that lets you run a modem session “right out of the box.” When
you run the modem in keyboard mode, characters typed on the
keyboard are transmitted to the other modem and characters
sent by the other modem are displayed on the screen. Data can
also be streamed through the COM port of the PC to send and
receive files and perform automated testing.
The modem system contains four ADSP-21mod870s connected
to an ADSP-21061 SHARC host processor. This design is ex-
tensible to 32 ADSP-21mod870s. The ADSP-21mod870s are
connected to a T1 interface. This accommodates testing with a
digital line. A diagram of the system is shown below in Figure 1.
The SHARC processor communicates to the PC through the
ISA bus. The SHARC acts as the modem system host and con-
trols the ADSP-21mod870-based modems connected to a DMA
bus. The code, written in C, runs on the SHARC and provides
an example of how the host loads code into the ADSP-21mod870s,
DIGITAL
TELCO
ISA
BUS
how data is passed, and how commands and status information
are communicated. You can port this C code to whatever host
processor you are using in your system. The SHARC also
controls an ADSP-2181 connected to the DMA bus. The
ADSP-2181 controls the T1 interface. The PCM serial stream
from the T1 interface is connected to the serial ports of the
ADSP-21mod870s.
A debugger is provided that lets you download code and data to
the SHARC and examine register and memory contents. Moni-
tor software is also included so you can run a modem session
immediately “out of the box” without writing extra layers of
software or adding to the configuration.
Additional InformationThis data sheet provides a general overview of ADSP-21mod870
functionality. For additional information on the architecture
and instruction set of the processor, refer to the ADSP-2100
Family User’s Manual, Third Edition. For more information
about the development tools, refer to the ADSP-2100 Family
Development Tools data sheet.
For more information about the modem software refer to
ADSP-21mod870-100 Modem Software data sheet.
ARCHITECTURE OVERVIEWThe ADSP-21mod870 instruction set provides flexible data moves
and multifunction (one or two data moves with a computation)
instructions. Every instruction can be executed in a single pro-
cessor cycle. The ADSP-21mod870 assembly language uses an
algebraic syntax for ease of coding and readability. A compre-
hensive set of development tools supports program development.
Figure 2.Functional Block Diagram
Figure 2 is an overall block diagram of the ADSP-21mod870.
The processor contains three independent computational units:
the ALU, the multiplier/accumulator (MAC) and the shifter.
The computational units process 16-bit data directly and have
provisions to support multiprecision computations. The ALU
performs a standard set of arithmetic and logic operations;
division primitives are also supported. The MAC performs
single-cycle multiply, multiply/add and multiply/subtract opera-
tions with 40 bits of accumulation. The shifter performs logical
and arithmetic shifts, normalization, denormalization and de-
rive exponent operations.
The internal result (R) bus connects the computational units so
that the output of any unit may be the input of any unit on the
next cycle.
A powerful program sequencer and two dedicated data address
generators ensure efficient delivery of operands to these compu-
tational units. The sequencer supports conditional jumps, sub-
routine calls and returns in a single cycle. With internal loop
counters and loop stacks, the ADSP-21mod870 executes looped
code with zero overhead; no explicit jump instructions are re-
quired to maintain loops.
Two data address generators (DAGs) provide addresses for
simultaneous dual operand fetches (from data memory and
program memory). Each DAG maintains and updates four ad-
dress pointers. Whenever the pointer is used to access data (indi-
rect addressing), it is post-modified by the value of one of four
possible modify registers. A length value may be associated with
each pointer to implement automatic modulo addressing for
circular buffers.
Efficient data transfer is achieved with the use of five internal
buses:Program Memory Address (PMA) BusProgram Memory Data (PMD) BusData Memory Address (DMA) BusData Memory Data (DMD) BusResult (R) Bus
The two address buses (PMA and DMA) share a single external
address bus, allowing memory to be expanded off-chip, and the
two data buses (PMD and DMD) share a single external data
bus. Byte and I/O memory space also share the external buses.
Program memory can store both instructions and data, permit-
ting the ADSP-21mod870 to fetch two operands in a single
cycle, one from program memory and one from data memory.
The ADSP-21mod870 can fetch an operand from program
memory and the next instruction in the same cycle.
In lieu of the address and data bus for external memory connec-
tion, the ADSP-21mod870 may be configured for 16-bit Inter-
nal DMA port (IDMA port) connection to external systems.
The IDMA port is made up of 16 data/address pins and five
control pins. The IDMA port provides transparent, direct ac-
cess to the DSPs on-chip program and data RAM.
An interface to low cost byte-wide memory is provided by the
Byte DMA port (BDMA port). The BDMA port is bidirectional
and can directly address up to four megabytes of external RAM
or ROM for off-chip storage of program overlays or data tables.
The byte memory and I/O memory space interface supports
slow memories and I/O memory-mapped peripherals with pro-
grammable wait state generation. External devices can gain
control of external buses with bus request/grant signals (BR,
BGH, and BG). One execution mode (Go Mode) allows the
ADSP-21mod870 to continue running from on-chip memory.
Normal execution mode requires the processor to halt while
buses are granted.
The ADSP-21mod870 can respond to eleven interrupts. There
can be up to six external interrupts (one edge-sensitive, two
ADSP-21mod870synchronous serial interface with optional companding in hard-
ware and a wide variety of framed or frameless data transmit
and receive modes of operation.
Each port can generate an internal programmable serial clock or
accept an external serial clock.
The ADSP-21mod870 provides up to 13 general-purpose flag
pins. The data input and output pins on SPORT1 can be alter-
natively configured as an input flag and an output flag. In addi-
tion, there are eight flags that are programmable as inputs or
outputs, and three flags that are always outputs.
A programmable interval timer generates periodic interrupts. A
16-bit count register (TCOUNT) decrements every n processor
cycles, where n is a scaling value stored in an 8-bit register
(TSCALE). When the value of the count register reaches zero,
an interrupt is generated and the count register is reloaded from
a 16-bit period register (TPERIOD).
Serial PortsThe ADSP-21mod870 incorporates two complete synchronous
serial ports (SPORT0 and SPORT1) for serial communications
and multiprocessor communication.
Here is a brief list of the capabilities of the ADSP-21mod870
SPORTs. For additional information on Serial Ports, refer to the
ADSP-2100 Family User’s Manual, Third Edition.SPORTs are bidirectional and have a separate, double-
buffered transmit and receive section.SPORTs can use an external serial clock or generate their
own serial clock internally.SPORTs have independent framing for the receive and trans-
mit sections. Sections run in a frameless mode or with frame
synchronization signals internally or externally generated.
Frame sync signals are active high or inverted, with either of
two pulsewidths and timings.SPORTs support serial data word lengths from 3 to 16 bits
and provide optional A-law and m-law companding according
to CCITT recommendation G.711.SPORT receive and transmit sections can generate unique
interrupts on completing a data word transfer.SPORTs can receive and transmit an entire circular buffer of
data with one overhead cycle per data word. An interrupt is
generated after a data buffer transfer.SPORT0 has a multichannel interface to selectively receive
and transmit a 24 or 32 word, time-division multiplexed,
serial bitstream.SPORT1 can be configured to have two external interrupts
(IRQ0 and IRQ1) and the Flag In and Flag Out signals. The
internally generated serial clock may still be used in this
configuration.
PIN DESCRIPTIONSThe ADSP-21mod870 is available in a 100-lead LQFP package.
To maintain maximum functionality and reduce package size
and pin count, some serial port, programmable flag, interrupt,
and external bus pins have dual, multiplexed functionality. The
external bus pins are configured during RESET, while serial
port pins are software configurable during program execution.
Common-Mode PinsNOTESInterrupt/Flag pins retain both functions concurrently. If IMASK is set to enable the
corresponding interrupts, the DSP will vector to the appropriate interrupt vector address
Memory Interface PinsThe ADSP-21mod870 processor can be used in one of two
modes: Full Memory Mode, which allows BDMA operation
with full external overlay memory and I/O capability, or Host
Mode, which allows IDMA operation with limited external
addressing capabilities. The operating mode is determined by
the state of the Mode C pin during RESET and cannot be
changed while the processor is running.
Full Memory Mode Pins (Mode C = 0)
Host Mode Pins (Mode C = 1)In Host Mode, external peripheral addresses can be decoded using the A0,
CMS, PMS, DMS and IOMS signals.
Terminating Unused PinThe following table shows the recommendations for terminating
unused pins.
Pin Terminations
PinIAD12:0
D23:8
D7 or
IWR
D6 or
NOTES
**Hi-Z = High Impedance.
**Determined by MODE D pin:
Mode D = 0 and in host mode: IACK is an active, driven signal and cannot
be “wire ORed.”
Mode D = 1 and in host mode: IACK is an open source and requires an
external pull-down, but multiple IACK pins can be “wire ORed” together.If the CLKOUT pin is not used, turn it OFF.If the Interrupt/Programmable Flag pins are not used, there are two options:
Option 1: When these pins are configured as INPUTS at reset and function
as interrupts and input flag pins, pull the pins High (inactive).
Option 2: Program the unused pins as OUTPUTS, set them to 1, and let
them float.
ADSP-21mod870
InterruptsThe interrupt controller allows the processor to respond to the
eleven possible interrupts and reset with minimum overhead.
The ADSP-21mod870 provides four dedicated external inter-
rupt input pins, IRQ2, IRQL0, IRQL1, and IRQE (shared with
the PF7:4 pins). In addition, SPORT1 may be reconfigured for
IRQ0, IRQ1, FLAG_IN and FLAG_OUT, for a total of six
external interrupts. The ADSP-21mod870 also supports internal
interrupts from the timer, the byte DMA port, the two serial
ports, software and the power-down control circuit. The inter-
rupt levels are internally prioritized and individually maskable
(except power down and reset). The IRQ2, IRQ0 and IRQ1
input pins can be programmed to be either level- or edge-
sensitive. IRQL0 and IRQL1 are level-sensitive and IRQE is
edge-sensitive. The priorities and vector addresses of all inter-
rupts are shown in Table I.
Table I.Interrupt Priority and Interrupt Vector AddressesInterrupt routines can either be nested with higher priority inter-
rupts taking precedence or processed sequentially. Interrupts can
be masked or unmasked with the IMASK register. Individual
interrupt requests are logically ANDed with the bits in IMASK;
the highest priority unmasked interrupt is then selected. The
power-down interrupt is nonmaskable.
The ADSP-21mod870 masks all interrupts for one instruction
cycle following the execution of an instruction that modifies the
IMASK register. This does not affect serial port autobuffering or
DMA transfers.
The interrupt control register, ICNTL, controls interrupt nesting
and defines the IRQ0, IRQ1 and IRQ2 external interrupts to be
either edge- or level-sensitive. The IRQE pin is an external edge
sensitive interrupt and can be forced and cleared. The IRQL0
and IRQL1 pins are external level-sensitive interrupts.
The IFC register is a write-only register used to force and clear
interrupts. On-chip stacks preserve the processor status and are
automatically maintained during interrupt handling. The stacks
are twelve levels deep to allow interrupt, loop, and subroutine
nesting. The following instructions allow global enable or disable
servicing of the interrupts (including power down), regardless of
the state of IMASK. Disabling the interrupts does not affect serial
LOW POWER OPERATIONThe ADSP-21mod870 has three low power modes that signifi-
cantly reduce the power dissipation when the device operates
under standby conditions. These modes are:Power-DownIdleSlow Idle
The CLKOUT pin may also be disabled to reduce external
power dissipation.
Power-DownThe ADSP-21mod870 Internet gateway processor has a low
power feature that lets the processor enter a very low power
dormant state through hardware or software control. Here is a
brief list of power-down features. Refer to the ADSP-2100 Fam-
ily User’s Manual, Third Edition, “System Interface” chapter, for
detailed information about the power-down feature.Quick recovery from power-down. The processor begins
executing instructions in as few as 400 CLKIN cycles.Support for an externally generated TTL or CMOS processor
clock. The external clock can continue running during power-
down without affecting the lowest power rating and 400 CLKIN
cycle recovery.Support for crystal operation includes disabling the oscillator
to save power (the processor automatically waits approxi-
mately 4096 CLKIN cycles for the crystal oscillator to start or
stabilize), and letting the oscillator run to allow 400 CLKIN
cycle startup.Power-down is initiated by either the power-down pin (PWD)
or the software power-down force bit. Interrupt support al-
lows an unlimited number of instructions to be executed
before optionally powering down. The power-down interrupt
also can be used as a nonmaskable, edge-sensitive interrupt.Context clear/save control allows the processor to continue
where it left off or start with a clean context when leaving the
power-down state.The RESET pin also can be used to terminate power-down.Power-down acknowledge pin indicates when the processor
has entered power-down.
IdleWhen the ADSP-21mod870 is in the Idle Mode, the processor
waits indefinitely in a low power state until an interrupt occurs.
When an unmasked interrupt occurs, it is serviced; execution
then continues with the instruction following the IDLE instruc-
tion. In Idle Mode IDMA, BDMA and autobuffer cycle steals
still occur.
Slow IdleThe IDLE instruction is enhanced on the ADSP-21mod870 to
let the processor’s internal clock signal be slowed, further reduc-
ing power consumption. The reduced clock frequency, a pro-
grammable fraction of the normal clock rate, is specified by a
selectable divisor given in the IDLE instruction.
The format of the instruction is
IDLE (n);
ratio. The default form of the instruction, when no clock divisor
is given, is the standard IDLE instruction.
When the IDLE (n) instruction is used, it effectively slows down
the processor’s internal clock and thus its response time to in-
coming interrupts. The one-cycle response time of the standard
idle state is increased by n, the clock divisor. When an enabled
interrupt is received, the ADSP-21mod870 will remain in the idle
state for up to a maximum of n processor cycles (n = 16, 32, 64,
or 128) before resuming normal operation.
When the IDLE (n) instruction is used in systems that have an
externally generated serial clock (SCLK), the serial clock rate
may be faster than the processor’s reduced internal clock rate.
Under these conditions, interrupts must not be generated at a
faster rate than can be serviced, due to the additional time the
processor takes to come out of the idle state (a maximum of n
processor cycles).
SYSTEM INTERFACEFigure 3 shows a typical multichannel modem configuration
with the ADSP-21mod870. A line interface can be used to
connect the multichannel subscriber or client data stream to the
multichannel serial port of the ADSP-21mod870. The ADSP-
21mod870 can support 24 or 32 channels. The IDMA port of
the ADSP-21mod870 is used to give a host processor full access
to the internal memory of the ADSP-21mod870. This lets the
host dynamically configure the ADSP-21mod870 by loading code
and data into its internal memory. This configuration also lets
the host access server data directly from the ADSP-21mod870’s
internal memory. In this configuration, the ADSP-21mod870
should be put into host memory mode where Mode C = 1,
Mode B = 0 and Mode A = 1 (see Table II).
CLOCK SIGNALSThe ADSP-21mod870 can be clocked by either a crystal or a
TTL-compatible clock signal.
The CLKIN input cannot be halted, changed during operation,
or operated below the specified frequency during normal opera-
tion. The only exception is while the processor is in the power-
down state. For additional information, refer to Chapter 9,
ADSP-2100 Family User’s Manual, Third Edition, for detailed
information on this power-down feature.
If an external clock is used, it should be a TTL-compatible
signal running at half the instruction rate. The signal is con-
nected to the processor’s CLKIN input. When an external clock
is used, the XTAL input must be left unconnected.
The ADSP-21mod870 uses an input clock with a frequency
equal to half the instruction rate; a 26 MHz input clock yields a
19 ns processor cycle (which is equivalent to 52 MHz). Nor-
mally, instructions are executed in a single processor cycle. All
device timing is relative to the internal instruction clock rate,
which is indicated by the CLKOUT signal when enabled.
Because the ADSP-21mod870 includes an on-chip oscillator
circuit, an external crystal may be used. The crystal should be
connected across the CLKIN and XTAL pins, with two capaci-
tors connected as shown in Figure 4. Capacitor values are de-
pendent on crystal type and should be specified by the crystal
manufacturer. A parallel-resonant, fundamental frequency,
microprocessor-grade crystal should be used.
A clock output (CLKOUT) signal is generated by the processor
at the processor’s cycle rate. This is enabled and disabled by the
CLKODIS bit in the SPORT0 Autobuffer Control Register.
T1, E1, PRI,
xDSL, ATM
LAN OR
INTERNET
ADSP-21mod870 FUNCTIONSHOST FUNCTIONS
• MULTI-DSP CONTROL AND OVERLAY
MANAGEMENT
• SERVICE 32 DSPs/HOST
• DATA PACKETIZING
• V.34/56k MODEM
• V.17 FAX
• V.42, V.42bis, MNP2-5
DTMF DIALING
HDLC PROTOCOL
CALLER IDFigure 3.Network Access System
ADSP-21mod870
ResetThe RESET signal initiates a master reset of the ADSP-
21mod870. The RESET signal must be asserted during the
power-up sequence to assure proper initialization. RESET
during initial power-up must be held long enough to allow the
internal clock to stabilize. If RESET is activated any time after
power-up, the clock continues to run and does not require
stabilization time.
The power-up sequence is defined as the total time required for
the crystal oscillator circuit to stabilize after a valid VDD is ap-
plied to the processor, and for the internal phase-locked loop
(PLL) to lock onto the specific crystal frequency. A minimum
of 2000 CLKIN cycles ensures that the PLL has locked but
does not include the crystal oscillator start-up time. During
this power-up sequence the RESET signal should be held low.
On any subsequent resets, the RESET signal must meet the
minimum pulsewidth specification, tRSP.
The RESET input contains some hysteresis; however, if you use
an RC circuit to generate your RESET signal, the use of an
external Schmidt trigger is recommended.
The master reset sets all internal stack pointers to the empty
stack condition, masks all interrupts and clears the MSTAT
register. When RESET is released, if there is no pending bus
request and the chip is configured for booting, the boot-loading
sequence is performed. The first instruction is fetched from
on-chip program memory location 0x0000 once boot loading
completes.
Table II.Modes of Operation1NOTESAll mode pins are recognized while RESET is active (low).When Mode D = 0 and in host mode, IACK is an active, driven signal and cannot be “wire ORed.”
MODES OF OPERATIONTable II summarizes the ADSP-21mod870 memory modes.
Setting Memory ModeThe ADSP-21mod870 uses the Mode C pin to make a Memory
Mode selection during chip reset. This pin is multiplexed with
the processor’s PF2 pin, so exercise care when selecting a mode.
The two methods for selecting the value of Mode C are active
and passive.
Passive configuration uses a pull-up or pull-down resistorconnected to the Mode C pin. To minimize power consump-
tion, or if the PF2 pin is used as an output in the DSP applica-
tion, use a weak pull-up or pull-down, on the order of 100 kW.
This value should be sufficient to pull the pin to the desired
level and still let the pin operate as a programmable flag output
without undue strain on the processor’s output driver. For mini-
mum power consumption during power-down, reconfigure PF2
as an input, as the pull-up or pull-down will hold the pin in a
known state, and will not switch.
Active configuration uses a three-statable external driver con-nected to the Mode C pin. A driver’s output enable should be
connected to the processor’s RESET signal so it only drives the
PF2 pin when RESET is active (low). When RESET is de-as-
serted, the driver should three-state, allowing the PF2 pin to be
an input or output. To minimize power consumption during
power-down, configure the programmable flag as an output when
connected to a three-stated buffer. This ensures that the pin is
Program Memory (Full Memory Mode) is a 24-bit space forstoring both instruction op codes and data. The ADSP-21mod870
has 32K words of Program Memory RAM on chip, and the
capability of accessing up to two 8K external memory overlay
spaces using the external data bus.
Table III.PMOVLAY Bits
Data MemoryThe Data Memory map is shown in Figure 6.
held at a constant level and will not oscillate if the three-state
driver’s level hovers around the logic switching point.
MEMORY ARCHITECTUREThe ADSP-21mod870 provides a variety of memory and pe-
ripheral interface options. The key functional groups are Pro-
gram Memory, Data Memory, Byte Memory and I/O. Refer to
the following figures and tables for PM and DM memory alloca-
tions in the ADSP-21mod870.
Program MemoryThe Program Memory map is shown in Figure 5.
PROGRAM MEMORY
MODE B = 1ADDRESS
PROGRAM MEMORY
MODE B = 0ADDRESS
INTERNAL
MEMORY
EXTERNAL
MEMORY
0x2000–
0x3FFF2
PM MODE B=0INTERNAL
MEMORY
EXTERNAL
MEMORY
PM (MODE B=1)1
1WHEN MODE = 1, PMOVLAY MUST BE SET TO 0
2SEE TABLE III FOR PMOVLAY BITSFigure 5.Program Memory
Program Memory (Host Mode) allows access to all internalmemory. External overlay access is limited by a single external
address line (A0). External program execution is not available in
host mode due to a restricted data bus that is 16 bits wide only.
The PMOVLAY bits are defined in Table III.
ADSP-21mod870
Data Memory (Full Memory Mode) is a 16-bit-wide spaceused for the storage of data variables and for memory-mapped
control registers. The ADSP-21mod870 has 32K words on Data
Memory RAM on chip, consisting of 16,352 user-accessible
locations and 32 memory-mapped registers. Support also exists
for up to two 8K external memory overlay spaces through the
external data bus. All internal accesses complete in one cycle.
Accesses to external memory are timed using the wait states
specified by the DWAIT register.
Data Memory (Host Mode) allows access to all internalmemory. External overlay access is limited by a single external
address line (A0). The DMOVLAY bits are defined in Table IV.
Table IV.DMOVLAY Bits
I/O Space (Full Memory Mode)The ADSP-21mod870 supports an additional external memory
space called I/O space. This space is designed to support simple
connections to peripherals (such as data converters and external
registers) or to bus interface ASIC data registers. I/O space
supports 2048 locations of 16-bit-wide data. The lower eleven
bits of the external address bus are used; the upper 3 bits are
undefined. Two instructions were added to the core ADSP-2100
Family instruction set to read from and write to I/O memory
space. The I/O space also has four dedicated three-bit wait state
registers, IOWAIT0-3, which specify up to seven wait states to
be automatically generated for each of four regions. The wait
states act on address ranges as shown in Table V.
Table V.Wait States
Composite Memory Select (CMS)The ADSP-21mod870 has a programmable memory select
signal that is useful for generating memory select signals for
memories mapped to more than one space. The CMS signal is
generated to have the same timing as each of the individual
memory select signals (PMS, DMS, BMS, IOMS) but can com-
bine their functionality.
Each bit in the CMSSEL register, when set, causes the CMS
signal to be asserted when the selected memory select is as-
serted. For example, to use a 32K word memory to act as both
program and data memory, set the PMS and DMS bits in the
The CMS pin functions like the other memory select signals with
the same timing and bus request logic. A 1 in the enable bit
causes the assertion of the CMS signal at the same time as the
selected memory select signal. All enable bits default to 1 at reset,
except BMS.
Boot Memory Select (BMS) DisableThe ADSP-21mod870 lets you boot the processor from one
external memory space while using a different external memory
space for BDMA transfers during normal operation. You can
use the CMS to select the first external memory space for
BDMA transfers and BMS to select the second external space
for booting. The BMS signal can be disabled by setting Bit 3 of
the system control register to 1. The system control register is
illustrated in Figure 7.
Figure 7.System Control Register
Byte MemoryThe byte memory space is a bidirectional, 8-bit-wide, external
memory space used to store programs and data. Byte memory is
accessed using the BDMA feature. The byte memory space
consists of 256 pages, each of which is 16K · 8.
The byte memory space on the ADSP-21mod870 supports read
and write operations as well as four different data formats. The
byte memory uses data bits 15:8 for data. The byte memory uses
data bits 23:16 and address bits 13:0 to create a 22-bit address.
This allows up to a 4 meg · 8 (32 megabit) ROM or RAM to be
used without glue logic. All byte memory accesses are timed by
the BMWAIT register.
Byte Memory DMA (BDMA, Full Memory Mode)The byte memory DMA controller allows loading and storing of
program instructions and data using the byte memory space.
The BDMA circuit is able to access the byte memory space
while the processor is operating normally and steals only one
processor cycle per 8-, 16- or 24-bit word transferred.
Figure 8.BDMA Control Register
The BDMA circuit supports four different data formats which
are selected by the BTYPE register field. The appropriate num-
ber of 8-bit accesses are done from the byte memory space to
build the word size selected. Table VI shows the data formats
Unused bits in the 8-bit data memory formats are filled with 0s.
The BIAD register field is used to specify the starting address
for the on-chip memory involved with the transfer. The 14-bit
BEAD register specifies the starting address for the external byte
memory space. The 8-bit BMPAGE register specifies the start-
ing page for the external byte memory space. The BDIR register
field selects the direction of the transfer. Finally the, 14-bit
BWCOUNT register specifies the number of DSP words to
transfer and initiates the BDMA circuit transfers.
Table VI.Data FormatsBDMA accesses can cross page boundaries during sequential
addressing. A BDMA interrupt is generated on the completion
of the number of transfers specified by the BWCOUNT register.
The BWCOUNT register is updated after each transfer so it can
be used to check the status of the transfers. When it reaches zero,
the transfers have finished and a BDMA interrupt is generated.
The BMPAGE and BEAD registers must not be accessed by the
processor during BDMA operations.
The source or destination of a BDMA transfer will always be
on-chip program or data memory.
When the BWCOUNT register is written with a nonzero value,
the BDMA circuit starts executing byte memory accesses with
wait states set by BMWAIT. These accesses continue until the
count reaches zero. When enough accesses have occurred to
create a destination word, it is transferred to or from on-chip
memory. The transfer takes one processor cycle. Processor
accesses to external memory have priority over BDMA byte
memory accesses.
The BDMA Context Reset bit (BCR) controls whether the
processor is held off while the BDMA accesses are occurring.
Setting the BCR bit to 0 allows the processor to continue opera-
tions. Setting the BCR bit to 1 causes the processor to stop
execution while the BDMA accesses are occurring, to clear the
context of the processor, and start execution at address 0 when
the BDMA accesses have completed. The BDMA overlay bits
specify the OVLAY memory blocks to be accessed for internal
memory.
Internal Memory DMA Port (IDMA Port; Host Memory
Mode)The IDMA Port provides an efficient means of communication
between a host system and the ADSP-21mod870. The port is
used to access the on-chip program memory and data memory
of the processor with only one processor cycle per word over-
head. The IDMA port cannot be used, however, to write to the
processor’s memory-mapped control registers. A typical IDMA
transfer process is described as follows:Host starts IDMA transfer.Host checks IACK control line to see if the processor is busy.Host uses IS and IAL control lines to latch either the DMA
starting address (IDMAA) or the PM/DM OVLAY selection
into the processor’s IDMA control registers.
If IAD[15] = 1, the value of IAD[7:0] represents the IDMA
overlay: Bits 14:8 must be set to 0.
If IAD[15] = 0, the value of IAD[13:0] represents the start-
ing address of internal memory to be accessed and IAD[14]
reflects PM or DM for access.Host uses IS and IRD (or IWR) to read (or write) processor
internal memory (PM or DM).Host checks IACK line to see if the processor has completed
the previous IDMA operation.Host ends IDMA transfer.
The IDMA port has a 16-bit multiplexed address and data bus
and supports 24-bit program memory. The IDMA port is com-
pletely asynchronous and can be written to while the ADSP-
21mod870 is operating at full speed.
The processor memory address is latched and is then automati-
cally incremented after each IDMA transaction. An external
device can therefore access a block of sequentially addressed
memory by specifying only the starting address of the block.
This increases throughput as the address does not have to be
sent for each memory access.
IDMA Port access occurs in two phases. The first is the IDMA
Address Latch cycle. When the acknowledge is asserted, a 14-bit
address and 1-bit destination type can be driven onto the bus by
an external device. The address specifies an on-chip memory
location; the destination type specifies whether it is a DM or
PM access. The falling edge of the address latch signal latches
this value into the IDMAA register.
Once the address is stored, data can then be either read from, or
written to, the ADSP-21mod870’s on-chip memory. Asserting
the select line (IS) and the appropriate read or write line (IRD
and IWR respectively) signals the ADSP-21mod870 that a par-
ticular transaction is required. In either case, there is a one-
processor-cycle delay for synchronization. The memory access
consumes one additional processor cycle.
Once an access has occurred, the latched address is automati-
cally incremented, and another access can occur.
Through the IDMAA register, the processor can also specify the
starting address and data format for DMA operation. Asserting
the IDMA port select (IS) and address latch enable (IAL)
directs the ADSP-21mod870 to write the address onto the
IAD[14:0] bus into the IDMA Control Register. If IAD[15]
is set to 0, IDMA latches the address. If IAD[15] is set to 1,
IDMA latches OVLAY memory. This register, shown below, is
memory mapped at address DM (0x3FE0). Note that the latched
address (IDMAA) cannot be read back by the host.
ADSP-21mod870Figure 9 shows the IDMA Control and OVLAY Registers, Fig-
ure 10 shows the bus usage during IDMA transfers, and Figure
11 shows the DMA memory maps.
Figure 9.IDMA Control/OVLAY Registers
(IAD 15–0)
1 = DM14131211109876543210
PAGE
LATCHADDRESS
LATCH
PAGE AND ADDRESS LATCH
(IAD 15–0)14131211109876543210
DM 16-BIT
IDMA DATA WRITE/INPUTPM 24-BIT
1ST
TRANSFER
2ND
TRANSFER
(IAD 15–0)14131211109876543210
DM 16-BIT
IDMA DATA READ/OUTPUTPM 24-BIT
1ST
TRANSFER
2ND
TRANSFERFigure 10.Bus Usage During IDMA Transfers
Bootstrap Loading (Booting)The ADSP-21mod870 has two mechanisms to allow automatic
loading of the internal program memory after reset. The method
for booting is controlled by the Mode A, B and C configuration
bits.
When the MODE pins specify BDMA booting, the ADSP-
21mod870 initiates a BDMA boot sequence when reset is
released.
The BDMA interface is set up during reset to the following
defaults when BDMA booting is specified: the BDIR, BMPAGE,
BIAD and BEAD registers are set to 0, the BTYPE register is
set to 0 to specify program memory 24-bit words, and the
BWCOUNT register is set to 32. This causes 32 words of on-
chip program memory to be loaded from byte memory. These
32 words are used to set up the BDMA to load in the remaining
program code. The BCR bit is also set to 1, which causes pro-
gram execution to be held off until all 32 words are loaded into
on-chip program memory. Execution then begins at Address 0.
The ADSP-2100 Family development software (Revision 5.02
and later) fully supports the BDMA booting feature and can
generate boot code compatible with byte memory space.
The IDLE instruction can also be used to allow the processor to
hold off execution while booting continues through the BDMA
interface. For BDMA accesses while in Host Mode, the ad-
dresses to boot memory must be constructed externally to the
ADSP-21mod870. The only memory address bit provided by
the processor is A0.
IDMA Port BootingThe ADSP-21mod870 can also boot programs through its In-
ternal DMA port. If Mode C = 1, Mode B = 0, and Mode A =
1, the ADSP-21mod870 boots from the IDMA port. IDMA
feature can load as much on-chip memory as desired. Program
execution is held off until data is written to on-chip program
memory location 0.
Bus Request and Bus GrantThe ADSP-21mod870 can relinquish control of the data and
address buses to an external device. When the external device
requires access to memory, it asserts the bus request (BR)
signal. If the ADSP-21mod870 is not performing an external
memory access, it responds to the active BR input in the follow-
ing processor cycle by:Three-stating the data and address buses and the PMS,
DMS, BMS, CMS, IOMS, RD, WR output drivers,Asserting the bus grant (BG) signal andHalting program execution.
If Go Mode is enabled, the ADSP-21mod870 will not halt pro-
gram execution until it encounters an instruction that requires an
external memory access.
If the ADSP-21mod870 is performing an external memory access
when the external device asserts the BR signal, it will not three-
state the memory interfaces or assert the BG signal until the
processor cycle after the access completes. The instruction does
not need to be completed when the bus is granted. If a single
instruction requires two external memory accesses, the bus will
When the BR signal is released, the processor releases the BG
signal, reenables the output drivers and continues program
execution from the point at which it stopped.
The bus request feature operates at all times, including when the
processor is booting and when RESET is active.
The BGH pin is asserted when the ADSP-21mod870 is ready to
execute an instruction but is stopped because the external bus is
already granted to another device. The other device can release
the bus by deasserting bus request. Once the bus is released, the
ADSP-21mod870 deasserts BG and BGH and executes the
external memory access.
Flag I/O PinsThe ADSP-21mod870 has eight general purpose programmable
input/output flag pins. They are controlled by two memory map-
ped registers. The PFTYPE register determines the direction,
1 = output and 0 = input. The PFDATA register is used to read
and write the values on the pins. Data being read from a pin
configured as an input is synchronized to the ADSP-21mod870’s
clock. Bits that are programmed as outputs will read the value
being output. The PF pins default to input during reset.
In addition to the programmable flags, the ADSP-21mod870
has five fixed-mode flags, FLAG_IN, FLAG_OUT, FL0, FL1,
and FL2. FL0-FL2 are dedicated output flags. FLAG_IN and
FLAG_OUT are available as an alternate configuration of
SPORT1.
Note: Pins PF0, PF1, PF2 and PF3 are also used for device
configuration during reset.
Instruction Set DescriptionThe ADSP-21mod870 assembly language instruction set has an
algebraic syntax that was designed for ease of coding and read-
ability. The assembly language, which takes full advantage of
the processor’s unique architecture, offers the following ben-
efits:The algebraic syntax eliminates the need to remember cryptic
assembler mnemonics. For example, a typical arithmetic add
instruction, such as AR = AX0 + AY0, resembles a simple
equation.Every instruction assembles into a single, 24-bit word that can
execute in a single instruction cycle.The syntax is a superset ADSP-2100 Family assembly lan-
guage and is completely source and object code compatible
with other family members. Programs may need to be relo-
cated to utilize on-chip memory and conform to the ADSP-
21mod870’s interrupt vector and reset vector map.Sixteen condition codes are available. For conditional jump,
call, return or arithmetic instructions, the condition can be
checked and the operation executed in the same instruction
cycle.Multifunction instructions allow parallel execution of an
arithmetic instruction with up to two fetches or one write to
processor memory space during a single instruction cycle.
DESIGNING AN EZ-ICE-COMPATIBLE SYSTEMThe ADSP-21mod870 has on-chip emulation support and an
the target system to the EZ-ICE. Target systems must have a
14-pin connector to accept the EZ-ICE’s in-circuit probe, a 14-
pin plug. See the ADSP-2100 Family EZ-Tools data sheet for
complete information on ICE products.
Issuing the “chip reset” command during emulation causes the
DSP processor to perform a full chip reset, including a reset of its
memory mode. Therefore, it is vital that the mode pins are set
correctly PRIOR to issuing a chip reset command from the emu-
lator user interface. As the mode pins share functionality with
PF0:2 (and PF3 on the ADSP-21mod870), it may be necessary
to reset the target hardware separately to insure the proper mode
selection state on emulator chip reset.
If you are using a passive method of maintaining mode informa-
tion (as discussed in the Setting Memory Modes section), it
does not matter that mode information is latched by an emula-
tor reset. However, if you are using the RESET pin as a method
of setting the value of the mode pins, then you must consider
the effects of an emulator reset.
One method of ensuring that the values located on the mode
pins is correct is to construct a circuit like the one shown below.
This circuit will force the value located on the mode A pin
to zero, regardless of whether it latched via the RESET or
ERESET pin.
Figure 12.RESET, ERESET Circuit
See the ADSP-2100 Family EZ-Tools data sheet for complete
information on ICE products.
The ICE-Port interface consists of the following ADSP-21mod870
pins:
EBREMSELIN
EBGEINTELOUT
ERESETECLKEE
These ADSP-21mod870 pins must be connected only to the EZ-
ICE connector in the target system. These pins have no function
except during emulation, and do not require pull-up or pull-
down resistors. The traces for these signals between the ADSP-
21mod870 and the connector must be kept as short as possible,
no longer that three inches.
The following pins are also used by the EZ-ICE:RESETGND
The EZ-ICE uses the EE (emulator enable) signal to take control
of the ADSP-21mod870 in the target system. This causes the
processor to use its ERESET, EBR and EBG pins instead of the
ADSP-21mod870The EZ-ICE connects to your target system via a ribbon cable
and a 14-pin female plug. The ribbon cable is ten inches long
with one end fixed to the EZ-ICE. The female plug is plugged
onto the 14-pin connector (a pin strip header) on the target
board.
Target Board Connector for EZ-ICE ProbeThe EZ-ICE connector (a standard pin strip header) is shown in
Figure 13. You must add this connector to your target board
design if you intend to use the EZ-ICE. Be sure to allow enough
room in your system to fit the EZ-ICE probe onto the 14-pin
connector.
The 14-pin, 2-row pin strip header is keyed at the Pin 7 loca-
tion—you must remove Pin 7 from the header. The pins must be
0.025 inch square and at least 0.20 inch in length. Pin spacing
should be 0.1 · 0.1 inches. The pin strip header must have at
least 0.15 inch clearance on all sides to accept the EZ-ICE probe
plug.
Pin strip headers are available from vendors such as 3M,
McKenzie and Samtec.
Target Memory InterfaceFor your target system to be compatible with the EZ-ICE emu-
lator, it must comply with the memory interface guidelines listed
below.
Figure 13.Target Board Connector for EZ-ICE
PM, DM, BM, IOM and CMDesign your Program Memory (PM), Data Memory (DM), Byte
Memory (BM), I/O Memory (IOM), and Composite Memory
(CM) external interfaces to comply with worst case device tim-
ing requirements and switching characteristics as specified in
this data sheet. The performance of the EZ-ICE may approach
published worst case specification for some memory access
timing requirements and switching characteristics.
Note: If your target does not meet the worst case chip specifica-
tion for memory access parameters, you may not be able to
emulate your circuitry at the desired CLKIN frequency. De-
pending on the severity of the specification violation, you may
have trouble manufacturing your system as processor compo-
nents statistically vary in switching characteristic and timing
requirements within published limits.
Restriction: All memory strobe signals on the ADSP-21mod870
(RD, WR, PMS, DMS, BMS, CMS and IOMS) used in your
target system must have 10 kW pull-up resistors connected when
the EZ-ICE is being used. The pull-up resistors are necessary
because there are no internal pull-ups to guarantee their state
during prolonged three-state conditions resulting from typical
EZ-ICE debugging sessions. These resistors may be removed at
your option when the EZ-ICE is not being used.
Target System Interface SignalsWhen the EZ-ICE board is installed, the performance on some
system signals changes. Design your system to be compatible
with the following system interface signal changes introduced by
the EZ-ICE board:EZ-ICE emulation introduces an 8 ns propagation delay
between your target circuitry and the processor on the
RESET signal.EZ-ICE emulation introduces an 8 ns propagation delay
between your target circuitry and the processor on the BR
signal.EZ-ICE emulation ignores RESET and BR when single-
stepping.EZ-ICE emulation ignores RESET and BR when in Emulator
Space (processor halted).EZ-ICE emulation ignores the state of target BR in certain
modes. As a result, the target system may take control of the
processor’s external memory bus only if bus grant (BG) is
asserted by the EZ-ICE board’s processor.
ADSP-21mod870
RECOMMENDED OPERATING CONDITIONS
ELECTRICAL CHARACTERISTICSIIH
IIL
IOZL
IDD
IDD
NOTESBidirectional pins: D0-D23, RFS0, RFS1, SCLK0, SCLK1, TFS0, TFS1, A1–A13, PF0–PF7.Input only pins: RESET, BR, DR0, DR1, PWD.Input only pins: CLKIN, RESET, BR, DR0, DR1, PWD.Output pins: BG, PMS, DMS, BMS, IOMS, CMS, RD, WR, PWDACK, A0, DT0, DT1, CLKOUT, FL2-0, BGH.Although specified for TTL outputs, all ADSP-21mod870 outputs are CMOS-compatible and will drive to VDD and GND, assuming no dc loads.6Guaranteed but not tested.Three-statable pins: A0–A13, D0–D23, PMS, DMS, BMS, IOMS, CMS, RD, WR, DT0, DT1, SCLK0, SCLK1, TFS0, TFS1, RFS0, RSF1, PF0–PF7.0 V on BR.Idle refers to ADSP-21mod870 state of operation during execution of IDLE instruction. Deasserted pins are driven to either VDD or GND.VIN = 0 V and 3 V. For typical figures for supply currents, refer to Power Dissipation section.IDD measurement taken with all instructions executing from internal memory. 50% of the instructions are multifunction (types 1, 4, 5, 12, 13, 14), 30% are type 2
and type 6, and 20% are idle instructions.Applies to LQFP package type.Output pin capacitance is the capacitive load for any three-stated output pin.
SPECIFICATIONS
ADSP-21mod870
ESD SENSITIVITYThe ADSP-21mod870 is an ESD (electrostatic discharge) sensitive device. Electrostatic charges
readily accumulate on the human body and equipment and can discharge without detection.
Permanent damage may occur to devices subjected to high energy electrostatic discharges.
The ADSP-21mod870 features proprietary ESD protection circuitry to dissipate high energy
discharges (Human Body Model) per method 3015 of MIL-STD-883. Proper ESD precautions are
recommended to avoid performance degradation or loss of functionality. Unused devices must be
stored in conductive foam or shunts, and the foam should be discharged to the destination before
devices are removed.
ABSOLUTE MAXIMUM RATINGS*Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +4.6 V
Input Voltage . . . . . . . . . . . . . . . . . . . . –0.5 V to VDD + 0.5 V
Output Voltage Swing . . . . . . . . . . . . . –0.5 V to VDD + 0.5 V
Operating Temperature Range (Ambient) . . –40°C to +85°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Lead Temperature (5 sec) LQFP . . . . . . . . . . . . . . . . +280°C
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. These are stress ratings only; functional operation of
the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
TIMING PARAMETERS
GENERAL NOTESUse the exact timing information given. Do not attempt to
derive parameters from the addition or subtraction of others.
While addition or subtraction would yield meaningful results for
an individual device, the values given in this data sheet reflect
statistical variations and worst cases. Consequently, you cannot
meaningfully add up parameters to derive longer times.
TIMING NOTESSwitching characteristics specify how the processor changes its
signals. You have no control over this timing—circuitry external
to the processor must be designed for compatibility with these
signal characteristics. Switching characteristics tell you what the
processor will do in a given circumstance. You can also use
switching characteristics to ensure that any timing requirement
of a device connected to the processor (such as memory) is
satisfied.
Timing requirements apply to signals that are controlled by
circuitry external to the processor, such as the data input for a
read operation. Timing requirements guarantee that the proces-
sor operates correctly with other devices.
MEMORY TIMING SPECIFICATIONSThe table below shows common memory device specifications
and the corresponding ADSP-21mod870 timing parameter.
Note: xMS = PMS, DMS, BMS, CMS, IOMS.
FREQUENCY DEPENDENCY FOR TIMING
SPECIFICATIONStCK is defined as 0.5 tCKI. The ADSP-21mod870 uses an input
clock with a frequency equal to half the instruction rate: a
26 MHz input clock (which is equivalent to 38 ns) yields a 19 ns
processor cycle (equivalent to 52 MHz). tCK values within the
range of 0.5 tCKI period should be substituted for all relevant tim-
ing parameters to obtain the specification value.
Example: tCKH = 0.5 tCK – 7 ns = 0.5 (19 ns) – 7 ns = 2.5 ns
ENVIRONMENTAL CONDITIONSAmbient Temperature Rating:
TAMB=TCASE – (PD · qCA)
TCASE=Case Temperature in °C=Power Dissipation in WCA=Thermal Resistance (Case-to-Ambient)JA=Thermal Resistance (Junction-to-Ambient)JC=Thermal Resistance (Junction-to-Case)
