ADSP-2191MBST-140 ,DSP MicrocomputerGENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . .3Memory RAM and 32K Words 16-Bit Memor ..
ADSP-2191MBST-140 ,DSP MicrocomputerGENERAL DESCRIPTIONuses an algebraic syntax for ease of coding and readability. A The ADSP-2191M DS ..
ADSP-2191MBST-140 ,DSP MicrocomputerFEATURESPower Supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11Host Port with D ..
ADSP-2191MKCA-160 ,DSP MicrocomputerSPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . 18Two SPI-Compatible Ports with ..
ADSP-2191MKST-160 ,DSP MicrocomputerSPECIFICATIONS . . . . . . . . . . . . . . . . .20Three Programmable Interval Timers with PWM Outp ..
ADSP-2195MKCA-160 ,160MHz; on-chip SRAM: 1.3M bit; DSP microcomputerFEATURES Independent ALU, Multiplier/Accumulator, and Barrel 6.25 ns Instruction Cycle Time (Intern ..
AM26C31CD ,Quadruple Differential Line DriverFeatures section and added the Applications section, the Device Information table, ESD Ratings tabl ..
AM26C31CDB , QUADRUPLE DIFFERENTIAL LINE DRIVERS
AM26C31CDBR ,Quadruple Differential Line DriverElectrical Characteristics: AM26C31Q and12 Device and Documentation Support........ 15AM26C31M. 612 ..
AM26C31CDBRG4 ,Quadruple Differential Line Driver 16-SSOP 0 to 70Features 3 DescriptionThe AM26C31 device is a differential line driver with1• Meets or Exceeds the ..
AM26C31CDG4 ,Quadruple Differential Line Driver 16-SOIC 0 to 70Block Diagrams. 103 Description....... 18.3 Feature Description.... 114 Revision History........ 28 ..
AM26C31CDR ,Quadruple Differential Line DriverMaximum Ratings . 49.2 Typical Application .... 126.2 ESD Ratings........ 410 Power Supply Recommen ..
ADSP-2191MBST-140-ADSP-2191MKCA-160-ADSP-2191MKST-160
DSP Microcomputer
DSP MicrocomputerREV. 0
PERFORMANCE FEATURES
6.25ns Instruction Cycle Time, for up to 160MIPS
Sustained Performance
ADSP-218x Family Code Compatible with the Same
Easy to Use Algebraic Syntax
Single-Cycle Instruction Execution
Single-Cycle Context Switch between Two Sets of Com-
putation and Memory Instructions
Instruction Cache Allows Dual Operand Fetches in Every
Instruction Cycle
Multifunction Instructions
Pipelined Architecture Supports Efficient Code
Execution
Architectural Enhancements for Compiled C and C++
CodeEfficiency
Architectural Enhancements beyond ADSP-218x Family
are Supported with Instruction Set Extensions for
Added Registers, and Peripherals
Flexible Power Management with User-Selectable
Power-Down and Idle Modes
FUNCTIONAL BLOCK DIAGRAM
ADSP-2191M
INTEGRATION FEATURES
160 K Bytes On-Chip RAM Configured as 32K Words 24-Bit
Memory RAM and 32K Words 16-Bit Memory RAM
Dual-Purpose 24-Bit Memory for Both Instruction and
Data Storage
Independent ALU, Multiplier/Accumulator, and Barrel
Shifter Computational Units with Dual 40-bit
Accumulators
Unified Memory Space Allows Flexible Address Genera-
tion, Using Two Independent DAG Units
Powerful Program Sequencer Provides Zero-Overhead
Looping and Conditional Instruction Execution
Enhanced Interrupt Controller Enables Programming of
Interrupt Priorities and Nesting Modes
SYSTEM INTERFACE FEATURES
Host Port with DMA Capability for Glueless 8- or 16-Bit
Host Interface
16-Bit External Memory Interface for up to 16M Words of
Addressable Memory Space
Three Full-Duplex Multichannel Serial Ports, with
Support for H.100 and up to 128 TDM Channels with
A-Law and �-Law Companding Optimized for Telecom-
munications Systems
Two SPI-Compatible Ports with DMA Support
UART Port with DMA Support
16 General-Purpose I/O Pins with Integrated Inter-
rupt Support
Three Programmable Interval Timers with PWM
Generation, PWM Capture/Pulsewidth Measurement,
and External Event Counter Capabilities
Up to 11 DMA Channels Can Be Active at Any Given Time
for High I/O Throughput
On-Chip Boot ROM for Automatic Booting from External
8- or 16-Bit Host Device, SPI ROM, or UART with
Autobaud Detection
Programmable PLL Supports 1� to 32� Input Frequency
Multiplication and Can Be Altered during Runtime
IEEE JTAG Standard 1149.1 Test Access Port Supports
On-Chip Emulation and System Debugging
2.5V Internal Operation and 3.3V I/O
144-Lead LQFP and 144-Ball Mini-BGA Packages
TABLE OF CONTENTSGENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . .3
DSP Core Architecture . . . . . . . . . . . . . . . . . . . . . . . .3
DSP Peripherals Architecture . . . . . . . . . . . . . . . . . . .4
Memory Architecture . . . . . . . . . . . . . . . . . . . . . . . . .5
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
DMA Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Host Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
DSP Serial Ports (SPORTs) . . . . . . . . . . . . . . . . . . . .9
Serial Peripheral Interface (SPI) Ports . . . . . . . . . . . . .9
UART Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Programmable Flag (PFx) Pins . . . . . . . . . . . . . . . . .10
Low Power Operation . . . . . . . . . . . . . . . . . . . . . . . .10
Clock Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Power Supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Booting Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Bus Request and Bus Grant . . . . . . . . . . . . . . . . . . .12
Instruction Set Description . . . . . . . . . . . . . . . . . . . .13
Development Tools . . . . . . . . . . . . . . . . . . . . . . . . . .13
Additional Information . . . . . . . . . . . . . . . . . . . . . . .15
PIN FUNCTION DESCRIPTIONS . . . . . . . . . . . . . .15
SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . 18
ABSOLUTE MAXIMUM RATINGS. . . . . . . . . . . 19
ESD SENSITIVITY . . . . . . . . . . . . . . . . . . . . . . . . .19
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . .19
TIMING SPECIFICATIONS . . . . . . . . . . . . . . . . .20
Output Drive Currents . . . . . . . . . . . . . . . . . . . . . . .41
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . .41
Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
Environmental Conditions . . . . . . . . . . . . . . . . . . . .42
144-Lead LQFP Pinout . . . . . . . . . . . . . . . . . . . . . .44
144-Lead Mini-BGA Pinout . . . . . . . . . . . . . . . . . . .46
OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . .48
ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . .49
GENERAL DESCRIPTIONThe ADSP-2191M DSP is a single-chip microcomputer
optimized for digital signal processing (DSP) and other high
speed numeric processing applications.
The ADSP-2191M combines the ADSP-219x family base
architecture (three computational units, two data address gener-
ators, and a program sequencer) with three serial ports, two
SPI-compatible ports, one UART port, a DMA controller, three
programmable timers, general-purpose Programmable Flag
pins, extensive interrupt capabilities, and on-chip program and
data memory spaces.
The ADSP-2191M architecture is code-compatible with DSPs
of the ADSP-218x family. Although the architectures are
compatible, the ADSP-2191M architecture has a number of
enhancements over the ADSP-218x architecture. The enhance-
ments to computational units, data address generators, and
program sequencer make the ADSP-2191M more flexible and
even easier to program.
Indirect addressing options provide addressing flexibility—
premodify with no update, pre- and post-modify by an immediate
8-bit, two’s-complement value and base address registers for
easier implementation of circular buffering.
The ADSP-2191M integrates 64K words of on-chip memory
configured as 32K words (24-bit) of program RAM, and 32K
words (16-bit) of data RAM. Power-down circuitry is also
provided to reduce power consumption. The ADSP-2191M is
available in 144-lead LQFP and 144-ball mini-BGA packages.
Fabricated in a high-speed, low-power, CMOS process, the
ADSP-2191M operates with a 6.25ns instruction cycle time
(160MIPS). All instructions, except single-word instructions,
execute in one processor.
The ADSP-2191M’s flexible architecture and comprehensive
instruction set support multiple operations in parallel. For
example, in one processor cycle, the ADSP-2191M can:Generate an address for the next instruction fetchFetch the next instructionPerform one or two data movesUpdate one or two data address pointersPerform a computational operation
These operations take place while the processor continuesto:Receive and transmit data through two serial portsReceive and/or transmit data from a HostReceive or transmit data through the UARTReceive or transmit data over two SPI portsAccess external memory through the external memory
interfaceDecrement the timers
DSP Core ArchitectureThe ADSP-2191M instruction set provides flexible data moves
uses an algebraic syntax for ease of coding and readability. A
comprehensive set of development tools supports program
development.
The functional block diagram onpage1 shows the architecture
of the ADSP-219x core. It contains three independent compu-
tational units: the ALU, the multiplier/accumulator (MAC), and
the shifter. The computational units process 16-bit data from the
register file and have provisions to support multiprecision com-
putations. The ALU performs a standard set of arithmetic and
logic operations; division primitives are also supported. The
MAC performs single-cycle multiply, multiply/add, and multi-
ply/subtract operations. The MAC has two 40-bit accumulators,
which help with overflow. The shifter performs logical and arith-
metic shifts, normalization, denormalization, and derive
exponent operations. The shifter can be used to efficiently
implement numeric format control, including multiword and
block floating-point representations.
Register-usage rules influence placement of input and results
within the computational units. For most operations, the com-
putational units’ data registers act as a data register file,
permitting any input or result register to provide input to any unit
for a computation. For feedback operations, the computational
units let the output (result) of any unit be input to any unit on
the next cycle. For conditional or multifunction instructions,
there are restrictions on which data registers may provide inputs
or receive results from each computational unit. For more infor-
mation, see the ADSP-219x DSP Instruction Set Reference.
A powerful program sequencer controls the flow of instruction
execution. The sequencer supports conditional jumps, subrou-
tine calls, and low interrupt overhead. With internal loop
counters and loop stacks, the ADSP-2191M executes looped
code with zero overhead; no explicit jump instructions are
required to maintain loops.
Two data address generators (DAGs) provide addresses for
simultaneous dual operand fetches (from data memory and
program memory). Each DAG maintains and updates four
16-bit address pointers. Whenever the pointer is used to access
data (indirect addressing), it is pre- or post-modified by the value
of one of four possible modify registers. A length value and base
address may be associated with each pointer to implement
automatic modulo addressing for circular buffers. Page registers
in the DAGs allow circular addressing within 64K word bound-
aries of each of the 256 memory pages, but these buffers may not
cross page boundaries. Secondary registers duplicate all the
primary registers in the DAGs; switching between primary and
secondary registers provides a fast context switch.
Efficient data transfer in the core is achieved with the use of
internal buses:Program Memory Address (PMA) BusProgram Memory Data (PMD) BusData Memory Address (DMA) BusData Memory Data (DMD) Bus
ADSP-2191MThe two address buses (PMA and DMA) share a single external
address bus, allowing memory to be expanded off-chip, and the
two data buses (PMD and DMD) share a single external data
bus. Boot memory space and I/O memory space also share the
external buses.
Program memory can store both instructions and data, permit-
ting the ADSP-2191M to fetch two operands in a single cycle,
one from program memory and one from data memory. The
DSP’s dual memory buses also let the ADSP-219x core fetch an
operand from data memory and the next instruction from
program memory in a single cycle.
DSP Peripherals ArchitectureThe functional block diagram onpage1 shows the DSP’s
on-chip peripherals, which include the external memory inter-
face, Host port, serial ports, SPI-compatible ports, UART port,
JTAG test and emulation port, timers, flags, and interrupt con-
troller. These on-chip peripherals can connect to off-chip devices
as shown in Figure1.
The ADSP-2191M has a 16-bit Host port with DMA capability
that lets external Hosts access on-chip memory. This 24-pin
parallel port consists of a 16-pin multiplexed data/address bus
and provides a low-service overhead data move capability. Con-
figurable for 8 or 16 bits, this port provides a glueless interface
to a wide variety of 8- and 16-bit microcontrollers. Two
chip-selects provide Hosts access to the DSP’s entire memory
map. The DSP is bootable through this port.
The ADSP-2191M also has an external memory interface that is
shared by the DSP’s core, the DMA controller, and DMA
capable peripherals, which include the UART, SPORT0,
SPORT1, SPORT2, SPI0, SPI1, and the Host port. The external
port consists of a 16-bit data bus, a 22-bit address bus, and
control signals. The data bus is configurable to provide an 8 or bit interface to external memory. Support for word packing
lets the DSP access 16- or 24-bit words from external memory
regardless of the external data bus width. When configured for
an 8-bit interface, the unused eight lines provide eight program-
mable, bidirectional general-purpose Programmable Flag lines,
six of which can be mapped to software condition signals.
The memory DMA controller lets the ADSP-2191M move data
and instructions from between memory spaces: internal-to-exter-
nal, internal-to-internal, and external-to- external. On-chip
peripherals can also use this controller for DMA transfers.
The ADSP-2191M can respond to up to seventeen interrupts at
any given time: three internal (stack, emulator kernel, and
power-down), two external (emulator and reset), and twelve
user-defined (peripherals) interrupts. The programmer assigns a
peripheral to one of the 12 user-defined interrupts. The priority
of each peripheral for interrupt service is determined by these
assignments.
There are three serial ports on the ADSP-2191M that provide a
complete synchronous, full-duplex serial interface. This interface
includes optional companding in hardware and a wide variety of
tion. Each serial port can transmit or receive an internal or
external, programmable serial clock and frame syncs. Each serial
port supports 128-channel Time Division Multiplexing.
The ADSP-2191M provides up to sixteen general-purpose I/O
pins, which are programmable as either inputs or outputs. Eight
of these pins are dedicated-general purpose Programmable Flag
pins. The other eight of them are multifunctional pins, acting as
general-purpose I/O pins when the DSP connects to an 8-bit
external data bus and acting as the upper eight data pins when
the DSP connects to a 16-bit external data bus. These Program-
mable Flag pins can implement edge- or level-sensitive
interrupts, some of which can be used to base the execution of
Figure 1.System Diagram
Three programmable interval timers generate periodic inter-
rupts. Each timer can be independently set to operate in one of
three modes:Pulse Waveform Generation modePulsewidth Count/Capture modeExternal Event Watchdog mode
Each timer has one bidirectional pin and four registers that
implement its mode of operation: A 7-bit configuration register,
a 32-bit count register, a 32-bit period register, and a 32-bit
pulsewidth register. A single status register supports all three
timers. A bit in each timer’s configuration register enables or
disables the corresponding timer independently of the others.
Memory ArchitectureThe ADSP-2191M DSP provides 64K words of on-chip SRAM
memory. This memory is divided into four 16K blocks located
on memory Page0 in the DSP’s memory map. In addition to the
internal and external memory space, the ADSP-2191M can
address two additional and separate off-chip memory spaces: I/O
space and boot space.
As shown in Figure2, the DSP’s two internal memory blocks
populate all of Page0. The entire DSP memory map consists of
256 pages (Pages 0−255), and each page is 64K words long.
External memory space consists of four memory banks (banks
0–3) and supports a wide variety of SRAM memory devices. Each
bank is selectable using the memory select pins (MS3–0) and has
configurable page boundaries, waitstates, and waitstate modes.
The 1K word of on-chip boot-ROM populates the top of
Page255 while the remaining 254 pages are addressable off-chip.
I/O memory pages differ from external memory pages in that I/O
pages are 1K word long, and the external I/O pages have their
own select pin (IOMS). Pages 0–7 of I/O memory space reside
on-chip and contain the configuration registers for the peripher-
als. Both the core and DMA-capable peripherals can access the
DSP’s entire memory map.
Internal (On-Chip) MemoryThe ADSP-2191M’s unified program and data memory space
consists of 16M locations that are accessible through two 24-bit
address buses, the PMA and DMA buses. The DSP uses slightly
Figure 2.Memory Map
ADSP-2191Mdifferent mechanisms to generate a 24-bit address for each bus.
The DSP has three functions that support access to the full
memory map.The DAGs generate 24-bit addresses for data fetches from
the entire DSP memory address range. Because DAG
index (address) registers are 16 bits wide and hold the
lower 16bits of the address, each of the DAGs has its own
8-bit page register (DMPGx) to hold the most significant
eight address bits. Before a DAG generates an address,
the program must set the DAG’s DMPGx register to the
appropriate memory page.The Program Sequencer generates the addresses for
instruction fetches. For relative addressing instructions,
the program sequencer bases addresses for relative jumps,
calls, and loops on the 24-bit Program Counter (PC). In
direct addressing instructions (two-word instructions),
the instruction provides an immediate 24-bit address
value. The PC allows linear addressing of the full 24-bit
address range.For indirect jumps and calls that use a 16-bit DAG
address register for part of the branch address, the
Program Sequencer relies on an 8-bit Indirect Jump page
(IJPG) register to supply the most significant eight
address bits. Before a cross page jump or call, the program
must set the program sequencer’s IJPG register to the
appropriate memory page.
The ADSP-2191M has 1K word of on-chip ROM that holds boot
routines. If peripheral booting is selected, the DSP starts
executing instructions from the on-chip boot ROM, which starts
the boot process from the selected peripheral. For more informa-
tion, see “Booting Modes” on page11. The on-chip boot ROM
is located on Page255 in the DSP’s memory space map.
External (Off-Chip) MemoryEach of the ADSP-2191M’s off-chip memory spaces has a
separate control register, so applications can configure unique
access parameters for each space. The access parameters include
read and write wait counts, waitstate completion mode, I/O clock
divide ratio, write hold time extension, strobe polarity, and data
bus width. The core clock and peripheral clock ratios influence
the external memory access strobe widths. For more information,
see “Clock Signals” on page11. The off-chip memory spacesare:External memory space (MS3–0 pins)I/O memory space (IOMS pin)Boot memory space (BMS pin)
All of these off-chip memory spaces are accessible through the
External Port, which can be configured for data widths of
8 or 16 bits.
External Memory SpaceExternal memory space consists of four memory banks. These
banks can contain a configurable number of 64K word pages. At
reset, the page boundaries for external memory have Bank0
containing pages1−63, Bank1 containing pages64−127, Bank2
containing pages128−191, and Bank3 that contains pages
192−254. The MS3–0 memory bank pins select Banks 3–0,
respectively. The external memory interface is byte-addressable
and decodes the 8 MSBs of the DSP program address to select
one of the four banks. Both the ADSP-219x core and DMA-capa-
ble peripherals can access the DSP’s external memory space.
I/O Memory SpaceThe ADSP-2191M supports an additional external memory
called I/O memory space. This space is designed to support
simple connections to peripherals (such as data converters and
external registers) or to bus interface ASIC data registers. I/O
space supports a total of 256K locations. The first 8K addresses
are reserved for on-chip peripherals. The upper 248K addresses
are available for external peripheral devices. The DSP’s instruc-
tion set provides instructions for accessing I/O space. These
instructions use an 18-bit address that is assembled from an
8-bit I/O page (IOPG) register and a 10-bit immediate value
supplied in the instruction. Both the ADSP-219x core and a Host
(through the Host Port Interface) can access I/O memory space.
Boot Memory SpaceBoot memory space consists of one off-chip bank with 63 pages.
The BMS memory bank pin selects boot memory space. Both
the ADSP-219x core and DMA-capable peripherals can access
the DSP’s off-chip boot memory space. After reset, the DSP
always starts executing instructions from the on-chip boot ROM.
Depending on the boot configuration, the boot ROM code can
start booting the DSP from boot memory. For more information,
see “Booting Modes” on page11.
InterruptsThe interrupt controller lets the DSP respond to 17 interrupts
with minimum overhead. The controller implements an interrupt
priority scheme as shown in Table1. Applications can use the
unassigned slots for software and peripheral interrupts.
Table2 shows the ID and priority at reset of each of the periph-
eral interrupts. To assign the peripheral interrupts a different
priority, applications write the new priority to their correspond-
ing control bits (determined by their ID) in the Interrupt Priority
Control register. The peripheral interrupt’s position in the
IMASK and IRPTL register and its vector address depend on its
priority level, as shown in Table1. Because the IMASK and
IRPTL registers are limited to 16 bits, any peripheral interrupts
assigned a priority level of 11 are aliased to the lowest priority bit
position (15) in these registers and share vector address
0x0001E0.
Interrupt routines can either be nested with higher priority inter-
rupts taking precedence or processed sequentially. Interrupts can
be masked or unmasked with the IMASK register. Individual
interrupt requests are logically ANDed with the bits in IMASK;
The Interrupt Control (ICNTL) register controls interrupt
nesting and enables or disables interrupts globally.
The general-purpose Programmable Flag (PFx) pins can be con-
figured as outputs, can implement software interrupts, and (as
inputs) can implement hardware interrupts. Programmable Flag
pin interrupts can be configured for level-sensitive, single
edge-sensitive, or dual edge-sensitiveoperation.
The IRPTL register is used to force and clear interrupts. On-chip
stacks preserve the processor status and are automatically main-
tained during interrupt handling. To support interrupt, loop, and
subroutine nesting, the PC stack is 33levels deep, the loop stack
is eight levels deep, and the status stack is 16levels deep. To
prevent stack overflow, the PC stack can generate a stack-level
interrupt if the PC stack falls below three locations full or rises
above 28 locationsfull.
The following instructions globally enable or disable interrupt
servicing, regardless of the state of IMASK.
ENAINT;
DISINT;At reset, interrupt servicing is disabled.
For quick servicing of interrupts, a secondary set of DAG and
computational registers exist. Switching between the primary
and secondary registers lets programs quickly service interrupts,
while preserving the DSP’s state.
DMA ControllerThe ADSP-2191M has a DMA controller that supports
automated data transfers with minimal overhead for the DSP
core. Cycle stealing DMA transfers can occur between the
ADSP-2191M’s internal memory and any of its DMA-capable
peripherals. Additionally, DMA transfers can be accomplished
between any of the DMA-capable peripherals and external
devices connected to the external memory interface. DMA-capa-
ble peripherals include the Host port, SPORTs, SPI ports, and
UART. Each individual DMA-capable peripheral has a dedicated
DMA channel. To describe each DMA sequence, the DMA con-
troller uses a set of parameters—called a DMA descriptor. When
successive DMA sequences are needed, these DMA descriptors
can be linked or chained together, so the completion of one DMA
Table 1.Interrupt Priorities/Addresses These interrupt vectors start at address 0x10000 when the DSP is in
“no-boot,” run from external memory mode.
Table 2.Peripheral Interrupts and Priority at Reset
Table 3.Interrupt Control (ICNTL) Register Bits
ADSP-2191MAll DMA transfers use the DMA bus shown in the functional
block diagram onpage1. Because all of the peripherals use the
same bus, arbitration for DMA bus access is needed. The arbi-
tration for DMA bus access appears in Table4.
Host PortThe ADSP-2191M’s Host port functions as a slave on the
external bus of an external Host. The Host port interface lets a
Host read from or write to the DSP’s memory space, boot space,
or internal I/O space. Examples of Hosts include external micro-
controllers, microprocessors, orASICs.
The Host port is a multiplexed address and data bus that provides
both an 8-bit and a 16-bit data path and operates using an asyn-
chronous transmission protocol. Through this port, an off-chip
Host can directly access the DSP’s entire memory space map,
boot memory space, and internal I/O space. To access the DSP’s
internal memory space, a Host steals one cycle per access from
the DSP. A Host access to the DSP’s external memory uses the
external port interface and does not stall (or steal cycles from)
the DSP’s core. Because a Host can access internal I/O memory
space, a Host can control any of the DSP’s I/O mapped
peripherals.
The Host port is most efficient when using the DSP as a slave
and uses DMA to automate the incrementing of addresses for
these accesses. In this case, an address does not have to be trans-
ferred from the Host for every datatransfer.
Host Port Acknowledge (HACK) ModesThe Host port supports a number of modes (or protocols) for
generating a HACK output for the host. The host selects ACK
or Ready Modes using the HACK_P and HACK pins. The Host
port also supports two modes for address control: Address Latch
Enable (ALE) and Address Cycle Control (ACC) modes. The
DSP auto-detects ALE versus ACC Mode from the HALE and
HWR inputs.
The Host port HACK signal polarity is selected (only at reset) as
active high or active low, depending on the value driven on the
HACK_P pin.The HACK polarity is stored into the Host port
The DSP uses HACK to indicate to the Host when to complete
an access. For a read transaction, a Host can proceed and
complete an access when valid data is present in the read buffer
and the Host port is not busy doing a write. For a write transac-
tions, a Host can complete an access when the write buffer is not
full and the Host port is not busy doing a write.
Two mode bits in the Host Port configuration register HPCR
[7:6] define the functionality of the HACK line. HPCR6 is ini-
tialized at reset based on the values driven on HACK and
HACK_P pins (shown in Table5); HPCR7 is always cleared (0)
at reset. HPCR [7:6] can be modified after reset by a write access
to the Host port configurationregister.
The functional modes selected by HPCR [7:6] are as follows
(assuming active high signal):
ACK Mode—Acknowledge is active on strobes; HACK goes high from the leading edge of the strobe to indicate
when the access can complete. After the Host samples the
HACK active, it can complete the access by removing the
strobe.The Host port then removes theHACK.
Ready Mode—Ready active on strobes, goes low to insert
waitstate during the access.If the Host port cannot
complete the access, it deasserts the HACK/READY line.
In this case, the Host has to extend the access by keeping
the strobe asserted. When the Host samples the HACK
asserted, it can then proceed and complete the access by
deasserting the strobe.
While in Address Cycle Control (ACC) mode and the ACK or
Ready acknowledge modes, the HACK is returned active for any
address cycle.
Host Port Chip SelectsThere are two chip-select signals associated with the Host port:
HCMS and HCIOMS. The Host Chip Memory Select (HCMS)
lets the Host select the DSP and directly access the DSP’s inter-
nal/external memory space or boot memory space. The Host
Chip I/O Memory Select (HCIOMS) lets the Host select the DSP
and directly access the DSP’s internal I/O memory space.
Before starting a direct access, the Host configures Host port
interface registers, specifying the width of external data bus
(8- or 16-bit) and the target address page (in the IJPG register).
The DSP generates the needed memory select signals during the
access, based on the target address. The Host port interface
Table 4.I/O Bus Arbitration Priority
Table 5.Host Port Acknowledge Mode Selection
each byte access that does not start a read or complete a write.
Otherwise, the Host port interface asserts ACK when it has
completed the memory access successfully.
DSP Serial Ports (SPORTs)The ADSP-2191M incorporates three complete synchronous
serial ports (SPORT0, SPORT1, and SPORT2) for serial and
multiprocessor communications. The SPORTs support the
following features:Bidirectional operation—each SPORT has independent
transmit and receive pins.Double-buffered transmit and receive ports—each port
has a data register for transferring data words to and from
memory and shift registers for shifting data in and out of
the data registers.Clocking—each transmit and receive port can either use
an external serial clock (40 MHz) or generate its own, in
frequencies ranging from 19Hz to 40MHz.Word length—each SPORT supports serial data words
from 3 to 16 bits in length transferred in Big Endian
(MSB) or Little Endian (LSB) format.Framing—each transmit and receive port can run with or
without frame sync signals for each data word. Frame sync
signals can be generated internally or externally, active
high or low, and with either of two pulsewidths and early
or late frame sync.Companding in hardware—each SPORT can perform
A-law or µ-law companding according to ITU recommen-
dation G.711. Companding can be selected on the
transmit and/or receive channel of the SPORT without
additional latencies.DMA operations with single-cycle overhead—each
SPORT can automatically receive and transmit multiple
buffers of memory data, one data word each DSP cycle.
Either the DSP’s core or a Host processor can link or chain
sequences of DMA transfers between a SPORT and
memory. The chained DMA can be dynamically allocated
and updated through the DMA descriptors (DMA
transfer parameters) that set up the chain.Interrupts—each transmit and receive port generates an
interrupt upon completing the transfer of a data word or
after transferring an entire data buffer or buffers through
DMA.Multichannel capability—each SPORT supports the
H.100 standard.
Serial Peripheral Interface (SPI) PortsThe DSP has two SPI-compatible ports that enable the DSP to
communicate with multiple SPI-compatible devices. These ports
are multiplexed with SPORT2, so either SPORT2 or the SPI
ports are active, depending on the state of the OPMODE pin
during hardware reset.
The SPI interface uses three pins for transferring data: two data
SCKx). Two SPI chip select input pins (SPISSx) let other SPI
devices select the DSP, and fourteen SPI chip select output pins
(SPIxSEL7–1) let the DSP select other SPI devices. The SPI
select pins are reconfigured Programmable Flag pins. Using these
pins, the SPI ports provide a full duplex, synchronous serial inter-
face, which supports both master and slave modes and
multimaster environments.
Each SPI port’s baud rate and clock phase/polarities are program-
mable (see equation below for SPI clock rate calculation), and
each has an integrated DMA controller, configurable to support
both transmit and receive data streams. The SPI’s DMA control-
ler can only service unidirectional accesses at any given time.
During transfers, the SPI ports simultaneously transmit and
receive by serially shifting data in and out on their two serial data
lines. The serial clock line synchronizes the shifting and sampling
of data on the two serial data lines.
UART PortThe UART port provides a simplified UART interface to another
peripheral or Host. It performs full duplex, asynchronous
transfers of serial data. Options for the UART include support
for 5–8 data bits; 1 or 2 stop bits; and none, even, or odd parity.
The UART port supports two modes ofoperation:Programmed I/O
The DSP’s core sends or receives data by writing or
reading I/O-mapped THR or RBR registers, respectively.
The data is double-buffered on both transmit and receive.DMA (direct memory access)
The DMA controller transfers both transmit and receive
data. This reduces the number and frequency of inter-
rupts required to transfer data to and from memory. The
UART has two dedicated DMA channels. These DMA
channels have lower priority than most DMA channels
because of their relatively low servicerates.
The UART’s baud rate (see following equation for UART clock
rate calculation), serial data format, error code generation and
status, and interrupts are programmable:Supported bit rates range from 9.5 bits to 5Mbits per
second (80MHz peripheral clock).Supported data formats are 7- to 12-bit frames.Transmit and receive status can be configured to generate
maskable interrupts to the DSP’s core.
The timers can be used to provide a hardware-assisted autobaud
detection mechanism for the UART interface.
SPI Clock RateHCLKSPIBAUD×---------------------------------------=
UART Clock RateHCLKD×------------------=
ADSP-2191M
Programmable Flag (PFx) PinsThe ADSP-2191M has 16 bidirectional, general-purpose I/O,
Programmable Flag (PF15–0) pins. The PF7–0 pins are
dedicated to general-purpose I/O. The PF15–8 pins serve either
as general-purpose I/O pins (if the DSP is connected to an 8-bit
external data bus) or serve as DATA15–8 lines (if the DSP is
connected to a 16-bit external data bus). The Programmable Flag
pins have special functions for clock multiplier selection and for
SPI port operation. For more information, see Serial Peripheral
Interface (SPI) Ports on page9 and Clock Signals on page11.
Ten memory-mapped registers control operation of the Program-
mable Flag pins:Flag Direction register
Specifies the direction of each individual PFx pin as input
or output. Flag Control and Status registers
Specify the value to drive on each individual PFx output
pin. As input, software can predicate instruction
execution on the value of individual PFx input pins
captured in this register. One register sets bits, and one
register clears bits.Flag Interrupt Mask registers
Enable and disable each individual PFx pin to function
as an interrupt to the DSP’s core. One register sets bits to
enable interrupt function, and one register clears bits to
disable interrupt function. Input PFx pins function as
hardware interrupts, and output PFx pins function as
software interrupts—latching in the IMASK and IRPTL
registers.Flag Interrupt Polarity register
Specifies the polarity (active high or low) for interrupt
sensitivity on each individual PFx pin. Flag Sensitivity registers
Specify whether individual PFx pins are level- or
edge-sensitive and specify—if edge-sensitive—whether
just the rising edge or both the rising and falling edges of
the signal are significant. One register selects the type of
sensitivity, and one register selects which edges are signif-
icant for edge-sensitivity.
Low Power OperationThe ADSP-2191M has four low-power options that significantly
reduce the power dissipation when the device operates under
standby conditions. To enter any of these modes, the DSP
executes an IDLE instruction. The ADSP-2191M uses configu-
ration of the PDWN, STOPCK, and STOPALL bits in the
PLLCTL register to select between the low-power modes as the
DSP executes the IDLE. Depending on the mode, an IDLE shuts
off clocks to different parts of the DSP in the different modes.
The low power modes are:IdlePower-Down Core
Idle ModeWhen the ADSP-2191M is in Idle mode, the DSP core stops
executing instructions, retains the contents of the instruction
pipeline, and waits for an interrupt. The core clock and peripheral
clock continue running.
To enter Idle mode, the DSP can execute the IDLE instruction
anywhere in code. To exit Idle mode, the DSP responds to an
interrupt and (after two cycles of latency) resumes executing
instructions with the instruction after the IDLE.
Power-Down Core ModeWhen the ADSP-2191M is in Power-Down Core mode, the DSP
core clock is off, but the DSP retains the contents of the pipeline
and keeps the PLL running. The peripheral bus keeps running,
letting the peripherals receive data.
To enter Power-Down Core mode, the DSP executes an IDLE
instruction after performing the following tasks:Enter a power-down interrupt service routineCheck for pending interrupts and I/O serviceroutinesClear (= 0) the PDWN bit in the PLLCTL registerClear (= 0) the STOPALL bit in the PLLCTLregisterSet (= 1) the STOPCK bit in the PLLCTL register
To exit Power-Down Core mode, the DSP responds to an
interrupt and (after two cycles of latency) resumes executing
instructions with the instruction after the IDLE.
Power-Down Core/Peripherals ModeWhen the ADSP-2191M is in Power-Down Core/Peripherals
mode, the DSP core clock and peripheral bus clock are off, but
the DSP keeps the PLL running. The DSP does not retain the
contents of the instruction pipeline.The peripheral bus is
stopped, so the peripherals cannot receive data.
To enter Power-Down Core/Peripherals mode, the DSP executes
an IDLE instruction after performing the followingtasks:Enter a power-down interrupt service routineCheck for pending interrupts and I/O serviceroutinesClear (= 0) the PDWN bit in the PLLCTL registerSet (= 1) the STOPALL bit in the PLLCTLregister
To exit Power-Down Core/Peripherals mode, the DSP responds
to a wake-up event and (after five to six cycles of latency) resumes
executing instructions with the instruction after the IDLE.
Power-Down All ModeWhen the ADSP-2191M is in Power-Down All mode, the DSP
core clock, the peripheral clock, and the PLL are all stopped. The
DSP does not retain the contents of the instruction pipeline. The
peripheral bus is stopped, so the peripherals cannot receive data.
To enter Power-Down All mode, the DSP executes an IDLE
instruction after performing the following tasks:Enter a power-down interrupt service routineCheck for pending interrupts and I/O serviceroutines
To exit Power-Down Core/Peripherals mode, the DSP responds
to an interrupt and (after 500 cycles to restabilize the PLL)
resumes executing instructions with the instruction after the
IDLE.
Clock SignalsThe ADSP-2191M can be clocked by a crystal oscillator or a
buffered, shaped clock derived from an external clock oscillator.
If a crystal oscillator is used, the crystal should be connected
across the CLKIN and XTAL pins, with two capacitors and a
1M Ω shunt resistor connected as shown in Figure3. Capacitor
values are dependent on crystal type and should be specified by
the crystal manufacturer. A parallel-resonant, fundamental fre-
quency, microprocessor-grade crystal should be used for this
configuration.
If a buffered, shaped clock is used, this external clock connects
to the DSP’s CLKIN pin. CLKIN input cannot be halted,
changed, or operated below the specified frequency during
normal operation. When an external clock is used, the XTAL
input must be left unconnected.
The DSP provides a user-programmable 1� to 32� multiplica-
tion of the input clock, including some fractional values, to
support 128 external to internal (DSP core) clock ratios. The
MSEL6–0, BYPASS, and DF pins decide the PLL multiplication
factor at reset. At runtime, the multiplication factor can be con-
trolled in software. The combination of pullup and pull-down
resistors in Figure sets up a core clock ratio of6:1, which
produces a 150MHz core clock from the 25MHz input. For
other clock multiplier settings, see the ADSP-219x/2191 DSP
Hardware Reference.
The peripheral clock is supplied to the CLKOUT pin.
All on-chip peripherals for the ADSP-2191M operate at the rate
set by the peripheral clock. The peripheral clock is either equal
to the core clock rate or one-half the DSP core clock rate. This
selection is controlled by the IOSEL bit in the PLLCTL register.
The maximum core clock is160MHz and the maximum periph-
eral clock is80MHz—the combination of the input clock and
core/peripheral clock ratios may not exceed these limits.
ResetThe RESET signal initiates a master reset of the ADSP-2191M.
The RESET signal must be asserted during the powerup
sequence to assure proper initialization. RESET during initial
powerup must be held long enough to allow the internal clock to
stabilize.
The powerup sequence is defined as the total time required for
the crystal oscillator circuit to stabilize after a valid VDD is applied
to the processor, and for the internal phase-locked loop (PLL) to
lock onto the specific crystal frequency. A minimum of 100µs
ensures that the PLL has locked, but does not include the crystal
oscillator start-up time. During this powerup sequence the
RESET signal should be held low. On any subsequent resets, the
RESET signal must meet the minimum pulsewidth specifica-
tion,t.
The RESET input contains some hysteresis. If using an RC
circuit to generate your RESET signal, the circuit should use an
external Schmidt trigger.
The master reset sets all internal stack pointers to the empty stack
condition, masks all interrupts, and resets all registers to their
default values (where applicable). When RESET is released, if
there is no pending bus request and the chip is configured for
booting, the boot-loading sequence is performed. Program
control jumps to the location of the on-chip boot ROM
(0xFF0000).
Power SuppliesThe ADSP-2191M has separate power supply connections for
the internal (VDDINT) and external (VDDEXT) power supplies.
The internal supply must meet the 2.5V requirement. The
external supply must be connected to a 3.3V supply. All external
supply pins must be connected to the same supply.
Powerup SequencePower up together the two supplies VDDEXT and VDDINT. If
they cannot be powered up together, power up the internal (core)
supply first (powering up the core supply first reduces the risk of
latchup events.
Booting ModesThe ADSP-2191M has five mechanisms (listed in Table6) for
Figure 3.External Crystal Connections
ADSP-2191MThe OPMODE, BMODE1, and BMODE0 pins, sampled
during hardware reset, and three bits in the Reset Configuration
Register implement these modes:Execute from memory external 16 bits—The memory
boot routine located in boot ROM memory space
executes a boot-stream-formatted program located at
address 0x010000 of boot memory space, packing 16-bit
external data into 24-bit internal data. The External Port
Interface is configured for the default clock multiplier
(128) and read waitstates (7).Boot from EPROM—The EPROM boot routine located
in boot ROM memory space fetches a boot-stream-for-
matted program located at physical address 0x00 0000 of
boot memory space, packing 8- or 16-bit external data
into 24-bit internal data. The External Port Interface is
configured for the default clock multiplier (32) and read
waitstates (7).Boot from Host—The (8- or 16-bit) Host downloads a
boot-stream-formatted program to internal or external
memory. The Host’s boot routine is located in internal
ROM memory space and uses the top 16 locations of
Page0 program memory and the top 272 locations of
Page0 data memory.
The internal boot ROM sets semaphore A (an IO register
within the Host port) and then polls until the semaphore
is reset. Once detected, the internal boot ROM will remap
the interrupt vector table to Page0 internal memory and
jump to address 0x00 0000 internal memory. From the
point of view of the host interface, an external host has
full control of the DSP's memory map. The Host has the
freedom to directly write internal memory, external
memory, and internal I/O memory space. The DSP core
execution is held off until the Host clears the semaphore
register. This strategy allows the maximum flexibility for Execute from memory external 8 bits (No Boot)—
Execution starts from Page1 of external memory space,
packing either 8- or 16-bit external data into 24-bit
internal data. The External Port Interface is config-
ured for the default clock multiplier (128) and read
waitstates (7).Boot from UART—The Host downloads
boot-stream-formatted program using an autobaud
handshake sequence. The Host agent selects a baud rate
within the UART’s clocking capabilities. After a hardware
reset, the DSP’s UART expects a 0xAA character (eight
bits data, one start bit, one stop bit, no parity bit) on the
RXD pin to determine the bit rate; and then replies with
an OK string. Once the host receives this OK it downloads
the boot stream without further handshake.The UART
boot routine is located in internal ROM memory space
and uses the top 16 locations of Page0 program memory
and the top 272 locations of Page0 data memory.Boot from SPI, up to 4K bits—The SPI0 port uses the
SPI0SEL1 (reconfigured PF2) output pin to select a
single serial EEPROM device, submits a read command
at address 0x00, and begins clocking consecutive data into
internal or external memory. Use only SPI-compatible
EEPROMs of ≤4K bit (12-bit address range). The SPI0
boot routine located in internal ROM memory space
executes a boot-stream-formatted program, using the top
16 locations of Page0 program memory and the top 272
locations of Page0 data memory. The SPI boot configu-
ration is SPIBAUD0=60 (decimal), CPHA=1, CPOL=1,
8-bit data, and MSB first.Boot from SPI, from >4K bits to 512K bits—The SPI0
port uses the SPI0SEL1 (re-configured PF2) output pin
to select a single serial EEPROM device, submits a read
command at address 0x00, and begins clocking consecu-
tive data into internal or external memory. Use only
SPI-compatible EEPROMs of ≥4K bit (16-bit address
range). The SPI0 boot routine, located in internal ROM
memory space, executes a boot-stream-formatted
program, using the top 16 locations of Page0 program
memory and the top 272 locations of Page0 data memory.
As indicated in Table6, the OPMODE pin has a dual role, acting
as a boot mode select during reset and determining SPORT or
SPI operation at runtime. If the OPMODE pin at reset is the
opposite of what is needed in an application during runtime, the
application needs to set the OPMODE bit appropriately during
runtime prior to using the corresponding peripheral.
Bus Request and Bus GrantThe ADSP-2191M can relinquish control of the data and address
buses to an external device. When the external device requires
access to the bus, it asserts the bus request (BR) signal. The (BR)
signal is arbitrated with core and peripheral requests. External
Bus requests have the lowest priority. If no other internal request
is pending, the external bus request will be granted. Because of
Table 6.Select Boot Mode (OPMODE, BMODE1, and
BMODE0)
synchronizer and arbitration delays, bus grants will be provided
with a minimum of three peripheral clock delays. ADSP-2191M
DSPs will respond to the bus grant by:Three-stating the data and address buses and the MS3–0,
BMS, IOMS, RD, and WR output drivers.Asserting the bus grant (BG) signal.
The ADSP-2191M will halt program execution if the bus is
granted to an external device and an instruction fetch or data
read/write request is made to external general-purpose or periph-
eral memory spaces. If an instruction requires two external
memory read accesses, bus requests will not be granted between
the two accesses. If an instruction requires an external memory
read and an external memory write access, the bus may be
granted between the two accesses. The external memory
interface can be configured so that the core will have exclusive
use of the interface. DMA and Bus Requests will be granted.
When the external device releases BR, the DSP releases BG and
continues program execution from the point at which it stopped.
The bus request feature operates at all times, even while the DSP
is booting and RESET is active.
The ADSP-2191M asserts the BGH pin when it is ready to start
another external port access, but is held off because the bus was
previously granted. This mechanism can be extended to define
more complex arbitration protocols for implementing more
elaborate multimaster systems.
Instruction Set DescriptionThe ADSP-2191M assembly language instruction set has an
algebraic syntax that was designed for ease of coding and read-
ability. The assembly language, which takes full advantage of the
processor’s unique architecture, offers the following benefits:ADSP-219x assembly language syntax is a superset of and
source-code-compatible (except for two data registers
and DAG base address registers) with ADSP-218x family
syntax. It may be necessary to restructure ADSP-218x
programs to accommodate the ADSP-2191M’s unified
memory space and to conform to its interrupt vector map.The algebraic syntax eliminates the need to remember
cryptic assembler mnemonics. For example, a typical
arithmetic add instruction, such as AR=AX0+AY0,
resembles a simple equation.Every instruction, but two, assembles into a single, 24-bit
word that can execute in a single instruction cycle. The
exceptions are two dual word instructions. One writes 16-
or 24-bit immediate data to memory, and the other is an
absolute jump/call with the 24-bit address specified in the
instruction.Multifunction instructions allow parallel execution of an
arithmetic, MAC, or shift instruction with up to two
fetches or one write to processor memory space during a
single instruction cycle.Program flow instructions support a wider variety of con-
Development ToolsThe ADSP-2191M is supported with a complete set of software
and hardware development tools, including Analog Devices
emulators and VisualDSP++® development environment. The
same emulator hardware that supports other ADSP-219x DSPs,
also fully emulates the ADSP-2191M.
The VisualDSP++ project management environment lets pro-
grammers develop and debug an application. This environment
includes an easy-to-use assembler that is based on an algebraic
syntax; an archiver (librarian/library builder), a linker, a loader,
a cycle-accurate instruction-level simulator, a C/C++ compiler,
and a C/C++ run-time library that includes DSP and mathemat-
ical functions. Two key points for these tools are:Compiled ADSP-219x C/C++ code efficiency—the
compiler has been developed for efficient translation of
C/C++ code to ADSP-219x assembly. The DSP has
architectural features that improve the efficiency of
compiledC/C++code.ADSP-218x family code compatibility—The assembler
has legacy features to ease the conversion of existing
ADSP-218x applications to the ADSP-219x.
Debugging both C/C++ and assembly programs with the Visu-
alDSP++ debugger, programmers can:View mixed C/C++ and assembly code (interleaved
source and object information)Insert break pointsSet conditional breakpoints on registers, memory, and
stacksTrace instruction executionPerform linear or statistical profiling of program
executionFill, dump, and graphically plot the contents of memorySource level debuggingCreate custom debugger windows
The VisualDSP++ IDE lets programmers define and manage
DSP software development. Its dialog boxes and property pages
let programmers configure and manage all of the ADSP-219x
development tools, including the syntax highlighting in the Visu-
alDSP++ editor. This capability permits:Control how the development tools process inputs and
generate outputs.Maintain a one-to-one correspondence with the tool’s
command line switches.
Analog Devices DSP emulators use the IEEE 1149.1 JTAG test
access port of the ADSP-2191M processor to monitor and
control the target board processor during emulation. The
emulator provides full-speed emulation, allowing inspection and
modification of memory, registers, and processor stacks. Nonin-
trusive in-circuit emulation is assured by the use of the processor’s
JTAG interface—the emulator does not affect target system
ADSP-2191MIn addition to the software and hardware development tools
available from Analog Devices, third parties provide a wide range
of tools supporting the ADSP-219x processor family. Hardware
tools include ADSP-219x PC plug-in cards. Third party software
tools include DSP libraries, real-time operating systems, and
block diagram design tools.
Designing an Emulator-Compatible DSP Board
(Target)The White Mountain DSP (Product Line of Analog Devices,
Inc.) family of emulators are tools that every DSP developer
needs to test and debug hardware and software systems. Analog
Devices has supplied an IEEE 1149.1 JTAG Test Access Port
(TAP) on each JTAG DSP. The emulator uses the TAP to access
the internal features of the DSP, allowing the developer to load
code, set breakpoints, observe variables, observe memory, and
examine registers. The DSP must be halted to send data and
commands, but once an operation has been completed by the
emulator, the DSP system is set running at full speed with no
impact on system timing.
To use these emulators, the target’s design must include the
interface between an Analog Devices JTAG DSP and the
emulation header on a custom DSP target board.
Target Board HeaderThe emulator interface to an Analog Devices JTAG DSP is a
14-pin header, as shown in Figure4. The customer must supply
this header on the target board in order to communicate with the
emulator. The interface consists of a standard dual row 0.025"
square post header, set on 0.1"�0.1" spacing, with a minimum
post length of 0.235". Pin 3 is the key position used to prevent
the pod from being inserted backwards. This pin must be clipped
on the target board.
Also, the clearance (length, width, and height) around the header
must be considered. Leave a clearance of at least 0.15" and 0.10"
around the length and width of the header, and reserve a height
clearance to attach and detach the pod connector.
As can be seen in Figure4, there are two sets of signals on the
header. There are the standard JTAG signals TMS, TCK, TDI,
TDO, TRST, and EMU used for emulation purposes (via an
emulator). There are also secondary JTAG signals BTMS,
BTCK, BTDI, and BTRST that are optionally used for
board-level (boundary scan) testing.
When the emulator is not connected to this header, place jumpers
across BTMS, BTCK, BTRST, and BTDI as shown in Figure5.
This holds the JTAG signals in the correct state to allow the DSP
to run free. Remove all the jumpers when connecting the
emulator to the JTAG header.
JTAG Emulator Pod ConnectorFigure6 details the dimensions of the JTAG pod connector at the
14-pin target end. Figure7 displays the keep-out area for a target
board header. The keep-out area allows the pod connector to
properly seat onto the target board header. This board area
should contain no components (chips, resistors, capacitors, etc.).
The dimensions are referenced to the center of the 0.25" square
post pin.
Figure 5.JTAG Target Board Connector with No Local
Boundary Scan
Design-for-Emulation Circuit InformationFor details on target board design issues including: single
processor connections, multiprocessor scan chains, signal buff-
ering, signal termination, and emulator pod logic, see the EE-68:
Analog Devices JTAG Emulation Technical Reference on the Analog
Devices website ()—use site search on
“EE-68.” This document is updated regularly to keep pace with
improvements to emulator support.
Additional InformationThis data sheet provides a general overview of the ADSP-2191M
architecture and functionality. For detailed information on the
core architecture of the ADSP-219x family, refer to the
ADSP-219x/2191 DSP Hardware Reference. For details on the
instruction set, refer to the ADSP-219x Instruction Set Reference.
PIN FUNCTION DESCRIPTIONSADSP-2191M pin definitions are listed in Table7. All
ADSP-2191M inputs are asynchronous and can be asserted
asynchronously to CLKIN (or to TCK for TRST).
Tie or pull unused inputs to VDDEXT or GND, except for
ADDR21–0, DATA15–0, PF7-0, and inputs that have internal
pull-up or pull-down resistors (TRST, BMODE0, BMODE1,
OPMODE, BYPASS, TCK, TMS, TDI, and RESET)—these
pins can be left floating. These pins have a logic-level hold circuit
that prevents input from floating internally.
The following symbols appear in the Type column of Table: G
= Ground, I=Input, O = Output, P=Power Supply, and T =
Three-State.
Figure 7.JTAG Pod Connector Keep-Out Area
Table 7.Pin Function Descriptions
ADSP-2191M
Table 7.Pin Function Descriptions (continued)
Table 7.Pin Function Descriptions (continued)
ADSP-2191M
SPECIFICATIONS
RECOMMENDED OPERATING CONDITIONS Specifications subject to change without notice.
ELECTRICAL CHARACTERISTICS Specifications subject to change without notice.Applies to output and bidirectional pins: DATA15–0, ADDR21–0, HAD15–0, MS3–0, IOMS, RD, WR, CLKOUT, HACK, PF7–0, TMR2–0, BGH,
BG, DT0, DT1, DT2/MISO0, TCLK0, TCLK1, TCLK2/SCK0, RCLK0, RCLK1, RCLK2/SCK1, TFS0, TFS1, TFS2/MOSI0, RFS0, RFS1,
RFS2/MOSI1, BMS, TDO, TXD, EMU, DR2/MISO1.Applies to input pins: ACK, BR, HCMS, HCIOMS, HA16, HALE, HRD, HWR, CLKIN, DR0, DR1, RXD, HACK_P.Applies to input pins with internal pull-ups: BMODE0, BMODE1, OPMODE, BYPASS, TCK, TMS, TDI, RESET.Applies to input pin with internal pull-down: TRST.Applies to three-statable pins: DATA15–0, ADDR21–0, MS3–0, RD, WR, PF7–0, BMS, IOMS, TFSx, RFSx, TDO, EMU, TCLKx, RCLKx, DTx,
HAD15–0, TMR2–0.Applies to all signal pins.Guaranteed, but not tested.
ABSOLUTE MAXIMUM RATINGS
ESD SENSITIVITY
Power DissipationUsing the operation-versus-current information in Table8, designers can estimate the ADSP-2191M’s internal power supply DDINT) input current for a specific application, according to the formula for IDDINT calculation beneath Table8. For calculation
of external supply current and total supply current, see Power Dissipation on page41.
VDDINT Internal (Core) Supply Voltage1,2. . –0.3 V to 3.0 VSpecifications subject to change without notice.Stresses greater than those listed above may cause permanent damage to the device.
These are stress ratings only; functional operation of the device at these or any
other conditions greater than those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
VDDEXT External (I/O) Supply Voltage. . . . –0.3 V to 4.6 V
VIL–VIH Input Voltage . . . . . . . . –0.5 V to VDDEXT+0.5 VOL–VOH Output Voltage Swing. –0.5 V to VDDEXT+0.5 V
TSTOREStorage Temperature Range . . . . . .–65ºC to 150ºC
TLEADLead Temperature of ST-144 (5 seconds). . . .185ºC
CAUTIONESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V
readily accumulate on the human body and test equipment and can discharge without
detection. Although the ADSP-2191M features proprietary ESD protection circuitry,
permanent damage may occur on devices subjected to high-energy electrostatic
discharges. Therefore, proper ESD precautions are recommended to avoid perfor-
mance degradation or loss of functionality.
Table 8.Operation Types Versus Input CurrentTest conditions: VDDINT= 2.50 V; HCLK (peripheral clock) frequency = CCLK/2 (core clock/2) frequency; TAMB = 25ºC.Test conditions: VDDINT= 2.65 V; HCLK (peripheral clock) frequency = CCLK/2 (core clock/2) frequency; TAMB = 25ºC.PLL, Core, peripheral clocks, and CLKIN are disabled.PLL is enabled and Core and peripheral clocks are disabled.Core CLK is disabled and peripheral clock is enabled. All instructions execute from internal memory. 50% of the instructions are repeat MACs with dual operand addressing, with changing data fetched using
a linear address sequence. 50% of the instructions are type 3 instructions.All instructions execute from internal memory. 100% of the instructions are MACs with dual operand addressing, with changing data fetched using a linear
address sequence.
IDDINT%TypicalIDDINT-TYPICAL×()=%IdleIDDINT-IDLE×()%Power DownIDDINT-PWRDWN×()++
ADSP-2191M
TIMING SPECIFICATIONSThis section contains timing information for the DSP’s external signals. Use the exact information given. Do not attempt to derive
parameters from the addition or subtraction of other information. While addition or subtraction would yield meaningful results for an
individual device, the values given in this datasheet reflect statistical variations and worst cases. Consequently, parameters cannot be
added meaningfully to derive longer times.
Switching characteristics specify how the processor changes its signals. No control is possible over this timing; circuitry external to the
processor must be designed for compatibility with these signal characteristics. Switching characteristics indicate what the processor
will do in a given circumstance. Switching characteristics can also be used to ensure that any timing requirement of a device connected
to the processor (such as memory) is satisfied.
Timing requirements apply to signals that are controlled by circuitry external to the processor, such as the data input for a read
operation.Timing requirements guarantee that the processor operates correctly with other devices.
Clock In and Clock Out Cycle TimingTable9 and Figure8 describe clock and reset operations. Combinations of CLKIN and clock multipliers must not select core/periph-
eral clocks in excess of 160/80 MHz for commercial grade and 140/70 MHz for industrial grade, when the peripheral clock rate is
one-half the core clock rate. If the peripheral clock rate is equal to the core clock rate, the maximum peripheral clock rate is 80 MHz
for both commercial and industrial grade parts. The peripheral clock is supplied to the CLKOUT pins.
When changing from bypass mode to PLL mode, allow 512 HCLK cycles for the PLL to stabilize.
Table 9.Clock In and Clock Out Cycle TimingCLKOUT jitter can be as great as 8 ns when CLKOUT frequency is less than 20 MHz. For frequencies greater than 20 MHz, jitter is less than 1 ns.In clock multiplier mode and MSEL6–0 set for 1:1 (or CLKIN=CCLK), tCK=tCCLK.In bypass mode, tCK=tCCLK.
Figure 8. Clock In and Clock Out Cycle Timing
ADSP-2191M
Programmable Flags Cycle TimingTable10 and Figure9 describe Programmable Flag operations.
Timer PWM_OUT Cycle TimingTable11 and Figure10 describe timer expired operations. The input signal is asynchronous in “width capture mode” and has an
absolute maximum input frequency of 40MHz.
Table 10.Programmable Flags Cycle TimingFigure 9. Programmable Flags Cycle Timing
Table 11.Timer PWM_OUT Cycle TimingThe minimum time for tHTO is one cycle, and the maximum time for tHTO equals (232–1) cycles.
Figure 10. Timer PWM_OUT Cycle Timing
External Port Write Cycle TimingTable12 and Figure11 describe external port write operations.
The external port lets systems extend read/write accesses in three ways: waitstates, ACK input, and combined waitstates and ACK.
To add waits with ACK, the DSP must see ACK low at the rising edge of EMI clock. ACK low causes the DSP to wait, and the DSP
requires two EMI clock cycles after ACK goes high to finish the access. For more information, see the External Port chapter in the
ADSP-219x/2191 DSP Hardware Reference.
Table 12.External Port Write Cycle TimingtHCLK is the peripheral clock period.These are timing parameters that are based on worst-case operating conditions.W = (number of waitstates specified in wait register) � tHCLK.Write hold cycle–memory select control registers (MS � CTL).
ADSP-2191M
External Port Read Cycle TimingTable13 and Figure12 describe external port read operations. For additional information on the ACK signal, see the discussion page23.
Table 13.External Port Read Cycle TimingtHCLK is the peripheral clock period.These are timing parameters that are based on worst-case operating conditions.W = (number of waitstates specified in wait register) � tHCLK.
Figure 12. External Port Read Cycle Timing
External Port Bus Request and Grant Cycle TimingTable14 and Figure13 describe external port bus request and bus grant operations.
Table 14.External Port Bus Request and Grant Cycle TimingtHCLK is the peripheral clock period.These are timing parameters that are based on worst-case operating conditions.
Figure 13. External Port Bus Request and Grant Cycle Timing
ADSP-2191M
Host Port ALE Mode Write Cycle TimingTable15 and Figure14 describe Host port write operations in Address Latch Enable (ALE) mode. For more information on ACK,
Ready, ALE, and ACC mode selection, see the Host port modes description onpage8.
Table 15.Host Port ALE Mode Write Cycle TimingtNH are peripheral bus latencies (n�tHCLK); these are internal DSP latencies related to the number of peripheral DMAs attempting to access DSP memory
at the same time.Measurement is for the second, third, or fourth byte of a host write transaction. The quantity of bytes to complete a host write transaction is dependent on
the data bus size (8 or 16 bits) and the data type (16 or 24 bits).
