ADSP-2188M ,16-bit, 75 MIPS, 2.75v, 2 Serial Ports, Host Port, 256 KB RAMSPECIFICATIONS . . . . . . . . . . . . . . . . . . . . 21Common-Mode Pins . . . . . . . . . . . . . ..
ADSP-2188N ,16-Bit, 80MIPS, 1.8V, 2 Serial Ports, Host Port, 256KB RAMGENERAL DESCRIPTION This takes place while the processor continues to:The ADSP-218xN series consist ..
ADSP-2188NBST-320 ,DSP MicrocomputerGENERAL DESCRIPTION This takes place while the processor continues to:The ADSP-218xN series consist ..
ADSP2188NBST-320 ,DSP Microcomputerfeatures: units process 16-bit data directly and have provisions to support multiprecision computat ..
ADSP-2188NKST-320 ,DSP Microcomputeroverview of ADSP- Result (R) Bus218xN series functionality. For additional information on The two ..
ADSP-2189M ,16-bit, 75 MIPS, 2.5v, 2 serial ports, host port, 192 KB RAMapplications.SYSTEM INTERFACEFlexible I/O Structure Allows 2.5 V or 3.3 V Operation;The ADSP-2189M ..
AM26C31CD ,Quadruple Differential Line DriverFeatures section and added the Applications section, the Device Information table, ESD Ratings tabl ..
AM26C31CDB , QUADRUPLE DIFFERENTIAL LINE DRIVERS
AM26C31CDBR ,Quadruple Differential Line DriverElectrical Characteristics: AM26C31Q and12 Device and Documentation Support........ 15AM26C31M. 612 ..
AM26C31CDBRG4 ,Quadruple Differential Line Driver 16-SSOP 0 to 70Features 3 DescriptionThe AM26C31 device is a differential line driver with1• Meets or Exceeds the ..
AM26C31CDG4 ,Quadruple Differential Line Driver 16-SOIC 0 to 70Block Diagrams. 103 Description....... 18.3 Feature Description.... 114 Revision History........ 28 ..
AM26C31CDR ,Quadruple Differential Line DriverMaximum Ratings . 49.2 Typical Application .... 126.2 ESD Ratings........ 410 Power Supply Recommen ..
ADSP-2188M
16-bit, 75 MIPS, 2.75v, 2 Serial Ports, Host Port, 256 KB RAM
SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . 21Common-Mode Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6ENVIRONMENTAL CONDITIONS . . . . . . . . . . . . . . . 21Memory Interface Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . 7POWER DISSIPATION . . . . . . . . . . . . . . . . . . . . . . . . . . 21Full Memory Mode Pins (Mode C = 0) . . . . . . . . . . . . . . 7Output Drive Currents . . . . . . . . . . . . . . . . . . . . . . . . . . 21Host Mode Pins (Mode C = 1) . . . . . . . . . . . . . . . . . . . . 7Capacitive Loading . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22Terminating Unused Pins . . . . . . . . . . . . . . . . . . . . . . . . 8TEST CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . 23Pin Terminations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8Output Disable Time . . . . . . . . . . . . . . . . . . . . . . . . . . . 23Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9Output Enable Time . . . . . . . . . . . . . . . . . . . . . . . . . . . 23LOW POWER OPERATION . . . . . . . . . . . . . . . . . . . . . . . 9Clock Signals and Reset . . . . . . . . . . . . . . . . . . . . . . . . . 24Power-Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9Interrupts and Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25Idle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9Bus Request–Bus Grant . . . . . . . . . . . . . . . . . . . . . . . . . 26Slow Idle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9Memory Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27SYSTEM INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . 10Memory Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28Clock Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10Serial Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11IDMA Address Latch . . . . . . . . . . . . . . . . . . . . . . . . . . . 30Power Supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11IDMA Write, Short Write Cycle . . . . . . . . . . . . . . . . . . 31MODES OF OPERATION . . . . . . . . . . . . . . . . . . . . . . . 11IDMA Write, Long Write Cycle . . . . . . . . . . . . . . . . . . . 32Setting Memory Mode . . . . . . . . . . . . . . . . . . . . . . . . . . 11IDMA Read, Long Read Cycle . . . . . . . . . . . . . . . . . . . 33Passive Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . 11IDMA Read, Short Read Cycle . . . . . . . . . . . . . . . . . . . 34Active Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . 11IDMA Read, Short Read Cycle in Short ReadIACK Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . 12Only Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35MEMORY ARCHITECTURE . . . . . . . . . . . . . . . . . . . . . 12100-LEAD LQFP PIN CONFIGURATION . . . . . . . . . . 36Program Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12LQFP Package Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37Data Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13144-Ball Mini-BGA Package Pinout . . . . . . . . . . . . . . . . . 38Memory Mapped Registers (New to theMini-BGA Package Pinout . . . . . . . . . . . . . . . . . . . . . . . . 39ADSP-2188M) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13OUTLINE DIMENSIONSI/O Space (Full Memory Mode) . . . . . . . . . . . . . . . . . . . 14100-Lead Metric Thin Plastic Quad FlatpackComposite Memory Select (CMS) . . . . . . . . . . . . . . . . . 14 (LQFP) (ST-100) . . . . . . . . . . . . . . . . . . . . . . . . . . . 40Byte Memory Select (BMS) . . . . . . . . . . . . . . . . . . . . . . 14OUTLINE DIMENSIONSByte Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14144-Ball Mini-BGA (CA-144) . . . . . . . . . . . . . . . . . . . . 40Byte Memory DMA (BDMA, Full Memory Mode) . . . . 14ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40Internal Memory DMA Port(IDMA Port; Host Memory Mode) . . . . . . . . . . . . . . 15 TablesBootstrap Loading (Booting) . . . . . . . . . . . . . . . . . . . . . 16 Table I. Interrupt Priority and InterruptIDMA Port Booting . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Vector Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9Bus Request and Bus Grant . . . . . . . . . . . . . . . . . . . . . . 16 Table II. Modes of Operation . . . . . . . . . . . . . . . . . . . . . . 11Flag I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Table III. PMOVLAY Bits . . . . . . . . . . . . . . . . . . . . . . . . 12Instruction Set Description . . . . . . . . . . . . . . . . . . . . . . 17 Table IV. DMOVLAY Bits . . . . . . . . . . . . . . . . . . . . . . . . 13DESIGNING AN EZ-ICE-COMPATIBLE SYSTEM . . . 17 Table V. Wait States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14Target Board Connector for EZ-ICE Probe . . . . . . . . . . 18 Table VI. Data Formats . . . . . . . . . . . . . . . . . . . . . . . . . . 14Target Memory Interface . . . . . . . . . . . . . . . . . . . . . . . . 18PM, DM, BM, IOM, AND CM . . . . . . . . . . . . . . . . . . . . 18Target System Interface Signals . . . . . . . . . . . . . . . . . . . 18–2– REV. 0ADSP-2188M
