ADSP-2187LBST160 ,16-bit, 52 MIPS, 3.3v, 2 Serial Ports, Host Port, 160 KB RAMapplications.SYSTEM INTERFACE16-Bit Internal DMA Port for High Speed Access to The ADSP-2187L combi ..
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ADSP-2187LBST160
16-bit, 52 MIPS, 3.3v, 2 Serial Ports, Host Port, 160 KB RAM
DSP MicrocomputerICE-Port is a trademark of Analog Devices, Inc.
GENERAL NOTEThis data sheet represents specifications for the ADSP-2187L
3.3 V processor.
GENERAL DESCRIPTIONThe ADSP-2187L is a single-chip microcomputer optimized for
digital signal processing (DSP) and other high speed numeric
processing applications.
The ADSP-2187L combines the ADSP-2100 family base archi-
tecture (three computational units, data address generators and
a program sequencer) with two serial ports, a 16-bit internal
DMA port, a byte DMA port, a programmable timer, Flag I/O,
extensive interrupt capabilities and on-chip program and data
memory.
The ADSP-2187L integrates 160K bytes of on-chip memory
configured as 32K words (24-bit) of program RAM, and 32K
words (16-bit) of data RAM. Power-down circuitry is also pro-
vided to meet the low power needs of battery operated portable
equipment. The ADSP-2187L is available in 100-lead TQFP
package.
In addition, the ADSP-2187L supports new instructions, which
include bit manipulations—bit set, bit clear, bit toggle, bit test—
new ALU constants, new multiplication instruction (x squared),
biased rounding, result free ALU operations, I/O memory trans-
fers and global interrupt masking, for increased flexibility.
Fabricated in a high speed, low power, CMOS process, the
ADSP-2187L operates with a 19 ns instruction cycle time. Ev-
ery instruction can execute in a single processor cycle.
FEATURES
PERFORMANCE
19 ns Instruction Cycle Time @ 3.3 Volts, 52 MIPS
Sustained Performance
Single-Cycle Instruction Execution
Single-Cycle Context Switch
3-Bus Architecture Allows Dual Operand Fetches in
Every Instruction Cycle
Multifunction Instructions
Power-Down Mode Featuring Low CMOS Standby
Power Dissipation with 400 Cycle Recovery from
Power-Down Condition
Low Power Dissipation in Idle Mode
INTEGRATION
ADSP-2100 Family Code Compatible, with Instruction
Set Extensions
160K Bytes of On-Chip RAM, Configured as 32K Words
Program Memory RAM and 32K Words
Data Memory RAM
Dual Purpose Program Memory for Instruction␣and Data
Storage
Independent ALU, Multiplier/Accumulator and Barrel
Shifter Computational Units
Two Independent Data Address Generators
Powerful Program Sequencer Provides Zero Overhead
Looping Conditional Instruction Execution
Programmable 16-Bit Interval Timer with Prescaler
100-Lead TQFP
SYSTEM INTERFACE
16-Bit Internal DMA Port for High Speed Access to
On-Chip Memory (Mode Selectable)
4 MByte Memory Interface for Storage of Data Tables
and Program Overlays (Mode Selectable)
8-Bit DMA to Byte Memory for Transparent Program
and Data Memory Transfers (Mode Selectable)
I/O Memory Interface with 2048 Locations Supports
Parallel Peripherals (Mode Selectable)
Programmable Memory Strobe and Separate I/O Memory
Space Permits “Glueless” System Design
Programmable Wait State Generation
Two Double-Buffered Serial Ports with Companding
Hardware and Automatic Data Buffering
Automatic Booting of On-Chip Program Memory from
Byte-Wide External Memory, e.g., EPROM, or
Through Internal DMA Port
Six External Interrupts
13 Programmable Flag Pins Provide Flexible System
Signaling
UART Emulation through Software SPORT Reconfiguration
ICE-Port™ Emulator Interface Supports Debugging in
Final Systems
FUNCTIONAL BLOCK DIAGRAM
ADSP-2187LThe ADSP-2187L’s flexible architecture and comprehensive in-
struction set allow the processor to perform multiple operations
in parallel. In one processor cycle the ADSP-2187L can:Generate the next program addressFetch the next instructionPerform one or two data movesUpdate one or two data address pointersPerform a computational operation
This takes place while the processor continues to:Receive and transmit data through the two serial portsReceive and/or transmit data through the internal DMA portReceive and/or transmit data through the byte DMA portDecrement timer
DEVELOPMENT SYSTEMThe ADSP-2100 Family Development Software, a complete set
of tools for software and hardware system development, sup-
ports the ADSP-2187L. The System Builder provides a high
level method for defining the architecture of systems under de-
velopment. The Assembler has an algebraic syntax that is easy
to program and debug. The Linker combines object files into an
executable file. The Simulator provides an interactive instruc-
tion-level simulation with a reconfigurable user interface to dis-
play different portions of the hardware environment.
A PROM Splitter generates PROM programmer compatible
files. The C Compiler, based on the Free Software Foundation’s
GNU C Compiler, generates ADSP-2187L assembly source
code. The source code debugger allows programs to be cor-
rected in the C environment. The Runtime Library includes over
100 ANSI-standard mathematical and DSP-specific functions.
The EZ-KIT Lite is a hardware/software kit offering a complete
development environment for the entire ADSP-21xx family: an
ADSP-218x based evaluation board with PC monitor software
plus Assembler, Linker, Simulator, and PROM Splitter soft-
ware. The ADSP-218x EZ-KIT Lite is a low cost, easy to use
hardware platform on which you can quickly get started with
your DSP software design. The EZ-KIT Lite includes the fol-
lowing features:33 MHz ADSP-218xFull 16-bit Stereo Audio I/O with AD1847 SoundPort® CodecRS-232 Interface to PC with Windows 3.1 Control SoftwareEZ-ICE® Connector for Emulator ControlDSP Demo Programs
The ADSP-218x EZ-ICE Emulator aids in the hardware debug-
ging of ADSP-2187L system. The emulator consists of hard-
ware, host computer resident software and the target board
connector. The ADSP-2187L integrates on-chip emulation sup-
port with a 14-pin ICE-Port interface. This interface provides a
simpler target board connection requiring fewer mechanical
clearance considerations than other ADSP-2100 Family
EZ-ICEs. The ADSP-2187L device need not be removed from
the target system when using the EZ-ICE, nor are any adapters
needed. Due to the small footprint of the EZ-ICE connector, emu-
lation can be supported in final board designs.
The EZ-ICE performs a full range of functions, including:Registers and memory values can be examined and alteredPC upload and download functionsInstruction-level emulation of program booting and executionComplete assembly and disassembly of instructionsC source-level debugging
See “Designing An EZ-ICE-Compatible Target System” in the
ADSP-2100 Family EZ-Tools Manual (ADSP-2181 sections) as
well as the Designing an EZ-ICE Compatible System section of
this data sheet for the exact specifications of the EZ-ICE target
board connector.
Additional InformationThis data sheet provides a general overview of ADSP-2187L
functionality. For additional information on the architecture and
instruction set of the processor, see the ADSP-2100 Family
User’s Manual, Third Edition. For more information about the
development tools, refer to the ADSP-2100 Family Develop-
ment Tools Data Sheet.
ARCHITECTURE OVERVIEWThe ADSP-2187L instruction set provides flexible data moves
and multifunction (one or two data moves with a computation)
instructions. Every instruction can be executed in a single pro-
cessor cycle. The ADSP-2187L assembly language uses an alge-
braic syntax for ease of coding and readability. A comprehensive
set of development tools supports program development.
Figure 1.Functional Block Diagram
Figure 1 is an overall block diagram of the ADSP-2187L. The
processor contains three independent computational units: the
ALU, the multiplier/accumulator (MAC) and the shifter. The
computational units process 16-bit data directly and have provi-
sions to support multiprecision computations. The ALU per-
forms a standard set of arithmetic and logic operations; division
primitives are also supported. The MAC performs single-cycle
multiply, multiply/add and multiply/subtract operations with
40 bits of accumulation. The shifter performs logical and arith-
metic shifts, normalization, denormalization and derive expo-
nent operations.
The shifter can be used to efficiently implement numeric for-
mat control including multiword and block floating-point
representations.
The internal result (R) bus connects the computational units so
A powerful program sequencer and two dedicated data address
generators ensure efficient delivery of operands to these computa-
tional units. The sequencer supports conditional jumps, subroutine
calls and returns in a single cycle. With internal loop counters and
loop stacks, the ADSP-2187L executes looped code with zero over-
head; no explicit jump instructions are required to maintain loops.
Two data address generators (DAGs) provide addresses for
simultaneous dual operand fetches (from data memory and pro-
gram memory). Each DAG maintains and updates four address
pointers. Whenever the pointer is used to access data (indirect
addressing), it is post-modified by the value of one of four pos-
sible modify registers. A length value may be associated with
each pointer to implement automatic modulo addressing for
circular buffers.
Efficient data transfer is achieved with the use of five internal
buses:Program Memory Address (PMA) BusProgram Memory Data (PMD) BusData Memory Address (DMA) BusData Memory Data (DMD) BusResult (R) Bus
The two address buses (PMA and DMA) share a single external
address bus, allowing memory to be expanded off-chip, and the
two data buses (PMD and DMD) share a single external data
bus. Byte memory space and I/O memory space also share the
external buses.
Program memory can store both instructions and data, permit-
ting the ADSP-2187L to fetch two operands in a single cycle,
one from program memory and one from data memory. The
ADSP-2187L can fetch an operand from program memory and
the next instruction in the same cycle.
In lieu of the address and data bus for external memory connec-
tion, the ADSP-2187L may be configured for 16-bit Internal
DMA port (IDMA port) connection to external systems. The
IDMA port is made up of 16 data/address pins and five control
pins. The IDMA port provides transparent, direct access to the
DSPs on-chip program and data RAM.
An interface to low cost byte-wide memory is provided by the
Byte DMA port (BDMA port). The BDMA port is bidirectional
and can directly address up to four megabytes of external RAM
or ROM for off-chip storage of program overlays or data tables.
The byte memory and I/O memory space interface supports slow
memories and I/O memory-mapped peripherals with program-
mable wait state generation. External devices can gain control of
external buses with bus request/grant signals (BR, BGH, and BG).
One execution mode (Go Mode) allows the ADSP-2187L to con-
tinue running from on-chip memory. Normal execution mode re-
quires the processor to halt while buses are granted.
The ADSP-2187L can respond to eleven interrupts. There can
be up to six external interrupts (one edge-sensitive, two level-
sensitive and three configurable) and seven internal interrupts
generated by the timer, the serial ports (SPORTs), the Byte
DMA port and the power-down circuitry. There is also a masterRESET signal. The two serial ports provide a complete synchro-
nous serial interface with optional companding in hardware and a
wide variety of framed or frameless data transmit and receive
The ADSP-2187L provides up to 13 general-purpose flag pins.
The data input and output pins on SPORT1 can be alternatively
configured as an input flag and an output flag. In addition, there
are eight flags that are programmable as inputs or outputs and
three flags that are always outputs.
A programmable interval timer generates periodic interrupts. A
16-bit count register (TCOUNT) is decremented every n pro-
cessor cycle, where n is a scaling value stored in an 8-bit register
(TSCALE). When the value of the count register reaches zero,
an interrupt is generated and the count register is reloaded from
a 16-bit period register (TPERIOD).
Serial PortsThe ADSP-2187L incorporates two complete synchronous se-
rial ports (SPORT0 and SPORT1) for serial communications
and multiprocessor communication.
Here is a brief list of the capabilities of the ADSP-2187L
SPORTs. For additional information on Serial Ports, refer to
the ADSP-2100 Family User’s Manual, Third Edition.SPORTs are bidirectional and have a separate, double-
buffered transmit and receive section.SPORTs can use an external serial clock or generate their
own serial clock internally.SPORTs have independent framing for the receive and trans-
mit sections. Sections run in a frameless mode or with frame
synchronization signals internally or externally generated.
Frame sync signals are active high or inverted, with either of
two pulsewidths and timings.SPORTs support serial data word lengths from 3 to 16 bits
and provide optional A-law and m-law companding according
to CCITT recommendation G.711.SPORT receive and transmit sections can generate unique in-
terrupts on completing a data word transfer.SPORTs can receive and transmit an entire circular buffer of
data with only one overhead cycle per data word. An interrupt
is generated after a data buffer transfer.SPORT0 has a multichannel interface to selectively receive
and transmit a 24- or 32-word, time-division multiplexed,
serial bitstream.SPORT1 can be configured to have two external interrupts
(IRQ0 and IRQ1) and the Flag In and Flag Out signals. The
internally generated serial clock may still be used in this
configuration.
PIN DESCRIPTIONSThe ADSP-2187L will be available in a 100-lead TQFP pack-
age. In order to maintain maximum functionality and reduce
package size and pin count, some serial port, programmable
flag, interrupt and external bus pins have dual, multiplexed
functionality. The external bus pins are configured duringRESET only, while serial port pins are software configurable
during program execution. Flag and interrupt functionality is re-
tained concurrently on multiplexed pins. In cases where pin
functionality is reconfigurable, the default state is shown in plain
text; alternate functionality is shown in italics. See Common-
ADSP-2187LNOTESInterrupt/Flag Pins retain both functions concurrently. If IMASK is set to en-
able the corresponding interrupts, then the DSP will vector to the appropriate
interrupt vector address when the pin is asserted, either by external devices, or
set as a programmable flag.SPORT configuration determined by the DSP System Control Register. Soft-
ware configurable.
Memory Interface PinsThe ADSP-2187L processor can be used in one of two modes,
Full Memory Mode, which allows BDMA operation with full
external overlay memory and I/O capability, or Host Mode,
which allows IDMA operation with limited external addressing
capabilities. The operating mode is determined by the state of
the Mode C pin during RESET and cannot be changed while
the processor is running. See tables for Full Memory Mode Pins
and Host Mode Pins for descriptions.
Full Memory Mode Pins (Mode C = 0)
Host Mode Pins (Mode C = 1)In Host Mode, external peripheral addresses can be decoded using the A0,
CMS, PMS, DMS and IOMS signals
Terminating Unused PinThe following table shows the recommendations for terminating
unused pins.
Pin Terminations
PinIAD12:0
Common-Mode Pin Descriptions
IRD
D5 or
IAL
D4 or
D3 or
IACK
D2:0 or
IAD15:13
PMS
DMS
BMS
IOMS
CMS
BGH
IRQ2/PF7
IRQL0/PF6
IRQL1/PF5
IRQE/PF5
SCLK0
RFS0
DR0
TFS0
DT0
SCLK1
RFS1/RQ0
DR1/FI
TFS1/RQ1
DT1/FO
EBR
EBG
ERESET
EMS
EINT
ECLK
ELIN
NOTES
**Hi-Z = High Impedance.
**Determined by MODE D pin:
Mode D = 0 and in host mode: IACK is an active, driven signal and cannot be
“wire ORed.” If unused, let float.
Mode D = 1 and in host mode: IACK is an open source and requires an exter-
nal pull-down, but multiple IACK pins can be “wire ORed” together. If un-
used, let float.If the CLKOUT pin is not used, turn it OFF.
2.If the Interrupt/Programmable Flag pins are not used, there are two options:
Option 1: When these pins are configured as INPUTS at reset and function as
interrupts and input flag pins, pull the pins High (inactive).
Option 2: Program the unused pins as OUTPUTS, set them to 1, and let them
float.
3.All bidirectional pins have three-stated outputs. When the pins is configured as
an output, the output is Hi-Z (high impedance) when inactive.
4.CLKIN, RESET, and PF3:0 are not included in the table because these pins
must be used.
InterruptsThe interrupt controller allows the processor to respond to the
eleven possible interrupts and reset with minimum overhead.
The ADSP-2187L provides four dedicated external interrupt
input pins, IRQ2, IRQL0, IRQL1 and IRQE. In addition,
SPORT1 may be reconfigured for IRQ0, IRQ1, FLAG_IN and
FLAG_OUT, for a total of six external interrupts. The ADSP-
2187L also supports internal interrupts from the timer, the byte
DMA port, the two serial ports, software and the power-down
control circuit. The interrupt levels are internally prioritized and
individually maskable (except power down and reset). TheIRQ2, IRQ0 and IRQ1 input pins can be programmed to be
either level- or edge-sensitive. IRQL0 and IRQL1 are level-
sensitive and IRQE is edge sensitive. The priorities and vector
addresses of all interrupts are shown in Table I.
Table I.Interrupt Priority and Interrupt Vector AddressesInterrupt routines can either be nested with higher priority inter-
rupts taking precedence or processed sequentially. Interrupts
can be masked or unmasked with the IMASK register. Indi-
vidual interrupt requests are logically ANDed with the bits in
IMASK; the highest priority unmasked interrupt is then se-
lected. The power-down interrupt is nonmaskable.
The ADSP-2187L masks all interrupts for one instruction cycle
following the execution of an instruction that modifies the
IMASK register. This does not affect serial port auto-
buffering or DMA transfers.
The interrupt control register, ICNTL, controls interrupt nest-
ing and defines the IRQ0, IRQ1 and IRQ2 external interrupts to
be either edge- or level-sensitive. The IRQE pin is an external
edge-sensitive interrupt and can be forced and cleared. TheIRQL0 and IRQL1 pins are external level-sensitive interrupts.
ADSP-2187LThe IFC register is a write-only register used to force and clear
interrupts. On-chip stacks preserve the processor status and are
automatically maintained during interrupt handling. The stacks
are twelve levels deep to allow interrupt, loop and subroutine
nesting. The following instructions allow global enable or dis-
able servicing of the interrupts (including power down), regard-
less of the state of IMASK. Disabling the interrupts does not
affect serial port autobuffering or DMA.
ENA INTS;
DIS INTS;
When the processor is reset, interrupt servicing is enabled.
LOW POWER OPERATIONThe ADSP-2187L has three low power modes that significantly
reduce the power dissipation when the device operates under
standby conditions. These modes are:Power-DownIdleSlow Idle
The CLKOUT pin may also be disabled to reduce external
power dissipation.
Power-DownThe ADSP-2187L processor has a low power feature that lets
the processor enter a very low power dormant state through
hardware or software control. Here is a brief list of power-down
features. Refer to the ADSP-2100 Family User’s Manual, Third
Edition, “System Interface” chapter, for detailed information
about the power-down feature.Quick recovery from power-down. The processor begins ex-
ecuting instructions in as few as 400 CLKIN cycles.Support for an externally generated TTL or CMOS processor
clock. The external clock can continue running during power-
down without affecting the 400 CLKIN cycle recovery.Support for crystal operation includes disabling the oscillator
to save power (the processor automatically waits 4096 CLKIN
cycles for the crystal oscillator to start and stabilize), and let-
ting the oscillator run to allow 400 CLKIN cycle start up.Power-down is initiated by either the power-down pin (PWD)
or the software power-down force bit Interrupt support allows
an unlimited number of instructions to be executed before op-
tionally powering down. The power-down interrupt also can
be used as a non-maskable, edge-sensitive interrupt.Context clear/save control allows the processor to continue
where it left off or start with a clean context when leaving the
power-down state.The RESET pin also can be used to terminate power- down.Power-down acknowledge pin indicates when the processor
has entered power-down.
IdleWhen the ADSP-2187L is in the Idle Mode, the processor waits
indefinitely in a low power state until an interrupt occurs. When
an unmasked interrupt occurs, it is serviced; execution then con-
tinues with the instruction following the IDLE instruction. In
Slow IdleThe IDLE instruction on the ADSP-2187L slows the processor’s
internal clock signal, further reducing power consumption. The
reduced clock frequency, a programmable fraction of the nor-
mal clock rate, is specified by a selectable divisor given in the
IDLE instruction. The format of the instruction is
IDLE (n);
where n = 16, 32, 64 or 128. This instruction keeps the proces-
sor fully functional, but operating at the slower clock rate. While
it is in this state, the processor’s other internal clock signals,
such as SCLK, CLKOUT and timer clock, are reduced by the
same ratio. The default form of the instruction, when no clock
divisor is given, is the standard IDLE instruction.
When the IDLE (n) instruction is used, it effectively slows down
the processor’s internal clock and thus its response time to in-
coming interrupts. The one-cycle response time of the standard
idle state is increased by n, the clock divisor. When an enabled
interrupt is received, the ADSP-2187L will remain in the idle
state for up to a maximum of n processor cycles (n = 16, 32, 64
or 128) before resuming normal operation.
When the IDLE (n) instruction is used in systems that have an
externally generated serial clock (SCLK), the serial clock rate
may be faster than the processor’s reduced internal clock rate.
Under these conditions, interrupts must not be generated at a
faster rate than can be serviced, due to the additional time the
processor takes to come out of the idle state (a maximum of n
processor cycles).
SYSTEM INTERFACEFigure 2 shows a typical basic system configuration with the
ADSP-2187L, two serial devices, a byte-wide EPROM, and
optional external program and data overlay memories (mode se-
lectable). Programmable wait state generation allows the proces-
sor to connect easily to slow peripheral devices. The ADSP-2187L
also provides four external interrupts and two serial ports or six
external interrupts and one serial port. Host Memory Mode al-
lows access to the full external data bus, but limits addressing to
a single address bit (A0) Additional system peripherals can be
added in this mode through the use of external hardware to gen-
erate and latch address signals.
Clock SignalsThe ADSP-2187L can be clocked by either a crystal or a TTL-
compatible clock signal.
The CLKIN input cannot be halted, changed during operation
or operated below the specified frequency during normal opera-
tion. The only exception is while the processor is in the power-
down state. For additional information, refer to Chapter 9,
ADSP-2100 Family User’s Manual, Third Edition, for detailed in-
formation on this power-down feature.
If an external clock is used, it should be a TTL-compatible sig-
nal running at half the instruction rate. The signal is connected
to the processor’s CLKIN input. When an external clock is
used, the XTAL input must be left unconnected.
Figure 2.ADSP-2187L Basic System Configuration
The ADSP-2187L uses an input clock with a frequency equal to
half the instruction rate; a 26.00 MHz input clock yields a 19 ns
processor cycle (which is equivalent to 52 MHz). Normally, in-
structions are executed in a single processor cycle. All device tim-
ing is relative to the internal instruction clock rate, which is
indicated by the CLKOUT signal when enabled.
Because the ADSP-2187L includes an on-chip oscillator circuit,
an external crystal may be used. The crystal should be connected
across the CLKIN and XTAL pins, with two capacitors connected
as shown in Figure 3. Capacitor values are dependent on crystal
type and should be specified by the crystal manufacturer. A
parallel-resonant, fundamental frequency, microprocessor-grade
crystal should be used.
A clock output (CLKOUT) signal is generated by the processor
at the processor’s cycle rate. This can be enabled and disabled
by the CLK0DIS bit in the SPORT0 Autobuffer Control Register.
Figure 3.External Crystal Connections
ResetThe RESET signal initiates a master reset of the ADSP-2187L.
The RESET signal must be asserted during the power-up se-
quence to assure proper initialization. RESET during initial
power-up must be held long enough to allow the internal clock
to stabilize. If RESET is activated any time after power-up, the
clock continues to run and does not require stabilization time.
The power-up sequence is defined as the total time required for
the crystal oscillator circuit to stabilize after a valid VDD is ap-
plied to the processor, and for the internal phase-locked loop
(PLL) to lock onto the specific crystal frequency. A minimum
of 2000 CLKIN cycles ensures that the PLL has locked, but
does not include the crystal oscillator start-up time. During this
power-up sequence the RESET signal should be held low. On
any subsequent resets, the RESET signal must meet the mini-
mum pulsewidth specification, tRSP.
The RESET input contains some hysteresis; however, if an
RC circuit is used to generate the RESET signal, an external
Schmidt trigger is recommended.
The master reset sets all internal stack pointers to the empty
stack condition, masks all interrupts and clears the MSTAT
register. When RESET is released, if there is no pending bus
request and the chip is configured for booting, the boot-loading
sequence is performed. The first instruction is fetched from
on-chip program memory location 0x0000 once boot loading
completes.
ADSP-2187L
Table II.Modes of Operations1NOTESAll mode pins are recognized while RESET is active (low).When Mode D = 0 and in host mode, IACK is an active, driven signal and cannot be “wire ORed”.
When Mode D = 1 and in host mode, IACK is an open source and requires an external pull-down, multiple IACK pins can be “wire ORed” together.When Mode C = 0, Full Memory enabled. When Mode C = 1, Host Memory Mode enabled.When Mode B = 0, Auto Booting enabled. When Mode B = 1, no Auto Booting.When Mode A = 0, BDMA enabled. When Mode A = 1, IDMA enabled.Considered as standard operating settings. Using these configurations allows for easier design and better memory management.
MODES OF OPERATIONTable II summarizes the ADSP-2187L memory modes.
Setting Memory ModeMemory Mode selection for the ADSP-2187L is made during
chip reset through the use of the Mode C pin. This pin is multi-
plexed with the DSP’s PF2 pin, so care must be taken in how
the mode selection is made. The two methods for selecting the
value of Mode C are active and passive.
Passive configuration involves the use a pull-up or pull-downresistor connected to the Mode C pin. To minimize power con-
sumption, or if the PF2 pin is to be used as an output in the
DSP application, a weak pull-up or pull-down, on the order of
100 kW, can be used. This value should be sufficient to pull the
pin to the desired level and still allow the pin to operate as
a programmable flag output without undue strain on the
processor’s output driver. For minimum power consumption
during power-down, reconfigure PF2 to be an input, as the
pull-up or pull-down will hold the pin in a known state, and
will not switch.
Active configuration involves the use of a three-statable ex-ternal driver connected to the Mode C pin. A driver’s output
enable should be connected to the DSP’s RESET signal such
that it only drives the PF2 pin when RESET is active (low).
When RESET is deasserted, the driver should three-state, thus
allowing full use of the PF2 pin as either an input or output. To
minimize power consumption during power-down, configure
the programmable flag as an output when connected to a three-
stated buffer. This ensures that the pin will be held at a constant
level and not oscillate should the three-state driver’s level hover
around the logic switching point.
MEMORY ARCHITECTUREThe ADSP-2187L provides a variety of memory and peripheral
interface options. The key functional groups are Program
Memory, Data Memory, Byte Memory, and I/O. Refer to the
following figures and tables for PM and DM memory alloca-
tions in the ADSP-2187L.
PROGRAM MEMORY
Program Memory (Full Memory Mode) is a 24-bit-widespace for storing both instruction opcodes and data. The ADSP-
2187L has 32K words of Program Memory RAM on chip, and
the capability of accessing up to two 8K external memory over-
lay spaces using the external data bus.
IACK ConfigurationMode D = 0 and in host Mode: IACK is an active, driven signal
and cannot be “wire ORed.”
Mode D = 1 and in host mode: IACK is an open source and re-
quires an external pull-down, but multiple IACK pins can be
INTERNAL
MEMORY
EXTERNAL
MEMORY
033FFF2
PM (MODE B = 0)
PROGRAM MEMORY
MODE B = 1ADDRESS
PROGRAM MEMORY
MODE B = 0ADDRESSINTERNAL
MEMORY
EXTERNAL
MEMORY
PM (MODE B = 1)1
1WHEN MODE B = 1, PMOVLAY MUST BE SET TO 0
2SEE TABLE III FOR PMOVLAY BITSFigure 4.Program Memory
Program Memory (Host Mode) allows access to all internalmemory. External overlay access is limited by a single external
address line (A0). External program execution is not available
in host mode due to a restricted data bus that is 16-bits wide
only.
Table III.PMOVLAY Bits
DATA MEMORY
Data Memory (Full Memory Mode) is a 16-bit-wide spaceused for the storage of data variables and for memory-mapped
control registers. The ADSP-2187L has 32K words on Data
Memory RAM on chip, consisting of 16,352 user-accessible lo-
cations and 32 memory-mapped registers. Support also exists
for up to two 8K external memory overlay spaces through the
external data bus. All internal accesses complete in one cycle.
Accesses to external memory are timed using the wait states
specified by the DWAIT register.
Figure 5.Data Memory Map
Data Memory (Host Mode) allows access to all internal memory.
External overlay access is limited by a single external address line
(A0). The DMOVLAY bits are defined in Table IV.
Table IV.DMOVLAY Bits
ADSP-2187L
Byte MemoryThe byte memory space is a bidirectional, 8-bit-wide, external
memory space used to store programs and data. Byte memory is
accessed using the BDMA feature. The BDMA Control Register is
shown in Figure 7. The byte memory space consists of 256 pages,
each of which is 16K · 8.
The byte memory space on the ADSP-2187L supports read and
write operations as well as four different data formats. The byte
memory uses data bits 15:8 for data. The byte memory uses
data bits 23:16 and address bits 13:0 to create a 22-bit address.
This allows up to a 4 meg · 8 (32 megabit) ROM or RAM to be
used without glue logic. All byte memory accesses are timed by
the BMWAIT register.
Byte Memory DMA (BDMA, Full Memory Mode)The Byte memory DMA controller allows loading and storing of
program instructions and data using the byte memory space.
The BDMA circuit is able to access the byte memory space
while the processor is operating normally, and steals only one
DSP cycle per 8-, 16- or 24-bit word transferred.
Figure 7.BDMA Control Register
The BDMA circuit supports four different data formats that are
selected by the BTYPE register field. The appropriate number
of 8-bit accesses are done from the byte memory space to build
the word size selected. Table VI shows the data formats sup-
ported by the BDMA circuit.
Table VI.Data FormatsUnused bits in the 8-bit data memory formats are filled with 0s.
The BIAD register field is used to specify the starting address
for the on-chip memory involved with the transfer. The 14-bit
BEAD register specifies the starting address for the external
byte memory space. The 8-bit BMPAGE register specifies the
starting page for the external byte memory space. The BDIR
register field selects the direction of the transfer. Finally the 14-
bit BWCOUNT register specifies the number of DSP words to
transfer and initiates the BDMA circuit transfers.
I/O Space (Full Memory Mode)The ADSP-2187L supports an additional external memory
space called I/O space. This space is designed to support simple
connections to peripherals (such as data converters and external
registers) or to bus interface ASIC data registers. I/O space sup-
ports 2048 locations of 16-bit wide data. The lower eleven bits
of the external address bus are used; the upper three bits are un-
defined. Two instructions were added to the core ADSP-2100
Family instruction set to read from and write to I/O memory
space. The I/O space also has four dedicated 3-bit wait state
registers, IOWAIT0-3, that specify up to seven wait states to be
automatically generated for each of four regions. The wait states
act on address ranges as shown in Table V.
Table V.Wait States
Composite Memory Select (CMS)The ADSP-2187L has a programmable memory select signal
that is useful for generating memory select signals for memories
mapped to more than one space. The CMS signal is generated
to have the same timing as each of the individual memory select
signals (PMS, DMS, BMS, IOMS) but can combine their
functionality.
Each bit in the CMSSEL register, when set, causes the CMS
signal to be asserted when the selected memory select is as-
serted. For example, to use a 32K word memory to act as both
program and data memory, set the PMS and DMS bits in the
CMSSEL register and use the CMS pin to drive the chip select
of the memory; use either DMS or PMS as the additional
address bit.
The CMS pin functions like the other memory select signals,
with the same timing and bus request logic. A 1 in the enable bit
causes the assertion of the CMS signal at the same time as the
selected memory select signal. All enable bits default to 1 at re-
set, except the BMS bit.
Boot Memory Select (BMS) DisableThe ADSP-2187L also lets you boot the processor from one ex-
ternal memory space while using a different external memory
space for BDMA transfers during normal operation. You can
use the CMS to select the first external memory space for
BDMA transfers and BMS to select the second external
memory space for booting. The BMS signal can be disabled by
setting Bit 3 of the System Control Register to 1. The System
Control Register is illustrated in Figure 6.
14131211109876543210
DM (033FFF)
SYSTEM CONTROL REGISTER
SPORT0 ENABLE
1 = ENABLED, 0 = DISABLED
SPORT1 ENABLE
1 = ENABLED, 0 = DISABLED
SPORT1 CONFIGURE
1 = SERIAL PORT
BDMA accesses can cross page boundaries during sequential
addressing. A BDMA interrupt is generated on the completion
of the number of transfers specified by the BWCOUNT
register.
The BWCOUNT register is updated after each transfer so it can
be used to check the status of the transfers. When it reaches
zero, the transfers have finished and a BDMA interrupt is gener-
ated. The BMPAGE and BEAD registers must not be accessed
by the DSP during BDMA operations.
The source or destination of a BDMA transfer will always be
on-chip program or data memory.
When the BWCOUNT register is written with a nonzero value,
the BDMA circuit starts executing byte memory accesses with
wait states set by BMWAIT. These accesses continue until the
count reaches zero. When enough accesses have occurred to
create a destination word, it is transferred to or from on-chip
memory. The transfer takes one DSP cycle. DSP accesses to ex-
ternal memory have priority over BDMA byte memory accesses.
The BDMA Context Reset bit (BCR) controls whether or not
the processor is held off while the BDMA accesses are occur-
ring. Setting the BCR bit to 0 allows the processor to continue
operations. Setting the BCR bit to 1 causes the processor to
stop execution while the BDMA accesses are occurring, to clear
the context of the processor and start execution at address 0
when the BDMA accesses have completed.
The BDMA overlay bits specify the OVLAY memory blocks to
be accessed for internal memory.
Internal Memory DMA Port (IDMA Port; Host Memory
Mode)The IDMA Port provides an efficient means of communication
between a host system and the ADSP-2187L. The port is used
to access the on-chip program memory and data memory of the
DSP with only one DSP cycle per word overhead. The IDMA
port cannot be used, however, to write to the DSP’s memory-
mapped control registers. A typical IDMA transfer process is
described as follows:Host starts IDMA transfer.Host checks IACK control line to see if the DSP is busy.Host uses IS and IAL control lines to latch either the DMA
starting address (IDMAA) or the PM/DM OVLAY selection
into the DSP’s IDMA control registers.
If IAD[15] = 1, the value of IAD[7:0] represent the IDMA
overlay: IAD[14:8] must be set to 0.
If IAD[15] = 0, the value of IAD[13:0] represent the start-
ing address of internal memory to be accessed and IAD[14]
reflects PM or DM for access.Host uses IS and IRD (or IWR) to read (or write) DSP inter-
nal memory (PM or DM).Host checks IACK line to see if the DSP has completed the
previous IDMA operation.Host ends IDMA transfer.
The IDMA port has a 16-bit multiplexed address and data bus
and supports 24-bit program memory. The IDMA port is
completely asynchronous and can be written to while the
ADSP-2187L is operating at full speed.
The DSP memory address is latched and then automatically in-
cremented after each IDMA transaction. An external device can
therefore access a block of sequentially addressed memory by
specifying only the starting address of the block. This increases
throughput as the address does not have to be sent for each
memory access.
IDMA Port access occurs in two phases. The first is the IDMA
Address Latch cycle. When the acknowledge is asserted, a
14-bit address and 1-bit destination type can be driven onto the
bus by an external device. The address specifies an on-chip
memory location; the destination type specifies whether it is a
DM or PM access. The falling edge of the address latch signal
latches this value into the IDMAA register.
Once the address is stored, data can either be read from or
written to the ADSP-2187L’s on-chip memory. Asserting the
select line (IS) and the appropriate read or write line (IRD andIWR respectively) signals the ADSP-2187L that a particular
transaction is required. In either case, there is a one-processor-
cycle delay for synchronization. The memory access consumes
one additional processor cycle.
Once an access has occurred, the latched address is automati-
cally incremented and another access can occur.
Through the IDMAA register, the DSP can also specify the
starting address and data format for DMA operation. Asserting
the IDMA port select (IS) and address latch enable (IAL) di-
rects the ADSP-2187L to write the address onto the IAD0–14
bus into the IDMA Control Register. If IAD[15] is set to 0,
IDMA latches the address. If IAD[15] is set to 1, IDMA
latches OVLAY memory. The IDMA OVLAY and address are
stored in separate memory-mapped registers. The IDMAA regis-
ter, shown below, is memory mapped at address DM (0x3FE0).
Note that the latched address (IDMAA) cannot be read back by
the host. The IDMA OVLAY register is memory mapped at
address DM (0x3FE7). See Figures 8 and 9 for more informa-
tion on IDMA and DMA memory maps.
Figure 8.IDMA Control/OVLAY Registers
ADSP-2187LFigure 9.Direct Memory Access-PM and DM Memory Maps
Bootstrap Loading (Booting)The ADSP-2187L has two mechanisms to allow automatic
loading of the internal program memory after reset. The method
for booting after reset is controlled by the Mode A, B and C
configuration bits.
When the mode pins specify BDMA booting, the ADSP-2187L
initiates a BDMA boot sequence when reset is released.
The BDMA interface is set up during reset to the following de-
faults when BDMA booting is specified: the BDIR, BMPAGE,
BIAD and BEAD registers are set to 0, the BTYPE register is
set to 0 to specify program memory 24-bit words, and the
BWCOUNT register is set to 32. This causes 32 words of on-
chip program memory to be loaded from byte memory. These
32 words are used to set up the BDMA to load in the remaining
program code. The BCR bit is also set to 1, which causes pro-
gram execution to be held off until all 32 words are loaded into
on-chip program memory. Execution then begins at address 0.
The ADSP-2100 Family Development Software (Revision 5.02
and later) fully supports the BDMA booting feature and can
generate byte memory space compatible boot code.
The IDLE instruction can also be used to allow the processor to
hold off execution while booting continues through the BDMA
interface. For BDMA accesses while in Host Mode, the ad-
dresses to boot memory must be constructed externally to the
ADSP-2187L. The only memory address bit provided by the
processor is A0.
IDMA Port BootingThe ADSP-2187L can also boot programs through its Internal
DMA port. If Mode C = 1, Mode B = 0 and Mode A = 1, the
ADSP-2187L boots from the IDMA port. IDMA feature can
load as much on-chip memory as desired. Program execution is
held off until on-chip program memory location 0 is written to.
Bus Request and Bus Grant (Full Memory Mode)The ADSP-2187L can relinquish control of the data and ad-
dress buses to an external device. When the external device re-
quires access to memory, it asserts the bus request (BR) signal.
If the ADSP-2187L is not performing an external memory ac-
cess, it responds to the active BR input in the following proces-
sor cycle by:three-stating the data and address buses and the PMS, DMS,BMS, CMS, IOMS, RD, WR output drivers,asserting the bus grant (BG) signal, andhalting program execution.
If Go Mode is enabled, the ADSP-2187L will not halt program
execution until it encounters an instruction that requires an ex-
ternal memory access.
If the ADSP-2187L is performing an external memory access
when the external device asserts the BR signal, it will not three-
state the memory interfaces or assert the BG signal until the
processor cycle after the access completes. The instruction does
not need to be completed when the bus is granted. If a single in-
struction requires two external memory accesses, the bus will be
granted between the two accesses.
When the BR signal is released, the processor releases the BG
signal, reenables the output drivers and continues program ex-
ecution from the point at which it stopped.
The bus request feature operates at all times, including when
the processor is booting and when RESET is active.
The BGH pin is asserted when the ADSP-2187L is ready to ex-
ecute an instruction, but is stopped because the external bus is
already granted to another device. The other device can release
the bus by deasserting bus request. Once the bus is released, the
ADSP-2187L deasserts BG and BGH and executes the external
memory access.
Flag I/O PinsThe ADSP-2187L has eight general purpose programmable
input/output flag pins. They are controlled by two memory
mapped registers. The PFTYPE register determines the direc-
tion, 1 = output and 0 = input. The PFDATA register is used to
read and write the values on the pins. Data being read from a
pin configured as an input is synchronized to the ADSP-2187L’s
clock. Bits that are programmed as outputs will read the value
being output. The PF pins default to input during reset.
In addition to the programmable flags, the ADSP-2187L has
five fixed-mode flags, FLAG_IN, FLAG_OUT, FL0, FL1 and
FL2. FL0-FL2 are dedicated output flags. FLAG_IN and
FLAG_OUT are available as an alternate configuration of
SPORT1.
Note: Pins PF0, PF1, PF2 and PF3 are also used for device
configuration during reset.
INSTRUCTION SET DESCRIPTIONThe ADSP-2187L assembly language instruction set has an
algebraic syntax that was designed for ease of coding and read-
ability. The assembly language, which takes full advantage of
the processor’s unique architecture, offers the following benefits:The algebraic syntax eliminates the need to remember cryptic
assembler mnemonics. For example, a typical arithmetic add
instruction, such as AR = AX0 + AY0, resembles a simple
equation.Every instruction assembles into a single, 24-bit word that can
execute in a single instruction cycle.The syntax is a superset ADSP-2100 Family assembly lan-
guage and is completely source and object code compatible
with other family members. Programs may need to be relo-
cated to utilize on-chip memory and conform to the ADSP-
2187L’s interrupt vector and reset vector map.Sixteen condition codes are available. For conditional jump,
call, return or arithmetic instructions, the condition can be
checked and the operation executed in the same instruction
cycle.Multifunction instructions allow parallel execution of an
arithmetic instruction with up to two fetches or one write to
processor memory space during a single instruction cycle.
DESIGNING AN EZ-ICE-COMPATIBLE SYSTEMThe ADSP-2187L has on-chip emulation support and an ICE-
Port, a special set of pins that interface to the EZ-ICE. These
features allow in-circuit emulation without replacing the target
system processor by using only a 14-pin connection from the
target system to the EZ-ICE. Target systems must have a 14-pin
connector to accept the EZ-ICE’s in-circuit probe, a 14-pin plug.
See the ADSP-2100 Family EZ-Tools data sheet for complete in-
formation on ICE products.
Issuing the chip reset command during emulation causes the
DSP to perform a full chip reset, including a reset of its memory
mode. Therefore, it is vital that the mode pins are set correctly
PRIOR to issuing a chip reset command from the emulator user
interface. If you are using a passive method of maintaining
mode information (as discussed in Setting Memory Modes)
then it does not matter that the mode information is latched by
an emulator reset. However, if you are using the RESET pin as
a method of setting the value of the mode pins, then you have to
take into consideration the effects of an emulator reset.
The ICE-Port interface consists of the following ADSP-2187L
pins:
EBREBGERESETEMSEINTECLK
ELINELOUTEE
These ADSP-2187L pins must be connected only to the EZ-ICE
connector in the target system. These pins have no function ex-
cept during emulation, and do not require pull-up or pull-down
resistors. The traces for these signals between the ADSP-2187L
and the connector must be kept as short as possible, no longer
than three inches.
The following pins are also used by the EZ-ICE:BGRESETGND
The EZ-ICE uses the EE (emulator enable) signal to take con-
trol of the ADSP-2187L in the target system. This causes the
processor to use its ERESET, EBR and EBG pins instead of theRESET, BR and BG pins. The BG output is three-stated. These
signals do not need to be jumper-isolated in your system.
The EZ-ICE connects to your target system via a ribbon cable
and a 14-pin female plug. The ribbon cable is 10 inches in
length with one end fixed to the EZ-ICE. The female plug is
plugged onto the 14-pin connector (a pin strip header) on the
target board.
One method of ensuring that the values located on the mode
pins are those desired is to construct a circuit like the one shown
in Figure 10. This circuit forces the value located on the Mode
A pin to logic high; regardless if it latched via the RESET orERESET pin.
Figure 10.Mode A Pin/EZ-ICE Circuit
ADSP-2187L
Target Board Connector for EZ-ICE ProbeThe EZ-ICE connector (a standard pin strip header) is shown in
Figure 11. You must add this connector to your target board
design if you intend to use the EZ-ICE. Be sure to allow enough
room in your system to fit the EZ-ICE probe onto the 14-pin
connector.
Figure 11.Target Board Connector for EZ-ICE
The 14-pin, 2-row pin strip header is keyed at the Pin 7 loca-
tion—you must remove Pin 7 from the header. The pins must
be 0.025 inch square and at least 0.20 inch in length. Pin spac-
ing should be 0.1 · 0.1 inches. The pin strip header must have
at least 0.15 inch clearance on all sides to accept the EZ-ICE
probe plug.
Pin strip headers are available from vendors such as 3M,
McKenzie and Samtec.
Target Memory InterfaceFor your target system to be compatible with the EZ-ICE emu-
lator, it must comply with the memory interface guidelines listed
below.
PM, DM, BM, IOM and CMDesign your Program Memory (PM), Data Memory (DM),
Byte Memory (BM), I/O Memory (IOM) and Composite
Memory (CM) external interfaces to comply with worst case
device timing requirements and switching characteristics as
specified in the DSP’s data sheet. The performance of the
EZ-ICE may approach published worst case specification for
some memory access timing requirements and switching
characteristics.
Note: If your target does not meet the worst case chip specifica-
tion for memory access parameters, you may not be able to
emulate your circuitry at the desired CLKIN frequency. De-
pending on the severity of the specification violation, you may
have trouble manufacturing your system as DSP components
statistically vary in switching characteristic and timing require-
ments within published limits.
Restriction: All memory strobe signals on the ADSP-2187L(RD, WR, PMS, DMS, BMS, CMS and IOMS) used in your
target system must have 10 kW pull-up resistors connected when
the EZ-ICE is being used. The pull-up resistors are necessary
because there are no internal pull-ups to guarantee their state
during prolonged three-state conditions resulting from typical
EZ-ICE debugging sessions. These resistors may be removed at
your option when the EZ-ICE is not being used.
Target System Interface SignalsWhen the EZ-ICE board is installed, the performance on some
system signals changes. Design your system to be compatible
with the following system interface signal changes introduced by
the EZ-ICE board:EZ-ICE emulation introduces an 8 ns propagation delay be-
tween your target circuitry and the DSP on the RESET
signal.EZ-ICE emulation introduces an 8 ns propagation delay be-
tween your target circuitry and the DSP on the BR signal.EZ-ICE emulation ignores RESET and BR when single-
stepping.EZ-ICE emulation ignores RESET and BR when in Emulator
Space (DSP halted).EZ-ICE emulation ignores the state of target BR in certain
modes. As a result, the target system may take control of the
DSP’s external memory bus only if bus grant (BG) is asserted
by the EZ-ICE board’s DSP.
SPECIFICATIONS
RECOMMENDED OPERATING CONDITIONS
ELECTRICAL CHARACTERISTICSIIH
IOZL
IDD
NOTESBidirectional pins: D0–D23, RFS0, RFS1, SCLK0, SCLK1, TFS0, TFS1, A1–A13, PF0–PF7.Input only pins: RESET, BR, DR0, DR1, PWD.Input only pins: CLKIN, RESET, BR, DR0, DR1, PWD.Output pins: BG, PMS, DMS, BMS, IOMS, CMS, RD, WR, PWDACK, A0, DT0, DT1, CLKOUT, FL2–0, BGH.Although specified for TTL outputs, all ADSP-2187L outputs are CMOS-compatible and will drive to VDD and GND, assuming no dc loads.Guaranteed but not tested.Three-statable pins: A0–A13, D0–D23, PMS, DMS, BMS, IOMS, CMS, RD, WR, DT0, DT1, SCLK0, SCLK1, TFS0, TFS1, RFS0, RFS1, PF0–PF7.0 V on BR.Idle refers to ADSP-2187L state of operation during execution of IDLE instruction. Deasserted pins are driven to either VDD or GND.VIN = 0 V and 3 V. For typical figures for supply currents, refer to Power Dissipation section.IDD measurement taken with all instructions executing from internal memory. 50% of the instructions are multifunction (types 1, 4, 5, 12, 13, 14), 30% are type 2
and type 6, and 20% are idle instructions.Applies to TQFP package type.Output pin capacitance is the capacitive load for any three-stated output pin.
ADSP-2187L
ADSP-2187L
ESD SENSITIVITYThe ADSP-2187L is an ESD (electrostatic discharge) sensitive device. Electrostatic charges readily
accumulate on the human body and equipment and can discharge without detection. Permanent
damage may occur to devices subjected to high energy electrostatic discharges.
The ADSP-2187L features proprietary ESD protection circuitry to dissipate high energy discharges
(Human Body Model). Per method 3015 of MIL-STD-883, the ADSP-2187L has been classified
as a Class 1 device.
Proper ESD precautions are recommended to avoid performance degradation or loss of function-
ality. Unused devices must be stored in conductive foam or shunts, and the foam should be
discharged to the destination before devices are removed.
TIMING PARAMETERS
GENERAL NOTESUse the exact timing information given. Do not attempt to de-
rive parameters from the addition or subtraction of others.
While addition or subtraction would yield meaningful results for
an individual device, the values given in this data sheet reflect
statistical variations and worst cases. Consequently, you cannot
meaningfully add up parameters to derive longer times.
TIMING NOTESSwitching Characteristics specify how the processor changes its
signals. You have no control over this timing—circuitry external
to the processor must be designed for compatibility with these
signal characteristics. Switching characteristics tell you what the
processor will do in a given circumstance. You can also use switch-
ing characteristics to ensure that any timing requirement of a
device connected to the processor (such as memory) is satisfied.
Timing Requirements apply to signals that are controlled by cir-
cuitry external to the processor, such as the data input for a read
operation. Timing requirements guarantee that the processor
operates correctly with other devices.
MEMORY TIMING SPECIFICATIONSThe table below shows common memory device specifications
and the corresponding ADSP-2187L timing parameters, for
your convenience.
Address Setup to
Address Hold Time
Data Setup Time
Data Hold Time
OE to Data Valid
xMS = PMS, DMS, BMS, CMS, IOMS.
FREQUENCY DEPENDENCY FOR TIMING
SPECIFICATIONStCK = Instruction Clock Period. tCKI = External Clock Period.
tCK is defined as 0.5tCKI. The ADSP-2187L uses an input clock
with a frequency equal to half the instruction rate: a 26MHz
input clock (which is equivalent to 38 ns) yields a 19 ns processor
cycle (equivalent to 52 MHz). tCK values within the range of
0.5tCKI period should be substituted for all relevant timing
parameters to obtain the specification value.
Example: tCKH = 0.5tCK – 7 ns = 0.5 (19 ns) – 7 ns = 2.5 ns
ABSOLUTE MAXIMUM RATINGS*Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . .–0.3 V to +4.6 V
Input Voltage . . . . . . . . . . . . . . . . . . . . .–0.5 V to VDD + 0.5 V
Output Voltage Swing . . . . . . . . . . . . . .–0.5 V to VDD + 0.5 V
Operating Temperature Range (Ambient) . . . .–40°C to +85°C
Storage Temperature Range . . . . . . . . . . . . .–65°C to +150°C
Lead Temperature (5 sec) TQFP . . . . . . . . . . . . . . . .+280°C
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. These are stress ratings only; functional operation of
the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
