ADSP-2186MBST-266 ,DSP MicrocomputerSPECIFICATIONS . . . . . . . . . . . . . . . . . . . . 20Common-Mode Pins . . . . . . . . . . . . . ..
ADSP-2186MKST300 ,DSP Microcomputerfeatures:a program sequencer) with two serial ports, a 16-bit internal DMAport, a byte DMA port, a ..
ADSP-2186MKST-300 ,DSP MicrocomputerFEATURESSystem InterfacePerformanceFlexible I/O Structure Allows 2.5 V or 3.3 V Operation;13.3 ns I ..
ADSP-2186MKSTZ-300 , DSP Microcomputer
ADSP2186NKST320 ,DSP MicrocomputerFEATURES Memory Space Permits “Glueless” System DesignADSP-2100 Family Code Compatible (Easy to Use ..
ADSP-2186NKST-320 ,DSP Microcomputerfeatures: units process 16-bit data directly and have provisions to support multiprecision computat ..
AM26C31CD ,Quadruple Differential Line DriverFeatures section and added the Applications section, the Device Information table, ESD Ratings tabl ..
AM26C31CDB , QUADRUPLE DIFFERENTIAL LINE DRIVERS
AM26C31CDBR ,Quadruple Differential Line DriverElectrical Characteristics: AM26C31Q and12 Device and Documentation Support........ 15AM26C31M. 612 ..
AM26C31CDBRG4 ,Quadruple Differential Line Driver 16-SSOP 0 to 70Features 3 DescriptionThe AM26C31 device is a differential line driver with1• Meets or Exceeds the ..
AM26C31CDG4 ,Quadruple Differential Line Driver 16-SOIC 0 to 70Block Diagrams. 103 Description....... 18.3 Feature Description.... 114 Revision History........ 28 ..
AM26C31CDR ,Quadruple Differential Line DriverMaximum Ratings . 49.2 Typical Application .... 126.2 ESD Ratings........ 410 Power Supply Recommen ..
ADSP-2186MBST-266-ADSP-2186MKST300-ADSP-2186MKST-300
DSP Microcomputer
REV.0
DSP
Microcomputer
FUNCTIONAL BLOCK DIAGRAMICE-Port is a trademark of Analog Devices, Inc.
FEATURES
Performance
13.3 ns Instruction Cycle Time @ 2.5 V (Internal),
75 MIPS Sustained Performance
Single-Cycle Instruction Execution
Single-Cycle Context Switch
3-Bus Architecture Allows Dual Operand Fetches in
Every Instruction Cycle
Multifunction Instructions
Power-Down Mode Featuring Low CMOS Standby Power
Dissipation with 200 CLKIN Cycle Recovery from
Power-Down Condition
Low Power Dissipation in Idle Mode
Integration
ADSP-2100 Family Code Compatible (Easy to Use
Algebraic Syntax), with Instruction Set Extensions
40K Bytes of On-Chip RAM, Configured as
8K Words Program Memory RAM
8K Words Data Memory RAM
Dual-Purpose Program Memory for Both Instructionand
Data Storage
Independent ALU, Multiplier/Accumulator, and Barrel
Shifter Computational Units
Two Independent Data Address Generators
Powerful Program Sequencer Provides Zero Overhead
Looping Conditional Instruction Execution
Programmable 16-Bit Interval Timer with Prescaler
100-Lead LQFP and 144-Ball Mini-BGA
System Interface
Flexible I/O Structure Allows 2.5 V or 3.3 V Operation;
All Inputs Tolerate up to 3.6 V Regardless of Mode
16-Bit Internal DMA Port for High-Speed Access to
On-Chip Memory (Mode Selectable)
4 MByte Memory Interface for Storage of Data Tables
and Program Overlays (Mode Selectable)
8-Bit DMA to Byte Memory for Transparent Program
and Data Memory Transfers (Mode Selectable)
I/O Memory Interface with 2048 Locations Supports
Parallel Peripherals (Mode Selectable)
Programmable Memory Strobe and Separate I/O
Memory Space Permits “Glueless” System Design
Programmable Wait State Generation
Two Double-Buffered Serial Ports with Companding
Hardware and Automatic Data Buffering
Automatic Booting of On-Chip Program Memory from
Byte-Wide External Memory, e.g., EPROM, or
through Internal DMA Port
Six External Interrupts
13 Programmable Flag Pins Provide Flexible System
Signaling
UART Emulation through Software SPORT Reconfiguration
ICE-Port™ Emulator Interface Supports Debugging in
Final Systems
ADSP-2186M
TABLE OF CONTENTSFEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
FUNCTIONAL BLOCK DIAGRAM . . . . . . . . . . . . . . . .1
GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . .3
DEVELOPMENT SYSTEM . . . . . . . . . . . . . . . . . . . . . . .3
Additional Information . . . . . . . . . . . . . . . . . . . . . . . . . .3
ARCHITECTURE OVERVIEW . . . . . . . . . . . . . . . . . . . .4
Serial Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
PIN DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
Common-Mode Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Memory Interface Pins . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Full Memory Mode Pins (Mode C = 0) . . . . . . . . . . . . . .7
Host Mode Pins (Mode C = 1) . . . . . . . . . . . . . . . . . . . .7
Terminating Unused Pins . . . . . . . . . . . . . . . . . . . . . . . .8
Pin Terminations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
LOW POWER OPERATION . . . . . . . . . . . . . . . . . . . . . . .9
Power-Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Idle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Slow Idle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
SYSTEM INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . .10
Clock Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Power Supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
MODES OF OPERATION . . . . . . . . . . . . . . . . . . . . . . .11
Setting Memory Mode . . . . . . . . . . . . . . . . . . . . . . . . . .11
Passive Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Active Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . .12
IACK Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . .12
MEMORY ARCHITECTURE . . . . . . . . . . . . . . . . . . . . .12
Program Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Data Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Memory Mapped Registers (New to the
ADSP-2186M) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
I/O Space (Full Memory Mode) . . . . . . . . . . . . . . . . . . .13
Composite Memory Select (CMS) . . . . . . . . . . . . . . . . .14
Byte Memory Select (BMS) . . . . . . . . . . . . . . . . . . . . . .14
Byte Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Byte Memory DMA (BDMA, Full Memory Mode) . . . .14
Internal Memory DMA Port
(IDMA Port; Host Memory Mode) . . . . . . . . . . . . . .15
Bootstrap Loading (Booting) . . . . . . . . . . . . . . . . . . . . .15
IDMA Port Booting . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Bus Request and Bus Grant . . . . . . . . . . . . . . . . . . . . . .16
Flag I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Instruction Set Description . . . . . . . . . . . . . . . . . . . . . .16
DESIGNING AN EZ-ICE-COMPATIBLE SYSTEM . . .16
Target Board Connector for EZ-ICE Probe . . . . . . . . . .17
Target Memory Interface . . . . . . . . . . . . . . . . . . . . . . . .17
PM, DM, BM, IOM, AND CM . . . . . . . . . . . . . . . . . . . .17
Target System Interface Signals . . . . . . . . . . . . . . . . . . .17
RECOMMENDED OPERATING CONDITIONS . . . . .18
ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . .18
ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . .19
TIMING SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . .19
GENERAL NOTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
TIMING NOTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
MEMORY TIMING SPECIFICATIONS . . . . . . . . . . . .19
FREQUENCY DEPENDENCY FOR
TIMING SPECIFICATIONS . . . . . . . . . . . . . . . . . . . .20
ENVIRONMENTAL CONDITIONS . . . . . . . . . . . . . . .20
POWER DISSIPATION . . . . . . . . . . . . . . . . . . . . . . . . . .20
Output Drive Currents . . . . . . . . . . . . . . . . . . . . . . . . . .20
Capacitive Loading . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
TEST CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Output Disable Time . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Output Enable Time . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Clock Signals and Reset . . . . . . . . . . . . . . . . . . . . . . . . .23
Interrupts and Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
Bus Request–Bus Grant . . . . . . . . . . . . . . . . . . . . . . . . .25
Memory Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
Memory Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
Serial Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
IDMA Address Latch . . . . . . . . . . . . . . . . . . . . . . . . . . .29
IDMA Write, Short Write Cycle . . . . . . . . . . . . . . . . . .30
IDMA Write, Long Write Cycle . . . . . . . . . . . . . . . . . . .31
IDMA Read, Long Read Cycle . . . . . . . . . . . . . . . . . . .32
IDMA Read, Short Read Cycle . . . . . . . . . . . . . . . . . . .33
IDMA Read, Short Read Cycle in Short Read
Only Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
100-LEAD LQFP PIN CONFIGURATION . . . . . . . . . .35
LQFP Package Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
144-Ball Mini-BGA Package Pinout . . . . . . . . . . . . . . . . .37
Mini-BGA Package Pinout . . . . . . . . . . . . . . . . . . . . . . . .38
OUTLINE DIMENSIONS
100-Lead Metric Thin Plastic Quad Flatpack
(LQFP) (ST-100) . . . . . . . . . . . . . . . . . . . . . . . . . . .39
OUTLINE DIMENSIONS
144-Ball Mini-BGA (CA-144) . . . . . . . . . . . . . . . . . . . .40
ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
TablesTable I.Interrupt Priority and Interrupt
Vector Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Table II.Modes of Operation . . . . . . . . . . . . . . . . . . . . . .11
Table III.PMOVLAY Bits . . . . . . . . . . . . . . . . . . . . . . . .12
Table IV.DMOVLAY Bits . . . . . . . . . . . . . . . . . . . . . . . .13
Table V.Wait States . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Table VI.Data Formats . . . . . . . . . . . . . . . . . . . . . . . . . .14
GENERAL DESCRIPTIONThe ADSP-2186M is a single-chip microcomputer optimized
for digital signal processing (DSP) and other high-speed numeric
processing applications.
The ADSP-2186M combines the ADSP-2100 family base archi-
tecture (three computational units, data address generators, and
a program sequencer) with two serial ports, a 16-bit internal DMA
port, a byte DMA port, a programmable timer, Flag I/O, exten-
sive interrupt capabilities, and on-chip program and data memory.
The ADSP-2186M integrates 40K bytes of on-chip memory
configured as 8K words (24-bit) of program RAM, and 8K
words (16-bit) of data RAM. Power-down circuitry is also pro-
vided to meet the low power needs of battery-operated portable
equipment. The ADSP-2186M is available in a 100-lead LQFP
package and 144 Ball Mini-BGA.
In addition, the ADSP-2186M supports new instructions, which
include bit manipulations—bit set, bit clear, bit toggle, bit test—
new ALU constants, new multiplication instruction (× squared),
biased rounding, result-free ALU operations, I/O memory trans-
fers, and global interrupt masking, for increased flexibility.
Fabricated in a high-speed, low-power, CMOS process, the
ADSP-2186M operates with a 13.3 ns instruction cycle time.
Every instruction can execute in a single processor cycle.
The ADSP-2186M’s flexible architecture and comprehensive
instruction set allow the processor to perform multiple opera-
tions in parallel. In one processor cycle, the ADSP-2186M can:Generate the next program addressFetch the next instructionPerform one or two data movesUpdate one or two data address pointersPerform a computational operation
This takes place while the processor continues to:Receive and transmit data through the two serial portsReceive and/or transmit data through the internal DMA portReceive and/or transmit data through the byte DMA portDecrement timer
DEVELOPMENT SYSTEMThe ADSP-2100 Family Development Software, a complete set
of tools for software and hardware system development, supports
the ADSP-2186M. The System Builder provides a high-level
method for defining the architecture of systems under develop-
ment. The Assembler has an algebraic syntax that is easy to
program and debug. The Linker combines object files into an
executable file. The Simulator provides an interactive instruction-
level simulation with a reconfigurable user interface to display
different portions of the hardware environment.
The EZ-KIT Lite is a hardware/software kit offering a complete
evaluation environment for the ADSP-218x family: an ADSP-
2189M-based evaluation board with PC monitor software plus
assembler, linker, simulator, and PROM splitter software. The
ADSP-2189M EZ-KIT Lite is a low cost, easy to use hardware
platform on which you can quickly get started with your DSP
software design. The EZ-KIT Lite includes the following features:75 MHz ADSP-2189MFull 16-Bit Stereo Audio I/O with AD73322 CodecRS-232 InterfaceEZ-ICE Connector for Emulator ControlDSP Demo ProgramsEvaluation Suite of VisualDSP
The ADSP-218x EZ-ICE® Emulator aids in the hardware
debugging of an ADSP-2186M system. The ADSP-2186M
integrates on-chip emulation support with a 14-pin ICE-Port
interface. This interface provides a simpler target board connec-
tion that requires fewer mechanical clearance considerations
than other ADSP-2100 Family EZ-ICEs. The ADSP-2186M
device need not be removed from the target system when using
the EZ-ICE, nor are any adapters needed. Due to the small
footprint of the EZ-ICE connector, emulation can be supported
in final board designs.
The EZ-ICE performs a full range of functions, including:In-target operationUp to 20 breakpointsSingle-step or full-speed operationRegisters and memory values can be examined and alteredPC upload and download functionsInstruction-level emulation of program booting and executionComplete assembly and disassembly of instructionsC source-level debugging
See Designing An EZ-ICE-Compatible Target System in the
ADSP-2100 Family EZ-Tools Manual (ADSP-2181 sections) as
well as the Designing an EZ-ICE-Compatible System section of
this data sheet for the exact specifications of the EZ-ICE target
board connector.
Additional InformationThis data sheet provides a general overview of ADSP-2186M
functionality. For additional information on the architecture and
instruction set of the processor, refer to the ADSP-2100 Family
User’s Manual. For more information about the development
tools, refer to the ADSP-2100 Family Development Tools
data sheet.
ADSP-2186M
ARCHITECTURE OVERVIEWThe ADSP-2186M instruction set provides flexible data moves
and multifunction (one or two data moves with a computation)
instructions. Every instruction can be executed in a single
processor cycle. The ADSP-2186M assembly language uses an
algebraic syntax for ease of coding and readability. A compre-
hensive set of development tools supports program development.
Figure 1 is an overall block diagram of the ADSP-2186M. The
processor contains three independent computational units:
the ALU, the multiplier/accumulator (MAC), and the shifter.
The computational units process 16-bit data directly and have
provisions to support multiprecision computations. The ALU
performs a standard set of arithmetic and logic operations;
division primitives are also supported. The MAC performs
single-cycle multiply, multiply/add, and multiply/subtract opera-
tions with 40 bits of accumulation. The shifter performs logical
and arithmetic shifts, normalization, denormalization, and
derive exponent operations.
The shifter can be used to efficiently implement numeric
format control, including multiword and block floating-point
representations.
The internal result (R) bus connects the computational units so
that the output of any unit may be the input of any unit on the
next cycle.
A powerful program sequencer and two dedicated data address
generators ensure efficient delivery of operands to these computa-
tional units. The sequencer supports conditional jumps, subroutine
calls, and returns in a single cycle. With internal loop counters
and loop stacks, the ADSP-2186M executes looped code with
zero overhead; no explicit jump instructions are required to
maintain loops.
(indirect addressing), it is post-modified by the value of one of
four possible modify registers. A length value may be associated
with each pointer to implement automatic modulo addressing
for circular buffers.
Efficient data transfer is achieved with the use of five
internal buses:Program Memory Address (PMA) BusProgram Memory Data (PMD) BusData Memory Address (DMA) BusData Memory Data (DMD) BusResult (R) Bus
The two address buses (PMA and DMA) share a single external
address bus, allowing memory to be expanded off-chip, and the
two data buses (PMD and DMD) share a single external data
bus. Byte memory space and I/O memory space also share the
external buses.
Program memory can store both instructions and data, permit-
ting the ADSP-2186M to fetch two operands in a single cycle,
one from program memory and one from data memory. The
ADSP-2186M can fetch an operand from program memory and
the next instruction in the same cycle.
In lieu of the address and data bus for external memory connec-
tion, the ADSP-2186M may be configured for 16-bit Internal
DMA port (IDMA port) connection to external systems. The
IDMA port is made up of 16 data/address pins and five control
pins. The IDMA port provides transparent, direct access to the
DSPs on-chip program and data RAM.
An interface to low-cost byte-wide memory is provided by the
Byte DMA port (BDMA port). The BDMA port is bidirectional
and can directly address up to four megabytes of external RAM
or ROM for off-chip storage of program overlays or data tables.
Figure 1.Functional Block Diagram
external buses with bus request/grant signals (BR, BGH, and BG).
One execution mode (Go Mode) allows the ADSP-2186M to
continue running from on-chip memory. Normal execution
mode requires the processor to halt while buses are granted.
The ADSP-2186M can respond to eleven interrupts. There can
be up to six external interrupts (one edge-sensitive, two level-
sensitive, and three configurable) and seven internal interrupts
generated by the timer, the serial ports (SPORTs), the Byte DMA
port, and the power-down circuitry. There is also a master
RESET signal. The two serial ports provide a complete synchro-
nous serial interface with optional companding in hardware and
a wide variety of framed or frameless data transmit and receive
modes of operation.
Each port can generate an internal programmable serial clock or
accept an external serial clock.
The ADSP-2186M provides up to 13 general-purpose flag pins.
The data input and output pins on SPORT1 can be alternatively
configured as an input flag and an output flag. In addition, eight
flags are programmable as inputs or outputs, and three flags are
always outputs.
A programmable interval timer generates periodic interrupts.
A 16-bit count register (TCOUNT) decrements every n pro-
cessor cycle, where n is a scaling value stored in an 8-bit register
(TSCALE). When the value of the count register reaches zero,
an interrupt is generated and the count register is reloaded from
a 16-bit period register (TPERIOD).
Serial PortsThe ADSP-2186M incorporates two complete synchronous
serial ports (SPORT0 and SPORT1) for serial communications
and multiprocessor communication.
Here is a brief list of the capabilities of the ADSP-2186M
SPORTs. For additional information on Serial Ports, refer to
the ADSP-2100 Family User’s Manual.SPORTs are bidirectional and have a separate, double-
buffered transmit and receive section.SPORTs can use an external serial clock or generate their
own serial clock internally.SPORTs have independent framing for the receive and trans-
mit sections. Sections run in a frameless mode or with frame
synchronization signals internally or externally generated.
Frame sync signals are active high or inverted, with either of
two pulsewidths and timings.SPORTs support serial data word lengths from 3 to 16 bits
and provide optional A-law and µ-law companding according
to CCITT recommendation G.711.SPORT receive and transmit sections can generate unique
interrupts on completing a data word transfer.SPORTs can receive and transmit an entire circular buffer of
data with only one overhead cycle per data word. An interrupt
is generated after a data buffer transfer.SPORT0 has a multichannel interface to selectively receive
and transmit a 24 or 32 word, time- division multiplexed,
serial bitstream.SPORT1 can be configured to have two external interrupts
(IRQ0 and IRQ1) and the FI and FO signals. The internally
generated serial clock may still be used in this configuration.
PIN DESCRIPTIONSThe ADSP-2186M is available in a 100-lead LQFP package
and a 144-Ball Mini-BGA package. In order to maintain maxi-
mum functionality and reduce package size and pin count, some
serial port, programmable flag, interrupt and external bus pins
have dual, multiplexed functionality. The external bus pins are
configured during RESET only, while serial port pins are soft-
ware configurable during program execution. Flag and interrupt
functionality is retained concurrently on multiplexed pins. In
cases where pin functionality is reconfigurable, the default state is
shown in plain text; alternate functionality is shown in italics.
ADSP-2186M
Common-Mode PinsGND
VDDINT
NOTESInterrupt/Flag pins retain both functions concurrently. If IMASK is set to enable the corresponding interrupts, then the DSP will vector to the appropriate interrupt
vector address when the pin is asserted, either by external devices, or set as a programmable flag.SPORT configuration determined by the DSP System Control Register. Software configurable.
Memory Interface PinsThe ADSP-2186M processor can be used in one of two modes: Full Memory Mode, which allows BDMA operation with full exter-
nal overlay memory and I/O capability, or Host Mode, which allows IDMA operation with limited external addressing capabilities.
The operating mode is determined by the state of the Mode C pin during RESET and cannot be changed while the processor is running.
The following tables list the active signals at specific pins of the DSP during either of the two operating modes (Full Memory or
Host). A signal in one table shares a pin with a signal from the other table, with the active signal determined by the mode set. For the
shared pins and their alternate signals (e.g., A4/IAD3), refer to the package pinout tables.
Full Memory Mode Pins (Mode C = 0)
Host Mode Pins (Mode C = 1)NOTEIn Host Mode, external peripheral addresses can be decoded using the A0, CMS, PMS, DMS, and IOMS signals.
ADSP-2186M
Terminating Unused PinsThe following table shows the recommendations for terminating unused pins.
Pin TerminationsIRQL1/PF6
IRQL0/PF5
IRQE/PF4
SCLK0
RFS0
DR0
TFS0
DT0
SCLK1
RFS1/IRQ0
DR1/FI
TFS1/IRQ1
DT1/FO
EBR
EBG
ERESET
EMS
EINT
ECLK
ELIN
NOTES
*Hi-Z = High Impedance.If the CLKOUT pin is not used, turn it OFF, using CLKODIS in SPORT0 autobuffer control register.
InterruptsThe interrupt controller allows the processor to respond to the
11 possible interrupts and reset with minimum overhead. The
ADSP-2186M provides four dedicated external interrupt input
pins: IRQ2, IRQL0, IRQL1, and IRQE (shared with the PF7:4
pins). In addition, SPORT1 may be reconfigured for IRQ0,
IRQ1, FI and FO, for a total of six external interrupts. The
ADSP-2186M also supports internal interrupts from the timer,
the byte DMA port, the two serial ports, software, and the power-
down control circuit. The interrupt levels are internally prioritized
and individually maskable (except power- down and reset). The
IRQ2, IRQ0, and IRQ1 input pins can be programmed to be
either level- or edge-sensitive. IRQL0 and IRQL1 are level-
sensitive and IRQE is edge-sensitive. The priorities and vector
addresses of all interrupts are shown in Table I.
Table I.Interrupt Priority and Interrupt Vector AddressesInterrupt routines can either be nested with higher priority inter-
rupts taking precedence or processed sequentially. Interrupts
can be masked or unmasked with the IMASK register. Individual
interrupt requests are logically ANDed with the bits in IMASK;
the highest priority unmasked interrupt is then selected. The
power-down interrupt is nonmaskable.
The ADSP-2186M masks all interrupts for one instruction
cycle following the execution of an instruction that modifies the
IMASK register. This does not affect serial port autobuffering
or DMA transfers.
The interrupt control register, ICNTL, controls interrupt nest-
ing and defines the IRQ0, IRQ1, and IRQ2 external interrupts
to be either edge- or level-sensitive. The IRQE pin is an exter-
nal edge sensitive interrupt and can be forced and cleared. The
IRQL0 and IRQL1 pins are external level sensitive interrupts.
The IFC register is a write-only register used to force and clear
interrupts. On-chip stacks preserve the processor status and are
automatically maintained during interrupt handling. The stacks
are twelve levels deep to allow interrupt, loop, and subroutine
nesting. The following instructions allow global enable or disable
servicing of the interrupts (including power down), regardless
of the state of IMASK. Disabling the interrupts does not affect
serial port autobuffering or DMA.
ENA INTS;
DIS INTS;
When the processor is reset, interrupt servicing is enabled.
LOW POWER OPERATIONThe ADSP-2186M has three low power modes that significantly
reduce the power dissipation when the device operates under
standby conditions. These modes are:Power-Down
•IdleSlow Idle
The CLKOUT pin may also be disabled to reduce external
power dissipation.
Power-DownThe ADSP-2186M processor has a low power feature that lets
the processor enter a very low-power dormant state through
hardware or software control. Following is a brief list of power-
down features. Refer to the ADSP-2100 Family User’s Manual,
“System Interface” chapter, for detailed information about the
power-down feature.Quick recovery from power-down. The processor begins
executing instructions in as few as 200 CLKIN cycles.Support for an externally generated TTL or CMOS processor
clock. The external clock can continue running during power-
down without affecting the lowest power rating and 200 CLKIN
cycle recovery.Support for crystal operation includes disabling the oscillator
to save power (the processor automatically waits approximately
4096 CLKIN cycles for the crystal oscillator to start or stabi-
lize), and letting the oscillator run to allow 200 CLKIN cycle
start-up.Power-down is initiated by either the power-down pin (PWD)
or the software power-down force bit. Interrupt support allows
an unlimited number of instructions to be executed before
optionally powering down. The power-down interrupt also
can be used as a nonmaskable, edge-sensitive interrupt.Context clear/save control allows the processor to continue
where it left off or start with a clean context when leaving the
power-down state.The RESET pin also can be used to terminate power-down.Power-down acknowledge pin indicates when the processor
has entered power-down.
IdleWhen the ADSP-2186M is in the Idle Mode, the processor
waits indefinitely in a low-power state until an interrupt occurs.
When an unmasked interrupt occurs, it is serviced; execution
then continues with the instruction following the IDLE instruc-
tion. In Idle mode IDMA, BDMA and autobuffer cycle steals
still occur.
ADSP-2186M
Slow IdleThe IDLE instruction is enhanced on the ADSP-2186M to let
the processor’s internal clock signal be slowed, further reducing
power consumption. The reduced clock frequency, a program-
mable fraction of the normal clock rate, is specified by a selectable
divisor given in the IDLE instruction.
The format of the instruction is:
IDLE (n);
where n = 16, 32, 64, or 128. This instruction keeps the proces-
sor fully functional, but operating at the slower clock rate. While
it is in this state, the processor’s other internal clock signals, such
as SCLK, CLKOUT, and timer clock, are reduced by the same
ratio. The default form of the instruction, when no clock divisor
is given, is the standard IDLE instruction.
When the IDLE (n) instruction is used, it effectively slows down
the processor’s internal clock and thus its response time to incom-
ing interrupts. The one-cycle response time of the standard idle
state is increased by n, the clock divisor. When an enabled inter-
rupt is received, the ADSP-2186M will remain in the idle state
for up to a maximum of n processor cycles (n = 16, 32, 64, or
128) before resuming normal operation.
When the IDLE (n) instruction is used in systems that have an
externally generated serial clock (SCLK), the serial clock rate
may be faster than the processor’s reduced internal clock rate.
Under these conditions, interrupts must not be generated at a
faster than can be serviced, due to the additional time the
processor takes to come out of the idle state (a maximum of n
processor cycles).
SYSTEM INTERFACEFigure 2 shows typical basic system configurations with the
ADSP-2186M, two serial devices, a byte-wide EPROM, and
optional external program and data overlay memories (mode-
selectable). Programmable wait state generation allows the
processor to connect easily to slow peripheral devices. The
ADSP-2186M also provides four external interrupts and two
serial ports or six external interrupts and one serial port. Host
Memory Mode allows access to the full external data bus, but
limits addressing to a single address bit (A0). Through the use
of external hardware, additional system peripherals can be added
in this mode to generate and latch address signals.
Clock SignalsThe ADSP-2186M can be clocked by either a crystal or a
TTL-compatible clock signal.
The CLKIN input cannot be halted, changed during opera-
tion, nor operated below the specified frequency during normal
operation. The only exception is while the processor is in the
power-down state. For additional information, refer to Chap-
ter 9, ADSP-2100 Family User’s Manual, for detailed information
on this power-down feature.
If an external clock is used, it should be a TTL-compatible signal
running at half the instruction rate. The signal is connected to
the processor’s CLKIN input. When an external clock is used,
the XTAL input must be left unconnected.
The ADSP-2186M uses an input clock with a frequency equal to
half the instruction rate; a 37.50 MHz input clock yields a 13 ns
processor cycle (which is equivalent to 75 MHz). Normally,
instructions are executed in a single processor cycle. All device
timing is relative to the internal instruction clock rate, which is
indicated by the CLKOUT signal when enabled.
Because the ADSP-2186M includes an on-chip oscillator circuit,
an external crystal may be used. The crystal should be connected
across the CLKIN and XTAL pins, with two capacitors con-
nected as shown in Figure 3. Capacitor values are dependent on
crystal type and should be specified by the crystal manufacturer.
A parallel-resonant, fundamental frequency, microprocessor-
grade crystal should be used.
A clock output (CLKOUT) signal is generated by the processor
at the processor’s cycle rate. This can be enabled and disabled by
the CLKODIS bit in the SPORT0 Autobuffer Control Register.
Figure 3.External Crystal Connections
RESETThe RESET signal initiates a master reset of the ADSP-2186M.
The RESET signal must be asserted during the power-up
sequence to assure proper initialization. RESET during initial
power-up must be held long enough to allow the internal clock
to stabilize. If RESET is activated any time after power-up, the
clock continues to run and does not require stabilization time.
The power-up sequence is defined as the total time required for the
crystal oscillator circuit to stabilize after a valid VDD is applied to
the processor, and for the internal phase-locked loop (PLL) to lock
onto the specific crystal frequency. A minimum of 2000 CLKIN
cycles ensures that the PLL has locked but does not include the
crystal oscillator start-up time. During this power-up sequence
the RESET signal should be held low. On any subsequent resets,
the RESET signal must meet the minimum pulsewidth specifi-
cation, tRSP.
The RESET input contains some hysteresis; however, if an
RC circuit is used to generate the RESET signal, the use of an
external Schmidt trigger is recommended.
The master reset sets all internal stack pointers to the empty stack
condition, masks all interrupts, and clears the MSTAT register.
When RESET is released, if there is no pending bus request and
the chip is configured for booting, the boot-loading sequence is
Table II.Modes of Operationperformed. The first instruction is fetched from on-chip pro-
gram memory location 0x0000 once boot loading completes.
Power SuppliesThe ADSP-2186M has separate power supply connections for
the internal (VDDINT) and external (VDDEXT) power supplies.
The internal supply must meet the 2.5 V requirement. The
external supply can be connected to either a 2.5 V or 3.3 V supply.
All external supply pins must be connected to the same supply.
All input and I/O pins can tolerate input voltages up to 3.6 V,
regardless of the external supply voltage. This feature provides
maximum flexibility in mixing 2.5 V and 3.3 V components.
MODES OF OPERATION
Setting Memory ModeMemory Mode selection for the ADSP-2186M is made during
chip reset through the use of the Mode C pin. This pin is multi-
plexed with the DSP’s PF2 pin, so care must be taken in how
the mode selection is made. The two methods for selecting the
value of Mode C are active and passive.
Passive ConfigurationPassive Configuration involves the use a pull-up or pull-down
resistor connected to the Mode C pin. To minimize power con-
sumption, or if the PF2 pin is to be used as an output in the DSP
application, a weak pull-up or pull-down, on the order of 10 kΩ,
can be used. This value should be sufficient to pull the pin to the
desired level and still allow the pin to operate as a programmable
flag output without undue strain on the processor’s output driver.
For minimum power consumption during power-down, recon-
figure PF2 to be an input, as the pull-up or pull-down will
hold the pin in a known state, and will not switch.
ADSP-2186M
Active ConfigurationActive Configuration involves the use of a three-statable external
driver connected to the Mode C pin. A driver’s output enable
should be connected to the DSP’s RESET signal such that it
only drives the PF2 pin when RESET is active (low). When
RESET is deasserted, the driver should three-state, thus allow-
ing full use of the PF2 pin as either an input or output. To
minimize power consumption during power-down, configure
the programmable flag as an output when connected to a three-
stated buffer. This ensures that the pin will be held at a constant
level, and will not oscillate should the three-state driver’s level
hover around the logic switching point.
IACK ConfigurationMode D = 0 and in host mode: IACK is an active, driven signal
and cannot be “wire OR’d.”
Mode D = 1 and in host mode: IACK is an open drain and
requires an external pull-down, but multiple IACK pins can be
“wire OR’d” together.
MEMORY ARCHITECTUREThe ADSP-2186M provides a variety of memory and peripheral
interface options. The key functional groups are Program Memory,
Data Memory, Byte Memory, and I/O. Refer to the following
figures and tables for PM and DM memory allocations in the
ADSP-2186M.
Program Memory
Program Memory (Full Memory Mode) is a 24-bit-widespace for storing both instruction opcodes and data. The ADSP-
2186M has 8K words of Program Memory RAM on chip, and
the capability of accessing up to two 8K external memory over-
lay spaces using the external data bus.
Program Memory (Host Mode) allows access to all internalmemory. External overlay access is limited by a single external
address line (A0). External program execution is not available in
host mode due to a restricted data bus that is 16 bits wide only.
Figure 4. Program Memory
Table III.PMOVLAY Bits
Data Memory
Data Memory (Full Memory Mode) is a 16-bit-wide space usedfor the storage of data variables and for memory-mapped control
registers. The ADSP-2186M has 8K words on Data Memory
RAM on-chip. Part of this space is used by 32 memory-mapped
registers. Support also exists for up to two 8K external memory
overlay spaces through the external data bus. All internal accesses
Figure 5. Data Memory Map
complete in one cycle. Accesses to external memory are timed
using the wait states specified by the DWAIT register and the
wait state mode bit.
Data Memory (Host Mode) allows access to all internalmemory. External overlay access is limited by a single external
address line (A0).
Table IV.DMOVLAY Bits
Memory Mapped Registers (New to the ADSP-2186M)The ADSP-2186M has three memory mapped registers that differ
from other ADSP-21xx Family DSPs. The slight modifications
to these registers (Wait State Control, Programmable Flag and
Composite Select Control, and System Control) provide the
ADSP-2186M’s wait state and BMS control features. Default
bit values at reset are shown; if no value is shown, the bit is unde-
fined at reset. Reserved bits are shown on a grey field. These bits
should always be written with zeros.
DWAITIOWAIT3IOWAIT2IOWAIT1IOWAIT0
DM(0x3FFE)
WAITSTATE CONTROL14131211109876543210
WAIT STATE MODE SELECT
0 = NORMAL MODE (PWAIT, DWAIT, IOWAIT0–3 = N WAIT STATES, RANGING
FROM 0 TO 7)
1 = 2N + 1 MODE (PWAIT, DWAIT, IOWAIT0–3 = 2N + 1 WAIT STATES, RANGING
FROM 0 TO 15)Figure 6.Wait State Control Register
Figure 8.System Control Register
I/O Space (Full Memory Mode)The ADSP-2186M supports an additional external memory
space called I/O space. This space is designed to support simple
connections to peripherals (such as data converters and external
registers) or to bus interface ASIC data registers. I/O space sup-
ports 2048 locations of 16-bit wide data. The lower eleven bits
of the external address bus are used; the upper three bits are
undefined. Two instructions were added to the core ADSP-2100
Family instruction set to read from and write to I/O memory
space. The I/O space also has four dedicated three-bit wait state
ADSP-2186M
Table V.Wait States
Composite Memory Select (CMS)The ADSP-2186M has a programmable memory select signal that
is useful for generating memory select signals for memories
mapped to more than one space. The CMS signal is gener-
ated to have the same timing as each of the individual memory
select signals (PMS, DMS, BMS, IOMS) but can combine their
functionality.
Each bit in the CMSSEL register, when set, causes the CMS
signal to be asserted when the selected memory select is
asserted. For example, to use a 32K word memory to act as both
program and data memory, set the PMS and DMS bits in the
CMSSEL register and use the CMS pin to drive the chip
select of the memory, and use either DMS or PMS as the
additional address bit.
The CMS pin functions like the other memory select signals
with the same timing and bus request logic. A 1 in the enable bit
causes the assertion of the CMS signal at the same time as the
selected memory select signal. All enable bits default to 1 at reset,
except the BMS bit.
Byte Memory Select (BMS)The ADSP-2186M’s BMS disable feature combined with the
CMS pin allows use of multiple memories in the byte memory
space. For example, an EPROM could be attached to the BMS
select, and an SRAM could be connected to CMS. Because at
reset BMS is enabled, the EPROM would be used for booting.
After booting, software could disable BMS and set the CMS
signal to respond to BMS, enabling the SRAM.
Byte MemoryThe byte memory space is a bidirectional, 8-bit-wide, external
memory space used to store programs and data. Byte memory is
accessed using the BDMA feature. The byte memory space con-
sists of 256 pages, each of which is 16K × 8.
The byte memory space on the ADSP-2186M supports read and
write operations as well as four different data formats. The byte
memory uses data bits 15:8 for data. The byte memory uses data
bits 23:16 and address bits 13:0 to create a 22-bit address. This
allows up to a 4 meg × 8 (32 megabit) ROM or RAM to be used
without glue logic. All byte memory accesses are timed by the
BMWAIT register and the wait state mode bit.
Byte Memory DMA (BDMA, Full Memory Mode)The byte memory DMA controller allows loading and storing of
program instructions and data using the byte memory space. The
BDMA circuit is able to access the byte memory space while the
processor is operating normally and steals only one DSP cycle
per 8-, 16- or 24-bit word transferred.
Figure 9.BDMA Control Register
The BDMA circuit supports four different data formats that are
selected by the BTYPE register field. The appropriate number
of 8-bit accesses are done from the byte memory space to build
the word size selected. Table VI shows the data formats sup-
ported by the BDMA circuit.
Table VI.Data FormatsUnused bits in the 8-bit data memory formats are filled with 0s.
The BIAD register field is used to specify the starting address
for the on-chip memory involved with the transfer. The 14-bit
BEAD register specifies the starting address for the external byte
memory space. The 8-bit BMPAGE register specifies the start-
ing page for the external byte memory space. The BDIR register
field selects the direction of the transfer. Finally, the 14-bit
BWCOUNT register specifies the number of DSP words to
transfer and initiates the BDMA circuit transfers.
BDMA accesses can cross page boundaries during sequential
addressing. A BDMA interrupt is generated on the completion
of the number of transfers specified by the BWCOUNT register.
The BWCOUNT register is updated after each transfer so it can
be used to check the status of the transfers. When it reaches zero,
the transfers have finished and a BDMA interrupt is generated.
The BMPAGE and BEAD registers must not be accessed by the
DSP during BDMA operations.
The source or destination of a BDMA transfer will always be
on-chip program or data memory.
When the BWCOUNT register is written with a nonzero value
the BDMA circuit starts executing byte memory accesses with wait
states set by BMWAIT. These accesses continue until the count
reaches zero. When enough accesses have occurred to create a
destination word, it is transferred to or from on-chip memory.
The transfer takes one DSP cycle. DSP accesses to external
memory have priority over BDMA byte memory accesses.
The BDMA Context Reset bit (BCR) controls whether the
processor is held off while the BDMA accesses are occurring.
Setting the BCR bit to 0 allows the processor to continue opera-
tions. Setting the BCR bit to 1 causes the processor to stop
execution while the BDMA accesses are occurring, to clear the
context of the processor, and start execution at address 0 when
The BDMA overlay bits specify the OVLAY memory blocks to
be accessed for internal memory. For ADSP-2186M, set to zero
BDMA overlay bits in BDMA control register.
The BMWAIT field, which has four bits on ADSP-2186M,
allows selection of up to 15 wait states for BDMA transfers.
Internal Memory DMA Port (IDMA Port; Host Memory
Mode)The IDMA Port provides an efficient means of communication
between a host system and the ADSP-2186M. The port is used
to access the on-chip program memory and data memory of the
DSP with only one DSP cycle per word overhead. The IDMA
port cannot, however, be used to write to the DSP’s memory-
mapped control registers. A typical IDMA transfer process is
described as follows:Host starts IDMA transfer.Host checks IACK control line to see if the DSP is busy.Host uses IS and IAL control lines to latch either the DMA
starting address (IDMAA) or the PM/DM OVLAY selection
into the DSP’s IDMA control registers. If Bit 15 = 1, the
value of bits 7:0 represent the IDMA overlay: bits 14:8 must
be set to 0. If Bit 15 = 0, the value of Bits 13:0 represent the
starting address of internal memory to be accessed and
Bit 14 reflects PM or DM for access. For ADSP-2186M,
IDDMOVLAY and IDPMOVLAY bits in IDMA overlay
register should be set to zero.Host uses IS and IRD (or IWR) to read (or write) DSP inter-
nal memory (PM or DM).Host checks IACK line to see if the DSP has completed the
previous IDMA operation.Host ends IDMA transfer.
The IDMA port has a 16-bit multiplexed address and data bus
and supports 24-bit program memory. The IDMA port is com-
pletely asynchronous and can be written while the ADSP-2186M
is operating at full speed.
The DSP memory address is latched and then automatically incre-
mented after each IDMA transaction. An external device can
therefore access a block of sequentially addressed memory by
specifying only the starting address of the block. This increases
throughput as the address does not have to be sent for each
memory access.
IDMA Port access occurs in two phases. The first is the IDMA
Address Latch cycle. When the acknowledge is asserted, a 14-bit
address and 1-bit destination type can be driven onto the bus by
an external device. The address specifies an on-chip memory
location, the destination type specifies whether it is a DM or
PM access. The falling edge of the IDMA address latch signal
(IAL) or the missing edge of the IDMA select signal (IS) latches
this value into the IDMAA register.
Once the address is stored, data can be read from, or written to,
the ADSP-2186M’s on-chip memory. Asserting the select line
(IS) and the appropriate read or write line (IRD and IWR
respectively) signals the ADSP-2186M that a particular transac-
tion is required. In either case, there is a one-processor-cycle
delay for synchronization. The memory access consumes one
Through the IDMAA register, the DSP can also specify the
starting address and data format for DMA operation. Asserting
the IDMA port select (IS) and address latch enable (IAL) directs
the ADSP-2186M to write the address onto the IAD0–14 bus
into the IDMA Control Register. If Bit 15 is set to 0, IDMA
latches the address. If Bit 15 is set to 1, IDMA latches into the
OVLAY register. This register, shown below, is memory mapped
at address DM (0x3FE0). Note that the latched address (IDMAA)
cannot be read back by the host. When Bit 14 in 0x3FE7 is set
to 1, timing in Figure 31 applies for short reads. When Bit 14
in 0x3FE7 is set to zero, short reads use the timing shown in Fig-
ure 32. For ADSP-2186M, IDDMOVLAY and IDPMOVLAY
bits in IDMA overlay register should be set to zero.
Refer to the following figures for more information on IDMA
and DMA memory maps.
IDMA OVERLAY
DM (0x3FE7)14131211109876543210
1 = DISABLE
IDMA CONTROL (U = UNDEFINED AT RESET)
DM (0x3FE0)14131211109876543210
1 = DM
NOTES:
1RESERVED BITS ARE SHOWN ON A GRAY FIELD.
2THESE BITS SHOULD ALWAYS BE WRITTEN WITH ZEROS.
RESERVED SET TO 0
RESERVED SET TO 0Figure 10.IDMA Control/OVLAY Registers
Figure 11.Direct Memory Access—PM and DM
Memory Maps
Bootstrap Loading (Booting)The ADSP-2186M has two mechanisms to allow automatic load-
ing of the internal program memory after reset. The method for
booting is controlled by the Mode A, B, and C configuration bits.
When the MODE pins specify BDMA booting, the ADSP-2186M
initiates a BDMA boot sequence when reset is released.
The BDMA interface is set up during reset to the following
defaults when BDMA booting is specified: the BDIR, BMPAGE,
BIAD, and BEAD registers are set to 0, the BTYPE register is
ADSP-2186MThese 32 words are used to set up the BDMA to load in the
remaining program code. The BCR bit is also set to 1, which
causes program execution to be held off until all 32 words are
loaded into on-chip program memory. Execution then begins at
address 0.
The ADSP-2100 Family development software (Revision 5.02
and later) fully supports the BDMA booting feature and can
generate byte-memory space-compatible boot code.
The IDLE instruction can also be used to allow the processor
to hold off execution while booting continues through the
BDMA interface. For BDMA accesses while in Host Mode, the
addresses to boot memory must be constructed externally to the
ADSP-2186M. The only memory address bit provided by the
processor is A0.
IDMA Port BootingThe ADSP-2186M can also boot programs through its Internal
DMA port. If Mode C = 1, Mode B = 0, and Mode A = 1, the
ADSP-2186M boots from the IDMA port. IDMA feature can
load as much on-chip memory as desired. Program execution is
held off until on-chip program memory location 0 is written to.
Bus Request and Bus GrantThe ADSP-2186M can relinquish control of the data and address
buses to an external device. When the external device requires
access to memory, it asserts the bus request (BR) signal. If the
ADSP-2186M is not performing an external memory access, it
responds to the active BR input in the following processor cycle by:Three-stating the data and address buses and the PMS, DMS,
BMS, CMS, IOMS, RD, WR output drivers,Asserting the bus grant (BG) signal, andHalting program execution.
If Go Mode is enabled, the ADSP-2186M will not halt program
execution until it encounters an instruction that requires an
external memory access.
If the ADSP-2186M is performing an external memory access
when the external device asserts the BR signal, it will not three-
state the memory interfaces nor assert the BG signal until the
processor cycle after the access completes. The instruction does
not need to be completed when the bus is granted. If a single
instruction requires two external memory accesses, the bus will
be granted between the two accesses.
When the BR signal is released, the processor releases the BG
signal, re-enables the output drivers, and continues program
execution from the point at which it stopped.
The bus request feature operates at all times, including when
the processor is booting and when RESET is active.
The BGH pin is asserted when the ADSP-2186M requires the
external bus for a memory or BDMA access, but is stopped.
The other device can release the bus by deasserting bus request.
Once the bus is released, the ADSP-2186M deasserts BG and
BGH and executes the external memory access.
Flag I/O PinsThe ADSP-2186M has eight general purpose programmable
input/output flag pins. They are controlled by two memory
read and write the values on the pins. Data being read from a
pin configured as an input is synchronized to the ADSP-2186M’s
clock. Bits that are programmed as outputs will read the value
being output. The PF pins default to input during reset.
In addition to the programmable flags, the ADSP-2186M has five
fixed-mode flags, FI, FO, FL0, FL1, and FL2. FL0–FL2 are
dedicated output flags. FI and FO are available as an alternate
configuration of SPORT1.
Note: Pins PF0, PF1, PF2, and PF3 are also used for device
configuration during reset.
Instruction Set DescriptionThe ADSP-2186M assembly language instruction set has an
algebraic syntax that was designed for ease of coding and read-
ability. The assembly language, which takes full advantage of the
processor’s unique architecture, offers the following benefits:The algebraic syntax eliminates the need to remember cryptic
assembler mnemonics. For example, a typical arithmetic add
instruction, such as AR = AX0 + AY0, resembles a simple
equation.Every instruction assembles into a single, 24-bit word that
can execute in a single instruction cycle.The syntax is a superset ADSP-2100 Family assembly lan-
guage and is completely source and object code compatible
with other family members. Programs may need to be relocated
to utilize on-chip memory and conform to the ADSP-2186M’s
interrupt vector and reset vector map.Sixteen condition codes are available. For conditional jump,
call, return, or arithmetic instructions, the condition can
be checked and the operation executed in the same instruc-
tion cycle.Multifunction instructions allow parallel execution of an
arithmetic instruction with up to two fetches or one write to
processor memory space during a single instruction cycle.
DESIGNING AN EZ-ICE-COMPATIBLE SYSTEMThe ADSP-2186M has on-chip emulation support and an
ICE-Port, a special set of pins that interface to the EZ-ICE.
These features allow in-circuit emulation without replacing the
target system processor by using only a 14-pin connection from
the target system to the EZ-ICE. Target systems must have a
14-pin connector to accept the EZ-ICE’s in-circuit probe, a
14-pin plug.
Issuing the chip reset command during emulation causes the
DSP to perform a full chip reset, including a reset of its memory
mode. Therefore, it is vital that the mode pins are set correctly
PRIOR to issuing a chip reset command from the emulator user
interface. If a passive method of maintaining mode information is
being used (as discussed in Setting Memory Modes), it does not
matter that the mode information is latched by an emulator
reset. However, if the RESET pin is being used as a method of
setting the value of the mode pins, the effects of an emulator
reset must be taken into consideration.
One method of ensuring that the values located on the mode
pins are those desired is to construct a circuit like the one shown
Figure 12.Mode A Pin/EZ-ICE Circuit
See the ADSP-2100 Family EZ-Tools data sheet for complete
information on ICE products.
The ICE-Port interface consists of the following ADSP-2186M
pins: EBR, EINT, EE, EBG, ECLK, ERESET, ELIN, EMS,
and ELOUT
These ADSP-2186M pins must be connected only to the EZ-ICE
connector in the target system. These pins have no function except
during emulation, and do not require pull-up or pull-down
resistors. The traces for these signals between the ADSP-2186M
and the connector must be kept as short as possible, no longer
than 3 inches.
The following pins are also used by the EZ-ICE: BR, BG,
RESET, and GND.
The EZ-ICE uses the EE (emulator enable) signal to take con-
trol of the ADSP-2186M in the target system. This causes the
processor to use its ERESET, EBR, and EBG pins instead of
the RESET, BR, and BG pins. The BG output is three-stated.
These signals do not need to be jumper-isolated in your system.
The EZ-ICE connects to your target system via a ribbon cable
and a 14-pin female plug. The female plug is plugged onto the
14-pin connector (a pin strip header) on the target board.
Target Board Connector for EZ-ICE ProbeThe EZ-ICE connector (a standard pin strip header) is shown in
Figure 13. You must add this connector to your target board
design if you intend to use the EZ-ICE. Be sure to allow enough
room in your system to fit the EZ-ICE probe onto the 14-pin
connector.
Figure 13.Target Board Connector for EZ-ICE
The 14-pin, 2-row pin strip header is keyed at the Pin 7 loca-
tion—Pin 7 must be removed from the header. The pins must
be 0.025 inch square and at least 0.20 inch in length. Pin spac-
ing should be 0.1 × 0.1 inches. The pin strip header must have
at least 0.15 inch clearance on all sides to accept the EZ- ICE
probe plug.
Pin strip headers are available from vendors such as 3M,
McKenzie, and Samtec.
Target Memory InterfaceFor your target system to be compatible with the EZ-ICE
emulator, it must comply with the memory interface guidelines
listed below.
PM, DM, BM, IOM, AND CMDesign your Program Memory (PM), Data Memory (DM), Byte
Memory (BM), I/O Memory (IOM), and Composite Memory
(CM) external interfaces to comply with worst case device tim-
ing requirements and switching characteristics as specified in
this data sheet. The performance of the EZ- ICE may approach
published worst-case specification for some memory access
timing requirements and switching characteristics.
Note: If your target does not meet the worst-case chip specifica-
tion for memory access parameters, you may not be able to
emulate your circuitry at the desired CLKIN frequency. Depend-
ing on the severity of the specification violation, you may have
trouble manufacturing your system as DSP components statisti-
cally vary in switching characteristic and timing requirements
within published limits.
Restriction: All memory strobe signals on the ADSP-2186M
(RD, WR, PMS, DMS, BMS, CMS, and IOMS) used in your
target system must have 10 kΩ pull-up resistors connected when
the EZ-ICE is being used. The pull-up resistors are necessary
because there are no internal pull-ups to guarantee their state
during prolonged three-state conditions resulting from typical
EZ-ICE debugging sessions. These resistors may be removed at
your option when the EZ-ICE is not being used.
Target System Interface SignalsWhen the EZ-ICE board is installed, the performance on some
system signals change. Design your system to be compatible
with the following system interface signal changes introduced by
the EZ-ICE board:EZ-ICE emulation introduces an 8 ns propagation delay
between your target circuitry and the DSP on the RESET
signal.EZ-ICE emulation introduces an 8 ns propagation delay
between your target circuitry and the DSP on the BR signal.EZ-ICE emulation ignores RESET and BR when single-
stepping.EZ-ICE emulation ignores RESET and BR when in Emulator
Space (DSP halted).EZ-ICE emulation ignores the state of target BR in certain
modes. As a result, the target system may take control of the
DSP’s external memory bus only if bus grant (BG) is asserted
by the EZ- ICE board’s DSP.
ADSP-2186M–SPECIFICATIONS
RECOMMENDED OPERATING CONDITIONSVDDEXT
VINPUT
NOTESThe ADSP-2186M is 3.3 V tolerant (always accepts up to 3.6 V max VIH), but voltage compliance (on outputs, VOH) depends on the input VDDEXT; because VOH (max)
≈ VDDEXT (max). This applies to bidirectional pins (D0–D23, RFS0, RFS1, SCLK0, SCLK1, TFS0, TFS1, A1–A13, PF0–PF7) and input only pins (CLKIN, RESET,
BR, DR0, DR1, PWD).
Specifications subject to change without notice.
ELECTRICAL CHARACTERISTICSVIH
VIL
VOH
VOL
IIL
IOZH
IOZL
IDD
IDD
IDD
IDD
NOTESBidirectional pins: D0–D23, RFS0, RFS1, SCLK0, SCLK1, TFS0, TFS1, A1–A13, PF0–PF7.Input only pins: RESET, BR, DR0, DR1, PWD.Input only pins: CLKIN, RESET, BR, DR0, DR1, PWD.Output pins: BG, PMS, DMS, BMS, IOMS, CMS, RD, WR, PWDACK, A0, DT0, DT1, CLKOUT, FL2–0, BGH.Although specified for TTL outputs, all ADSP-2186M outputs are CMOS-compatible and will drive to VDDEXT and GND, assuming no dc loads.Guaranteed but not tested.Three-statable pins: A0–A13, D0–D23, PMS, DMS, BMS, IOMS, CMS, RD, WR, DT0, DT1, SCLK0, SCLK1, TFS0, TFS1, RFS0, RFS1, PF0–PF7.0 V on BR.Idle refers to ADSP-2186M state of operation during execution of IDLE instruction. Deasserted pins are driven to either VDD or GND.IDD measurement taken with all instructions executing from internal memory. 50% of the instructions are multifunction (Types 1, 4, 5, 12, 13, 14), 30% are Type 2
and Type 6, and 20% are idle instructions.VIN = 0 V and 3 V. For typical figures for supply currents, refer to Power Dissipation section.See Chapter 9 of the ADSP-2100 Family User’s Manual for details.Output pin capacitance is the capacitive load for any three-stated output pin.
Specifications subject to change without notice.
ABSOLUTE MAXIMUM RATINGS1NOTESStresses greater than those listed may cause permanent damage to the device.
These are stress ratings only; functional operation of the device at these or any other
conditions greater than those indicated in the operational sections of this specifi-
cation is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.Applies to Bidirectional pins (D0–D23, RFS0, RFS1, SCLK0, SCLK1, TFS0,
TFS1, A1–A13, PF0–PF7) and Input only pins (CLKIN, RESET, BR, DR0,
DR1, PWD).Applies to Output pins (BG, PMS, DMS, BMS, IOMS, CMS, RD, WR, PWDACK,
A0, DT0, DT1, CLKOUT, FL2–0, BGH).
TIMING SPECIFICATIONS
GENERAL NOTESUse the exact timing information given. Do not attempt to
derive parameters from the addition or subtraction of others.
While addition or subtraction would yield meaningful results for
an individual device, the values given in this data sheet reflect
statistical variations and worst cases. Consequently, you cannot
meaningfully add up parameters to derive longer times.
TIMING NOTESSwitching characteristics specify how the processor changes its
signals. You have no control over this timing—circuitry external
to the processor must be designed for compatibility with these
signal characteristics. Switching characteristics tell you what the
processor will do in a given circumstance. You can also use
switching characteristics to ensure that any timing require-
ment of a device connected to the processor (such as memory)
is satisfied.
Timing requirements apply to signals that are controlled by
circuitry external to the processor, such as the data input for a
read operation. Timing requirements guarantee that the proces-
sor operates correctly with other devices.
MEMORY TIMING SPECIFICATIONSThe table below shows common memory device specifications
and the corresponding ADSP-2186M timing parameters, for
your convenience.
NOTExMS = PMS, DMS, BMS, CMS or IOMS.
ESD SENSITIVITYESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the ADSP-2186M features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
ADSP-2186MEach address and data pin has a 10 pF total load at the pin.The application operates at VDDEXT = 3.3 V and tCK = 30 ns.
Total Power Dissipation = PINT + (C × VDDEXT2 × f)
PINT = internal power dissipation from Power vs. Frequency
graph (Figure 15).
(C × VDDEXT2 × f) is calculated for each output:
Total power dissipation for this example is PINT + 38.0 mW.
Output Drive CurrentsFigure 14 shows typical I-V characteristics for the output drivers
on the ADSP-2186M. The curves represent the current drive
capability of the output drivers as a function of output voltage.
Figure 14.Typical Output Driver Characteristics
FREQUENCY DEPENDENCY FOR TIMING
SPECIFICATIONStCK is defined as 0.5 tCKI. The ADSP-2186M uses an input clock
with a frequency equal to half the instruction rate. For example,
a 37.50 MHz input clock (which is equivalent to 26.6 ns) yields
a 13.3 ns processor cycle (equivalent to 75 MHz). tCK values
within the range of 0.5 tCKI period should be substituted for all
relevant timing parameters to obtain the specification value.
Example:tCKH = 0.5 tCK – 2 ns = 0.5 (15 ns) – 2 ns = 5.5 ns
ENVIRONMENTAL CONDITIONS1NOTEWhere the Ambient Temperature Rating (TAMB) is:
TAMB = TCASE – (PD × θCA)
TCASE = Case Temperature in °C
PD = Power Dissipation in W
POWER DISSIPATIONTo determine total power dissipation in a specific application,
the following equation should be applied for each output:
C × VDD2 × f
C = load capacitance, f = output switching frequency.
Example:
In an application where external data memory is used and no other
outputs are active, power dissipation is calculated as follows:
Assumptions:External data memory is accessed every cycle with 50% of the
address pins switching.External data memory writes occur every other cycle with
50% of the data pins switching.
