ADSP-2189NKST-320 ,DSP MicrocomputerFEATURESSingle-Cycle Context Switch Flexible I/O Allows 1.8 V, 2.5 V or 3.3 V Operation3-Bus Archit ..
ADSP-2191MBST-140 ,DSP MicrocomputerGENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . .3Memory RAM and 32K Words 16-Bit Memor ..
ADSP-2191MBST-140 ,DSP MicrocomputerGENERAL DESCRIPTIONuses an algebraic syntax for ease of coding and readability. A The ADSP-2191M DS ..
ADSP-2191MBST-140 ,DSP MicrocomputerFEATURESPower Supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11Host Port with D ..
ADSP-2191MKCA-160 ,DSP MicrocomputerSPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . 18Two SPI-Compatible Ports with ..
ADSP-2191MKST-160 ,DSP MicrocomputerSPECIFICATIONS . . . . . . . . . . . . . . . . .20Three Programmable Interval Timers with PWM Outp ..
AM26C31CD ,Quadruple Differential Line DriverFeatures section and added the Applications section, the Device Information table, ESD Ratings tabl ..
AM26C31CDB , QUADRUPLE DIFFERENTIAL LINE DRIVERS
AM26C31CDBR ,Quadruple Differential Line DriverElectrical Characteristics: AM26C31Q and12 Device and Documentation Support........ 15AM26C31M. 612 ..
AM26C31CDBRG4 ,Quadruple Differential Line Driver 16-SSOP 0 to 70Features 3 DescriptionThe AM26C31 device is a differential line driver with1• Meets or Exceeds the ..
AM26C31CDG4 ,Quadruple Differential Line Driver 16-SOIC 0 to 70Block Diagrams. 103 Description....... 18.3 Feature Description.... 114 Revision History........ 28 ..
AM26C31CDR ,Quadruple Differential Line DriverMaximum Ratings . 49.2 Typical Application .... 126.2 ESD Ratings........ 410 Power Supply Recommen ..
ADSP-2185NBST-320-ADSP-2185NKST-320-ADSP2186NKST320-ADSP-2186NKST-320-ADSP2186NKST-320-ADSP-2187NKST-320-ADSP-2188NBST-320-ADSP2188NBST-320-ADSP-2188NKST-320-ADSP-2189NBST-320-ADSP-2189NKST-320
DSP Microcomputer
DSP MicrocomputerREV. 0
ICE-Port is a trademark of Analog Devices, Inc.
PERFORMANCE FEATURES
12.5 ns Instruction Cycle Time @1.8 V (Internal), 80 MIPS
Sustained Performance
Single-Cycle Instruction Execution
Single-Cycle Context Switch
3-Bus Architecture Allows Dual Operand Fetches in
Every Instruction Cycle
Multifunction Instructions
Power-Down Mode Featuring Low CMOS Standby
Power Dissipation with 200CLKIN Cycle Recovery
from Power-Down Condition
Low Power Dissipation in Idle Mode
INTEGRATION FEATURES
ADSP-2100 Family Code Compatible (Easy to Use
Algebraic Syntax), with Instruction Set Extensions
Up to 256K Bytes of On-Chip RAM, Configured as
Up to 48K Words Program Memory RAM
Up to 56K Words Data Memory RAM
Dual-Purpose Program Memory for Both Instruction and
Data Storage
Independent ALU, Multiplier/Accumulator, and Barrel
Shifter Computational Units
Two Independent Data Address Generators
Powerful Program Sequencer Provides Zero Overhead
Looping Conditional Instruction Execution
Programmable 16-Bit Interval Timer with Prescaler
100-Lead LQFP and 144-Ball Mini-BGA
SYSTEM INTERFACE FEATURES
Flexible I/O Allows 1.8 V, 2.5V or 3.3V Operation
All Inputs Tolerate up to 3.6V Regardless of Mode
16-Bit Internal DMA Port for High-Speed Access to On-
Chip Memory (Mode Selectable)
4M-Byte Memory Interface for Storage of Data Tables
and Program Overlays (Mode Selectable)
8-Bit DMA to Byte Memory for Transparent Program and
Data Memory Transfers (Mode Selectable)
Programmable Memory Strobe and Separate I/O
Memory Space Permits “Glueless” System Design
Programmable Wait State Generationwo Double-Buffered Serial Ports with Companding
Hardware and Automatic Data Buffering
Automatic Booting of On-Chip Program Memory from
Byte-Wide External Memory, e.g., EPROM, or through
Internal DMA Port
Six External Interrupts
13 Programmable Flag Pins Provide Flexible System
Signaling
UART Emulation through Software SPORT
Reconfiguration
ICE-Port™ Emulator Interface Supports Debugging in
Final Systems
FUNCTIONAL BLOCK DIAGRAM
ADSP-218xN Series
GENERAL DESCRIPTIONThe ADSP-218xN series consists of six single chip micro-
computers optimized for digital signal processing applica-
tions. The high-level block diagram for the ADSP-218xN
series members appears on the previous page. All series
members are pin-compatible and are differentiated solely by
the amount of on-chip SRAM. This feature, combined with
ADSP-21xx code compatibility, provides a great deal of
flexibility in the design decision. Specific family members
are shown in Table1.
ADSP-218xN series members combine the ADSP-2100
family base architecture (three computational units, data
address generators, and a program sequencer) with two
serial ports, a 16-bit internal DMA port, a byte DMA port,
a programmable timer, Flag I/O, extensive interrupt capa-
bilities, and on-chip program and data memory.
ADSP-218xN series members integrate up to 256Kbytes
of on-chip memory configured as up to 48Kwords (24-bit)
of program RAM, and up to 56Kwords (16-bit) of data
RAM. Power-down circuitry is also provided to meet the
low power needs of battery-operated portable equipment.
The ADSP-218xN is available in a 100-lead LQFP package
and 144-Ball Mini-BGA.
Fabricated in a high-speed, low-power, 0.18µm CMOS
process, ADSP-218xN series members operate with a
12.5ns instruction cycle time. Every instruction can
execute in a single processor cycle.
The ADSP-218xN’s flexible architecture and comprehen-
sive instruction set allow the processor to perform multiple
operations in parallel. In one processor cycle, ADSP-218xN
series members can:Generate the next program addressFetch the next instructionPerform one or two data movesUpdate one or two data address pointersPerform a computational operation
This takes place while the processor continues to:Receive and transmit data through the two serial portsReceive and/or transmit data through the
internalDMAportReceive and/or transmit data through the byte DMA port
Decrement timer
DEVELOPMENT SYSTEMAnalog Devices’ wide range of software and hardware
development tools supports the ADSP-218xN series. The
DSP tools include an integrated development environment,
an evaluation kit, and a serial port emulator.
VisualDSP++™ is an integrated development environment,
allowing for fast and easy development, debug, and deploy-
ment. The VisualDSP++ project management environment
lets programmers develop and debug an application. This
environment includes an easy-to-use assembler that is based
on an algebraic syntax; an archiver (librarian/library build-
er); a linker; a PROM-splitter utility; a cycle-accurate,
instruction-level simulator; a C compiler; and a C run-time
library that
includes DSP and mathematical functions.
Debugging both C and assembly programs with the
VisualDSP++ debugger, programmers can:View mixed C and assembly code (interleaved source and
object information)Insert break pointsSet conditional breakpoints on registers, memory, and
stacksTrace instruction executionFill and dump memorySource level debugging
The VisualDSP++ IDE lets programmers define and
manage DSP software development. The dialog boxes and
property pages let programmers configure and manage all
of the ADSP-218xN development tools, including the
syntax highlighting in the VisualDSP++ editor. This capa-
bility controls how the development tools process inputs and
generate outputs.
The ADSP-2189M EZ-KIT Lite™ provides developers
with a cost-effective method for initial evaluation of the
powerful ADSP-218xN DSP family architecture. The
ADSP-2189M EZ-KIT Lite includes a stand-alone ADSP-
2189M DSP board supported by an evaluation suite of
VisualDSP++. With this EZ-KIT Lite, users can learn
about DSP hardware and software development and evalu-
ate potential applications of the ADSP-218xN series. The
ADSP-2189M EZ-KIT Lite provides an evaluation suite of
the VisualDSP++ development environment with the compiler, assembler, and linker. The size of the DSP
erxecutable that can be built using the EZ-KIT Lite tools is
Table 1. ADSP-218xN DSP Microcomputer Family
The EZ-KIT Lite includes the following features:75 MHz ADSP-2189MFull 16-Bit Stereo Audio I/O with AD73322 CodecRS-232 InterfaceEZ-ICE Connector for Emulator ControlDSP Demonstration ProgramsEvaluation Suite of VisualDSP++
The ADSP-218x EZ-ICE® Emulator provides an easier and
more cost-effective method for engineers to develop and
optimize DSP systems, shortening product development
cycles for faster time-to-market. ADSP-218xN series
members integrate on-chip emulation support with a 14-pin
ICE-Port interface. This interface provides a simpler target
board connection that requires fewer mechanical clearance
considerations than other ADSP-2100 Family EZ-ICEs.
ADSP-218xN series members need not be removed from
the target system when using the EZ-ICE, nor are any adapt-
ers needed. Due to the small footprint of the EZ-ICE con-
nector, emulation can be supported in final board
designs.The EZ-ICE performs a full range of functions,
including:
In-target operationUp to 20 breakpointsSingle-step or full-speed operationRegisters and memory values can be examined
andalteredPC upload and download functionsInstruction-level emulation of program booting
andexecutionComplete assembly and disassembly of instructionsC source-level debugging
Additional InformationThis data sheet provides a general overview of ADSP-
218xN series functionality. For additional information on
the architecture and instruction set of the processor, refer
to the ADSP-218x DSP Hardware Reference and the ADSP-
218x DSP Instruction Set Reference.
ARCHITECTURE OVERVIEWThe ADSP-218xN series instruction set provides flexible
data moves and multifunction (one or two data moves with
a computation) instructions. Every instruction can be exe-
cuted in a single processor cycle. The ADSP-218xN assem-
bly language uses an algebraic syntax for ease of coding and
readability. A comprehensive set of development tools sup-
ports program development.
The functional block diagram is an overall block diagram of
the ADSP-218xN series. The processor contains three in-
dependent computational units: the ALU, the multiplier/
accumulator (MAC), and the shifter. The computational
units process 16-bit data directly and have provisions to
support multiprecision computations. The ALU performs
a standard set of arithmetic and logic operations; division
primitives are also supported. The MAC performs single-
cycle multiply, multiply/add, and multiply/subtract opera-
tions with 40bits of accumulation. The shifter performs
logical and arithmetic shifts, normalization, denormaliza-
tion, and derive exponent operations.
The shifter can be used to efficiently implement numeric
format control, including multiword and block floating-
point representations.
The internal result (R) bus connects the computational
units so that the output of any unit may be the input of any
unit on the next cycle.
A powerful program sequencer and two dedicated data
address generators ensure efficient delivery of operands to
these computational units. The sequencer supports condi-
tional jumps, subroutine calls, and returns in a single cycle.
With internal loop counters and loop stacks, ADSP-218xN
series members execute looped code with zero overhead; no
explicit jump instructions are required to maintain loops.
Two data address generators (DAGs) provide addresses for
simultaneous dual operand fetches (from data memory and
program memory). Each DAG maintains and updates four
address pointers. Whenever the pointer is used to access
data (indirect addressing), it is post-modified by the value
of one of four possible modify registers. A length value may
be associated with each pointer to implement automatic
modulo addressing for circular buffers.
Five internal buses provide efficient data transfer:Program Memory Address (PMA) BusProgram Memory Data (PMD) BusData Memory Address (DMA) BusData Memory Data (DMD) BusResult (R) Bus
The two address buses (PMA and DMA) share a single
external address bus, allowing memory to be expanded off-
chip, and the two data buses (PMD and DMD) share a
single external data bus. Byte memory space and I/O
memory space also share the external buses.
Program memory can store both instructions and data, per-
mitting ADSP-218xN series members to fetch two oper-
ands in a single cycle, one from program memory and one
from data memory. ADSP-218xN series members can fetch
an operand from program memory and the next instruction
in the same cycle.
In lieu of the address and data bus for external memory
connection, ADSP-218xN series members may be config-
ured for 16-bit Internal DMA port (IDMA port) connec-
tion to external systems. The IDMA port is made up of 16
ADSP-218xN Seriesdata/address pins and five control pins. The IDMA port
provides transparent, direct access to the DSP’s on-chip
program and data RAM.
An interface to low-cost byte-wide memory is provided by
the Byte DMA port (BDMA port). The BDMA port is
bidirectional and can directly address up to four megabytes
of external RAM or ROM for off-chip storage of program
overlays or data tables.
The byte memory and I/O memory space interface supports
slow memories and I/O memory-mapped peripherals with
programmable wait state generation. External devices can
gain control of external buses with bus request/grant signals
(BR, BGH, and BG). One execution mode (Go Mode)
allows the ADSP-218xN to continue running from on-chip
memory. Normal execution mode requires the processor to
halt while buses are granted.
ADSP-218xN series members can respond to eleven inter-
rupts. There can be up to six external interrupts (one edge-
sensitive, two level-sensitive, and three configurable) and
seven internal interrupts generated by the timer, the serial
ports (SPORT), the Byte DMA port, and the power-down
circuitry. There is also a master RESET signal. The two
serial ports provide a complete synchronous serial interface
with optional companding in hardware and a wide variety
of framed or frameless data transmit and receive modes of
operation.
Each port can generate an internal programmable serial
clock or accept an external serial clock.
ADSP-218xN series members provide up to 13 general-
purpose flag pins. The data input and output pins on
SPORT1 can be alternatively configured as an input flag
and an output flag. In addition, eight flags are programma-
ble as inputs or outputs, and three flags are always outputs.
A programmable interval timer generates periodic inter-
rupts. A 16-bit count register (TCOUNT) decrements
every n processor cycle, where n is a scaling value stored
in an 8-bit register (TSCALE). When the value of the count
register reaches zero, an interrupt is generated and the
count register is reloaded from a 16-bit period register
(TPERIOD).
Serial PortsADSP-218xN series members incorporate two complete
synchronous serial ports (SPORT0 and SPORT1) for serial
communications and multiprocessor communication.
Following is a brief list of the capabilities of the ADSP-
218xN SPORTs. For additional information on Serial
Ports, refer to the ADSP-218x DSP Hardware Reference.SPORTs are bidirectional and have a separate, double-
buffered transmit and receive section.SPORTs can use an external serial clock or generate their
ownserial clock internally.SPORTs have independent framing for the receive and
transmit sections. Sections run in a frameless mode or
with frame synchronization signals internally or externally
generated. Frame sync signals are active high or inverted,
with either of two pulsewidths and timings.SPORTs support serial data word lengths from 3 to bits and provide optional A-law and μ-law compand-
ing, according to CCITT recommendation G.711.SPORT receive and transmit sections can generate
unique interrupts on completing a data word transfer.SPORTs can receive and transmit an entire circular buffer
of data with only one overhead cycle per data word. An
interrupt is generated after a data buffer transfer.SPORT0 has a multichannel interface to selectively
receive and transmit a 24 or 32word, time-division mul-
tiplexed, serial bitstream.SPORT1 can be configured to have two external inter-
rupts (IRQ0 and IRQ1) and the FI and FO signals. The
internally generated serial clock may still be used in this
configuration.
PIN DESCRIPTIONSADSP-218xN series members are available in a 100-lead
LQFP package and a 144-Ball Mini-BGA package. In order
to maintain maximum functionality and reduce package size
and pin count, some serial port, programmable flag, inter-
rupt and external bus pins have dual, multiplexed function-
ality. The external bus pins are configured during RESET
only, while serial port pins are software configurable during
program execution. Flag and interrupt functionality is
retained concurrently on multiplexed pins. In cases where
pin functionality is reconfigurable, the default state is shown
in plain text in Table2, while alternate functionality is
shown in italics.
Table 2. Common-Mode Pins Interrupt/Flag pins retain both functions concurrently. If IMASK is set to enable the corresponding interrupts, the DSP will
vector to the appropriate interrupt vector address when the pin is asserted, either by external devices or set as a programmable
flag.SPORT configuration determined by the DSP System Control Register. Software configurable.
ADSP-218xN Series
Memory Interface PinsADSP-218xN series members can be used in one of two
modes: Full Memory Mode, which allows BDMA operation
with full external overlay memory and I/O capability, or
Host Mode, which allows IDMA operation with limited
external addressing capabilities.
The operating mode is determined by the state of the Mode
C pin during RESET and cannot be changed while the
processor is running. Table3 and Table4 list the active
signals at specific pins of the DSP during either of the two
operating modes (Full Memory or Host). A signal in one
table shares a pin with a signal from the other table, with the
active signal determined by the mode that is set. For the
shared pins and their alternate signals (e.g., A4/IAD3), refer
to the package pinouts in Table27 on page40 and Table28
on page42.
Terminating Unused PinsTable5 shows the recommendations for terminating
unused pins.
Table 3. Full Memory Mode Pins (Mode C = 0)
Table 4. Host Mode Pins (Mode C = 1) In Host Mode, external peripheral addresses can be decoded using the A0, CMS, PMS, DMS, and IOMS signals.
Table 5. Unused Pin Terminations
CLKIN, RESET, and PF3–0/Mode D–A are not included in this table because these pins must be used.All bidirectional pins have three-stated outputs. When the pin is configured as an output, the output is Hi-Z (high impedance) when inactive.Hi-Z = High Impedance.If the CLKOUT pin is not used, turn it OFF, using CLKODIS in SPORT0 autobuffer control register.If the Interrupt/Programmable Flag pins are not used, there are two options: Option 1: When these pins are configured as INPUTS at reset and function as interrupts and input flag pins, pull the pins High (inactive). Option 2: Program the unused pins as OUTPUTS, set them to 1 prior to enabling interrupts,
and let pins float.
Table 5. Unused Pin Terminations (Continued)
ADSP-218xN Series
InterruptsThe interrupt controller allows the processor to respond to
the eleven possible interrupts and reset with minimum over-
head. ADSP-218xN series members provide four dedicated
external interrupt input pins: IRQ2, IRQL0, IRQL1, and
IRQE (shared with the PF7–4 pins). In addition, SPORT1
may be reconfigured for IRQ0, IRQ1, FI and FO, for a total
of six external interrupts. The ADSP-218xN also supports
internal interrupts from the timer, the byte DMA port, the
two serial ports, software, and the power-down control cir-
cuit. The interrupt levels are internally prioritized and indi-
vidually maskable (except power-down and reset). The
IRQ2, IRQ0, and IRQ1 input pins can be programmed to
be either level- or edge-sensitive. IRQL0 and IRQL1 are
level-sensitive and IRQE is edge-sensitive. The priorities
and vector addresses of all interrupts are shown in Table6.
Interrupt routines can either be nested with higher priority
interrupts taking precedence or processed sequentially. In-
terrupts can be masked or unmasked with the IMASK reg-
ister. Individual interrupt requests are logically ANDed
with the bits in IMASK; the highest priority unmasked in-
terrupt is then selected. The power-down interrupt is non-
maskable.
ADSP-218xN series members mask all interrupts for one
instruction cycle following the execution of an instruction
that modifies the IMASK register. This does not affect serial
port autobuffering or DMA transfers.
The interrupt control register, ICNTL, controls interrupt
nesting and defines the IRQ0, IRQ1, and IRQ2 external
interrupts to be either edge- or level-sensitive. The IRQE
pin is an external edge-sensitive interrupt and can be forced
and cleared. The IRQL0 and IRQL1 pins are external level
The IFC register is a write-only register used to force and
clear interrupts. On-chip stacks preserve the processor
status and are automatically maintained during interrupt
handling. The stacks are 12 levels deep to allow interrupt,
loop, and subroutine nesting. The following instructions
allow global enable or disable servicing of the interrupts
(including power-down), regardless of the state of IMASK:
ENAINTS;
DISINTS;Disabling the interrupts does not affect serial port auto-
buffering or DMA. When the processor is reset, interrupt
servicing is enabled.
LOW-POWER OPERATIONADSP-218xN series members have three low-power modes
that significantly reduce the power dissipation when the
device operates under standby conditions. These modes are:Power-Down
IdleSlow Idle
The CLKOUT pin may also be disabled to reduce external
power dissipation.
Power-DownADSP-218xN series members have a low-power feature that
lets the processor enter a very low-power dormant state
through hardware or software control. Following is a brief
list of power-down features. Refer to the ADSP-218x DSP
Hardware Reference, “System Interface” chapter, for detailed
information about the power-down feature.Quick recovery from power-down. The processor begins
executing instructions in as few as 200 CLKIN cycles.Support for an externally generated TTL or CMOS
processor clock. The external clock can continue running
during power-down without affecting the lowest power
rating and 200 CLKIN cycle recovery.Support for crystal operation includes disabling the oscil-
lator to save power (the processor automatically waits
approximately 4096CLKIN cycles for the crystal oscilla-
tor to start or stabilize), and letting the oscillator run to
allow 200CLKIN cycle start-up.Power-down is initiated by either the power-down pin
(PWD) or the software power-down force bit. Interrupt
support allows an unlimited number of instructions to be
executed before optionally powering down. The power-
down interrupt also can be used as a nonmaskable, edge-
sensitive interrupt.Context clear/save control allows the processor to
continue where it left off or start with a clean context when
leaving the power-down state.
Table 6. Interrupt Priority and Interrupt Vector
Addresses
The RESET pin also can be used to terminate power-
down. Power-down acknowledge pin (PWDACK) indicates
when the processor has entered power-down.
IdleWhen the ADSP-218xN is in the Idle Mode, the processor
waits indefinitely in a low-power state until an interrupt
occurs. When an unmasked interrupt occurs, it is serviced;
execution then continues with the instruction following the
IDLE instruction. In Idle mode IDMA, BDMA, and auto-
buffer cycle steals still occur.
Slow IdleThe IDLE instruction is enhanced on ADSP-218xN series
members to let the processor’s internal clock signal be
slowed, further reducing power consumption. The reduced
clock frequency, a programmable fraction of the normal
clock rate, is specified by a selectable divisor given in the
IDLE instruction.
The format of the instruction is:
IDLE(N);where N = 16, 32, 64, or 128. This instruction keeps the
processor fully functional, but operating at the slower clock
rate. While it is in this state, the processor’s other internal
clock signals, such as SCLK, CLKOUT, and timer clock,
are reduced by the same ratio. The default form of the in-
struction, when no clock divisor is given, is the standard
IDLE instruction.
When the IDLE (n) instruction is used, it effectively slows
down the processor’s internal clock and thus its response
time to incoming interrupts. The one-cycle response time
of the standard idle state is increased by n, the clock divisor.
When an enabled interrupt is received, ADSP-218xN series
members remain in the idle state for up to a maximum of n
processor cycles (n = 16, 32, 64, or 128) before resuming
normal operation.
When the IDLE (n) instruction is used in systems that have
an externally generated serial clock (SCLK), the serial clock
rate may be faster than the processor’s reduced internal
clock rate. Under these conditions, interrupts must not be
generated at a faster rate than can be serviced, due to the
additional time the processor takes to come out of the idle
state (a maximum of n processor cycles).
SYSTEM INTERFACEFigure1 shows typical basic system configurations with the
ADSP-218xN series, two serial devices, a byte-wide
EPROM, and optional external program and data overlay
memories (mode-selectable). Programmable wait state gen-
eration allows the processor to connect easily to slow periph-
eral devices. ADSP-218xN series members also provide
four external interrupts and two serial ports or six external
interrupts and one serial port. Host Memory Mode allows
access to the full external data bus, but limits addressing to
a single address bit (A0). Through the use of external hard-
ware, additional system peripherals can be added in this
mode to generate and latch address signals.
ADSP-218xN Series
Clock SignalsADSP-218xN series members can be clocked by either a
crystal or a TTL-compatible clock signal.
The CLKIN input cannot be halted, changed during oper-
ation, nor operated below the specified frequency during
normal operation. The only exception is while the processor
is in the power-down state. For additional information, refer
to the ADSP-218x DSP Hardware Reference, for detailed
information on this power-down feature.
If an external clock is used, it should be a TTL-compatible
signal running at half the instruction rate. The signal is
connected to the processor’s CLKIN input. When an exter-
nal clock is used, the XTAL pin must be left unconnected.
ADSP-218xN series members use an input clock with a
frequency equal to half the instruction rate; a 40MHz input
clock yields a 12.5 ns processor cycle (which is equivalent
to 80MHz). Normally, instructions are executed in a single
processor cycle. All device timing is relative to the internal
instruction clock rate, which is indicated by the CLKOUT
signal when enabled.
Because ADSP-218xN series members include an on-chip
oscillator circuit, an external crystal may be used. The
crystal should be connected across the CLKIN and XTAL
pins, with two capacitors connected as shown in Figure2.
Capacitor values are dependent on crystal type and should
be specified by the crystal manufacturer. A parallel-
resonant, fundamental frequency, microprocessor-grade
crystal should be used.
A clock output (CLKOUT) signal is generated by the pro-
cessor at the processor’s cycle rate. This can be enabled and
disabled by the CLKODIS bit in the SPORT0 Autobuffer
Control Register.
RESETThe RESET signal initiates a master reset of the ADSP-
218xN. The RESET signal must be asserted during the
power-up sequence to assure proper initialization. RESET
during initial power-up must be held long enough to allow
the internal clock to stabilize. If RESET is activated any time
after power-up, the clock continues to run and does not
require stabilization time.
The power-up sequence is defined as the total time required
for the crystal oscillator circuit to stabilize after a valid VDD
is applied to the processor, and for the internal phase-locked
loop (PLL) to lock onto the specific crystal frequency. A
minimum of 2000CLKIN cycles ensures that the PLL has
locked, but does not include the crystal oscillator start-up
time. During this power-up sequence the RESET signal
should be held low. On any subsequent resets, the RESET
signal must meet the minimum pulse-width specification
(tRSP).
The RESET input contains some hysteresis; however, if an
RC circuit is used to generate the RESET signal, the use of
an external Schmitt trigger is recommended.
The master reset sets all internal stack pointers to the empty
stack condition, masks all interrupts, and clears the MSTAT
register. When RESET is released, if there is no pending
bus request and the chip is configured for booting, the boot-
loading sequence is performed. The first instruction is
fetched from on-chip program memory location 0x0000
once boot loading completes.
POWER SUPPLIESADSP-218xN series members have separate power supply
connections for the internal (VDDINT) and external (VDDEXT)
power supplies. The internal supply must meet the 1.8V
requirement. The external supply can be connected to a
1.8V, 2.5V, or 3.3V supply. All external supply pins must
be connected to the same supply. All input and I/O pins can
tolerate input voltages up to 3.6V, regardless of the external
supply voltage. This feature provides maximum flexibility
in mixing 1.8 V, 2.5V, or 3.3V components.
Figure 2. External Crystal Connections
MODES OF OPERATIONThe ADSP-218xN series modes of operation appear in
Table7.
Setting Memory ModeMemory Mode selection for the ADSP-218xN series is
made during chip reset through the use of the Mode C pin.
This pin is multiplexed with the DSP’s PF2 pin, so care must
be taken in how the mode selection is made. The two meth-
ods for selecting the value of Mode C are active and passive.
Passive ConfigurationPassive Configuration involves the use of a pull-up or pull-
down resistor connected to the Mode C pin. To minimize
power consumption, or if the PF2 pin is to be used as
an output in the DSP application, a weak pull-up or pull-
down resistance, on the order of 10k�, can be used. This
value should be sufficient to pull the pin to the desired level
and still allow the pin to operate as a programmable flag
output without undue strain on the processor’s output
driver. For minimum power consumption during power-
down, reconfigure PF2 to be an input, as the pull-up or pull-
down resistance will hold the pin in a known state, and will
not switch.
Active ConfigurationActive Configuration involves the use of a three-statable
external driver connected to the Mode C pin. A driver’s
output enable should be connected to the DSP’s RESET
signal such that it only drives the PF2 pin when RESET is
active (low). When RESET is deasserted, the driver should
be three-state, thus allowing full use of the PF2 pin as either
an input or output. To minimize power consumption during
power-down, configure the programmable flag as an output
when connected to a three-stated buffer. This ensures that
the pin will be held at a constant level, and will not oscillate
should the three-state driver’s level hover around the logic
switching point.
IDMA ACK ConfigurationMode D = 0 and in host mode: IACK is an active, driven
signal and cannot be “wire ORed.” Mode D = 1 and in host
mode: IACK is an open drain and requires an external
pull-down, but multiple IACK pins can be “wire ORed”
together.
Table 7. Modes of Operation Considered as standard operating settings. Using these configurations allows for easier design and better memory management.
ADSP-218xN Series
MEMORY ARCHITECTUREThe ADSP-218xN series provides a variety of memory and
peripheral interface options. The key functional groups are
Program Memory, Data Memory, Byte Memory, and I/O.
Refer to Figure3 through Figure8, Table8 on page14, and
Table9 on page14 for PM and DM memory allocations in
the ADSP-218xN series.
Figure 3. ADSP-2184 Memory Architecture
Figure 4. ADSP-2185 Memory Architecture
Figure 5. ADSP-2186 Memory Architecture
Figure 6. ADSP-2187 Memory Architecture
Figure 7. ADSP-2188 Memory Architecture
Figure 8. ADSP-2189 Memory Architecture
ADSP-218xN Series
Program MemoryProgram Memory (Full Memory Mode) is a 24-bit-wide
space for storing both instruction opcodes and data. The
ADSP-218xN series has up to 48K words of Program
Memory RAM on chip, and the capability of accessing up
to two 8K external memory overlay spaces, using the exter-
nal data bus.
Program Memory (Host Mode) allows access to all internal
memory. External overlay access is limited by a single exter-
nal address line (A0). External program execution is not
available in host mode due to a restricted data bus that is
only 16bits wide.
Data MemoryData Memory (Full Memory Mode) is a 16-bit-wide space
used for the storage of data variables and for memory-
mapped control registers. The ADSP-218xN series has up
to 56Kwords of Data Memory RAM on-chip. Part of this
space is used by 32 memory-mapped registers. Support also
exists for up to two 8K external memory overlay spaces
through the external data bus. All internal accesses com-
plete in one cycle. Accesses to external memory are timed
using the wait states specified by the DWAIT register and
the wait state mode bit.
Data Memory (Host Mode) allows access to all internal
memory. External overlay access is limited by a single exter-
nal address line (A0).
Table 8. PMOVLAY Bits
Table 9. DMOVLAY Bits
Memory-Mapped Registers (New to the ADSP-218xM
and N series)ADSP-218xN series members have three memory-mapped
registers that differ from other ADSP-21xx Family DSPs.
The slight modifications to these registers (Wait State Con-
trol, Programmable Flag and Composite Select Control,
and System Control) provide the ADSP-218xN’s wait state
and BMS control features. Default bit values at reset are
shown; if no value is shown, the bit is undefined at reset.
Reserved bits are shown on a grey field. These bits should
always be written with zeros.
I/O Space (Full Memory Mode)ADSP-218xN series members support an additional exter-
nal memory space called I/O space. This space is designed
to support simple connections to peripherals (such as data
converters and external registers) or to bus interface ASIC
data registers. I/O space supports 2048 locations of 16-bit
wide data. The lower eleven bits of the external address bus
are used; the upper three bits are undefined.
Two instructions were added to the core ADSP-2100
Family instruction set to read from and write to I/O memory
space. The I/O space also has four dedicated three-bit wait
state registers, IOWAIT0–3 as shown in Figure9, which in
combination with the wait state mode bit, specify up to 15
wait states to be automatically generated for each of four
regions. The wait states act on address ranges, as shown
in Table10.
Note: In Full Memory Mode, all 2048 locations of I/O space are directly addressable. In Host Memory Mode, only
address pin A0 is available; therefore, additional logic is
required externally to achieve complete addressability of the
2048 I/O space locations.
Composite Memory SelectADSP-218xN series members have a programmable
memory select signal that is useful for generating memory
select signals for memories mapped to more than one space.
The CMS signal is generated to have the same timing as
each of the individual memory select signals (PMS, DMS,
BMS, IOMS) but can combine their functionality. Each bit
in the CMSSEL register, when set, causes the CMS signal
to be asserted when the selected memory select is asserted.
For example, to use a 32Kword memory to act as both
program and data memory, set the PMS and DMS bits in
the CMSSEL register and use the CMS pin to drive the chip
select of the memory, and use either DMS or PMS as the
additional address bit.
The CMS pin functions like the other memory select signals
with the same timing and bus request logic. A 1 in the enable
bit causes the assertion of the CMS signal at the same time
as the selected memory select signal. All enable bits default
to 1 at reset, except the BMS bit.
See Figure10 and Figure11 for illustration of the program-
mable flag and composite control register and the system
control register.
Table 10. Wait StatesFigure 9. Wait State Control Register
Figure 10. Programmable Flag and Composite Control
Register
ADSP-218xN Series
Byte Memory SelectThe ADSP-218xN’s BMS disable feature combined with
the CMS pin allows use of multiple memories in the byte
memory space. For example, an EPROM could be attached
to the BMS select, and a flash memory could be connected
to CMS. Because at reset BMS is enabled, the EPROM
would be used for booting. After booting, software could
disable BMS and set the CMS signal to respond to BMS,
enabling the flash memory.
Byte MemoryThe byte memory space is a bidirectional, 8-bit-wide,
external memory space used to store programs and data.
Byte memory is accessed using the BDMA feature. The byte
memory space consists of 256 pages, each of which is
16K�8bits.
The byte memory space on the ADSP-218xN series sup-
ports read and write operations as well as four different data
formats. The byte memory uses data bits 15–8 for data. The
byte memory uses data bits 23–16 and address bits 13–0
to create a 22-bit address. This allows up to a 4meg�8
(32 megabit) ROM or RAM to be used without glue logic.
All byte memory accesses are timed by the BMWAIT reg-
ister and the wait state mode bit.
Byte Memory DMA (BDMA, Full Memory Mode)The byte memory DMA controller (Figure12) allows
loading and storing of program instructions and data using
the byte memory space. The BDMA circuit is able to access
the byte memory space while the processor is operating
normally and steals only one DSP cycle per 8-, 16-, or 24-
bit word transferred.
The BDMA circuit supports four different data formats that
are selected by the BTYPE register field. The appropriate
number of 8-bit accesses are done from the byte memory
space to build the word size selected. Table11 shows the
data formats supported by the BDMA circuit.
Unused bits in the 8-bit data memory formats are filled with
0s. The BIAD register field is used to specify the starting
address for the on-chip memory involved with the transfer.
The 14-bit BEAD register specifies the starting address for
the external byte memory space. The 8-bit BMPAGE reg-
ister specifies the starting page for the external byte memory
space. The BDIR register field selects the direction of the
transfer. Finally, the 14-bit BWCOUNT register specifies
the number of DSP words to transfer and initiates the
BDMA circuit transfers.
BDMA accesses can cross page boundaries during sequen-
tial addressing. A BDMA interrupt is generated on the com-
pletion of the number of transfers specified by the
BWCOUNT register.
The BWCOUNT register is updated after each transfer so
it can be used to check the status of the transfers. When
it reaches zero, the transfers have finished and a BDMA
interrupt is generated. The BMPAGE and BEAD registers
must not be accessed by the DSP during BDMA operations.
The source or destination of a BDMA transfer will always
be on-chip program or data memory.
When the BWCOUNT register is written with a nonzero
value the BDMA circuit starts executing byte memory
accesses with wait states set by BMWAIT. These accesses
continue until the count reaches zero. When enough access-
es have occurred to create a destination word, it is trans-
ferred to or from on-chip memory. The transfer takes one
Figure 11. System Control Register
Figure 12. BDMA Control Register
Table 11. Data Formats
DSP cycle. DSP accesses to external memory have priority
over BDMA byte memory accesses.
The BDMA Context Reset bit (BCR) controls whether the
processor is held off while the BDMA accesses are occur-
ring. Setting the BCR bit to 0 allows the processor to con-
tinue operations. Setting the BCR bit to 1 causes the
processor to stop execution while the BDMA accesses are
occurring, to clear the context of the processor, and start
execution at address 0 when the BDMA accesses have
completed.
The BDMA overlay bits specify the OVLAY memory blocks
to be accessed for internal memory. Set these bits as indi-
cated in.
Note: BDMA cannot access external overlay memory regions 1 and 2.
The BMWAIT field, which has four bits on ADSP-218xN
series members, allows selection up to 15 wait states for
BDMA transfers.
Internal Memory DMA Port (IDMA Port; Host Memory
Mode)The IDMA Port provides an efficient means of communi-
cation between a host system and ADSP-218xN series
members. The port is used to access the on-chip program
memory and data memory of the DSP with only one DSP
cycle per word overhead. The IDMA port cannot, however,
be used to write to the DSP’s memory-mapped control reg-
isters. A typical IDMA transfer process is shown as follows:Host starts IDMA transfer.Host checks IACK control line to see if the DSP is
busy.Host uses IS and IAL control lines to latch either the
DMA starting address (IDMAA) or the PM/DM
OVLAY selection into the DSP’s IDMA control regis-
ters. If Bit 15 = 1, the value of bits 7–0 represent the
IDMA overlay; bits 14–8 must be set to 0. If Bit 15 =0,
the value of Bits 13–0 represent the starting address
of internal memory to be accessed and Bit 14 reflects
PM or DM for access. Set IDDMOVLAY and
IDPMOVLAY bits in the IDMA overlay register as
indicted in Table12.Host uses IS and IRD (or IWR) to read (or write) DSP
internal memory (PM or DM).Host checks IACK line to see if the DSP has completed
the previous IDMA operation.Host ends IDMA transfer.
The IDMA port has a 16-bit multiplexed address and data
bus and supports 24-bit program memory. The IDMA port
is completely asynchronous and can be written while the
ADSP-218xN is operating at full speed.
The DSP memory address is latched and then automatically
incremented after each IDMA transaction. An external
device can therefore access a block of sequentially addressed
memory by specifying only the starting address of the block.
This increases throughput as the address does not have to
be sent for each memory access.
IDMA Port access occurs in two phases. The first is the
IDMA Address Latch cycle. When the acknowledge is as-
serted, a 14-bit address and 1-bit destination type can be
driven onto the bus by an external device. The address spec-
ifies an on-chip memory location, the destination type spec-
ifies whether it is a DM or PM access. The falling edge of
the IDMA address latch signal (IAL) or the missing edge of
the IDMA select signal (IS) latches this value into the
IDMAA register.
Once the address is stored, data can be read from, or written
to, the ADSP-218xN’s on-chip memory. Asserting the
select line (IS) and the appropriate read or write line (IRD
and IWR respectively) signals the ADSP-218xN that a par-
ticular transaction is required. In either case, there is a one-
processor-cycle delay for synchronization. The memory
access consumes one additional processor cycle.
Once an access has occurred, the latched address is auto-
matically incremented, and another access can occur.
Through the IDMAA register, the DSP can also specify the
starting address and data format for DMA operation.
Asserting the IDMA port select (IS) and address latch
enable (IAL) directs the ADSP-218xN to write the address
onto the IAD14–0 bus into the IDMA Control Register
(Figure13). If Bit 15 is set to 0, IDMA latches the address.
If Bit 15 is set to 1, IDMA latches into the OVLAY register.
This register, also shown in Figure13, is memory-mapped
at address DM (0x3FE0). Note that the latched address
(IDMAA) cannot be read back by the host.
When Bit 14 in 0x3FE7 is set to zero, short reads use the
timing shown in Figure34 on page37. When Bit 14 in
0x3FE7 is set to 1, timing in Figure35 on page38 applies
for short reads in short read only mode. Set IDDMOVLAY
Table 12. IDMA/BDMA Overlay Bits
ADSP-218xN Seriesand IDPMOVLAY bits in the IDMA overlay register as
indicated in Table12. Refer to the ADSP-218x DSP Hard-
ware Reference for additional details.
Note: In full memory mode all locations of 4M-byte memory space are directly addressable. In host memory
mode, only address pin A0 is available, requiring additional
external logic to provide address information for the byte.
Bootstrap Loading (Booting)ADSP-218xN series members have two mechanisms to
allow automatic loading of the internal program memory
after reset. The method for booting is controlled by the
Mode A, B, and C configuration bits.
When the mode pins specify BDMA booting, the ADSP-
218xN initiates a BDMA boot sequence when reset is
released.
The BDMA interface is set up during reset to the following
defaults when BDMA booting is specified: the BDIR,
BMPAGE, BIAD, and BEAD registers are set to 0, the
BTYPE register is set to 0 to specify program memory 24-
bit words, and the BWCOUNT register is set to 32. This
causes 32 words of on-chip program memory to be loaded
from byte memory. These 32 words are used to set up the
BDMA to load in the remaining program code. The BCR
bit is also set to 1, which causes program execution to be
held off until all 32 words are loaded into on-chip program
memory. Execution then begins at address 0.
The ADSP-2100 Family development software (Revision
5.02 and later) fully supports the BDMA booting feature
and can generate byte memory space-compatible boot code.
The IDLE instruction can also be used to allow the proces-
sor to hold off execution while booting continues through
the BDMA interface. For BDMA accesses while in Host
Mode, the addresses to boot memory must be constructed
externally to the ADSP-218xN. The only memory address
IDMA Port BootingADSP-218xN series members can also boot programs
through its Internal DMA port. If Mode C = 1, Mode B =
0, and Mode A = 1, the ADSP-218xN boots from the IDMA
port. IDMA feature can load as much on-chip memory as
desired. Program execution is held off until the host writes
to on-chip program memory location 0.
BUS REQUEST AND BUS GRANT ADSP-218xN series members can relinquish control of the
data and address buses to an external device. When the
external device requires access to memory, it asserts the Bus
Request (BR) signal. If the ADSP-218xN is not performing
an external memory access, it responds to the active BR
input in the following processor cycle by: Three-stating the data and address buses and the PMS,
DMS, BMS, CMS, IOMS, RD, WR output drivers,Asserting the bus grant (BG) signal, andHalting program execution.
If Go Mode is enabled, the ADSP-218xN will not halt
program execution until it encounters an instruction that
requires an external memory access.
If an ADSP-218xN series member is performing an external
memory access when the external device asserts the BR
signal, it will not three-state the memory interfaces nor
assert the BG signal until the processor cycle after the access
completes. The instruction does not need to be completed
when the bus is granted. If a single instruction requires two
external memory accesses, the bus will be granted between
the twoaccesses.
When the BR signal is released, the processor releases the
BG signal, re-enables the output drivers, and continues
program execution from the point at which it stopped.
The bus request feature operates at all times, including
when the processor is booting and when RESET is active.
The BGH pin is asserted when an ADSP-218xN series
member requires the external bus for a memory or BDMA
access, but is stopped. The other device can release the bus
by deasserting bus request. Once the bus is released, the
ADSP-218xN deasserts BG and BGH and executes the
external memory access.
FLAG I/O PINSADSP-218xN series members have eight general-purpose
programmable input/output flag pins. They are controlled
by two memory-mapped registers. The PFTYPE register
determines the direction, 1 = output and 0 = input. The
PFDATA register is used to read and write the values on the
pins. Data being read from a pin configured as an input is
synchronized to the ADSP-218xN’s clock. Bits that are pro-
grammed as outputs will read the value being output. The
PF pins default to input during reset.
Figure 13. IDMA OVLAY/Control Registers
In addition to the programmable flags, ADSP-218xN series
members have five fixed-mode flags, FI, FO, FL0, FL1, and
FL2. FL0–FL2 are dedicated output flags. FI and FO are
available as an alternate configuration of SPORT1.
Note: Pins PF0, PF1, PF2, and PF3 are also used for device configuration during reset.
INSTRUCTION SET DESCRIPTIONThe ADSP-218xN series assembly language instruction set
has an algebraic syntax that was designed for ease of coding
and readability. The assembly language, which takes full
advantage of the processor’s unique architecture, offers the
following benefits:The algebraic syntax eliminates the need to remember
cryptic assembler mnemonics. For example, a typical
arithmetic add instruction, such as AR = AX0 + AY0,
resembles a simple equation.Every instruction assembles into a single, 24-bit word that
can execute in a single instruction cycle.The syntax is a superset ADSP-2100 Family assembly
language and is completely source and object code com-
patible with other family members. Programs may need
to be relocated to utilize on-chip memory and conform to
the ADSP-218xN’s interrupt vector and reset vector map.Sixteen condition codes are available. For conditional
jump, call, return, or arithmetic instructions, the
condition can be checked and the operation executed in
the same instruction cycle.Multifunction instructions allow parallel execution of an
arithmetic instruction, with up to two fetches or one write
to processor memory space, during a single instruc-
tioncycle.
DESIGNING AN EZ-ICE-COMPATIBLE SYSTEMADSP-218xN series members have on-chip emulation
support and an ICE-Port, a special set of pins that interface
to the EZ-ICE. These features allow in-circuit emulation
without replacing the target system processor by using only
a 14-pin connection from the target system to the EZ-ICE.
Target systems must have a 14-pin connector to accept the
EZ-ICE’s in-circuit probe, a 14-pin plug.
Note: The EZ-ICE uses the same VDD voltage as the VDD voltage used for VDDEXT. Because the input pins of the
ADSP-218xN series members are tolerant to input voltages
up to 3.6V, regardless of the value of VDDEXT, the voltage
setting for the EZ-ICE must not exceed 3.3V.
Issuing the chip reset command during emulation causes
the DSP to perform a full chip reset, including a reset of its
memory mode. Therefore, it is vital that the mode pins are
set correctly PRIOR to issuing a chip reset command from
the emulator user interface. If a passive method of maintain-
ing mode information is being used (as discussed in Setting
Memory Mode on page11), it does not matter that the
if the RESET pin is being used as a method of setting the
value of the mode pins, the effects of an emulator reset must
be taken into consideration.
One method of ensuring that the values located on the mode
pins are those desired is to construct a circuit like the one
shown in Figure14. This circuit forces the value located on
the Mode A pin to logic high, regardless of whether it is
latched via the RESET or ERESET pin.
The ICE-Port interface consists of the following ADSP-
218xN pins: EBR, EINT, EE, EBG, ECLK, ERESET,
ELIN, EMS, and ELOUT.
These ADSP-218xN pins must be connected only to the
EZ-ICE connector in the target system. These pins have no
function except during emulation, and do not require pull-
up or pull-down resistors. The traces for these signals
between the ADSP-218xN and the connector must be kept
as short as possible, no longer than 3 inches.
The following pins are also used by the EZ-ICE: BR, BG,
RESET, and GND.
The EZ-ICE uses the EE (emulator enable) signal to take
control of the ADSP-218xN in the target system. This
causes the processor to use its ERESET, EBR, and EBG
pins instead of the RESET, BR, and BG pins. The BG
output is three-stated. These signals do not need to be
jumper-isolated in the system.
The EZ-ICE connects to the target system via a ribbon cable
and a 14-pin female plug. The female plug is plugged onto
the 14-pin connector (a pin strip header) on the target
board.
Target Board Connector for EZ-ICE ProbeThe EZ-ICE connector (a standard pin strip header) is
shown in Figure15. This connector must be added to the
target board design to use the EZ-ICE. Be sure to allow
enough room in the system to fit the EZ-ICE probe onto
the 14-pin connector.
The 14-pin, 2-row pin strip header is keyed at the Pin7
location—Pin7 must be removed from the header. The pins
must be 0.025 inch square and at least 0.20inch in length.
Figure 14. Mode A Pin/EZ-ICE Circuit
ADSP-218xN SeriesPin spacing should be 0.1�0.1 inches. The pin strip header
must have at least 0.15inch clearance on all sides to accept
the EZ-ICE probe plug.
Pin strip headers are available from vendors such as 3M,
McKenzie, and Samtec.
Target Memory InterfaceFor the target system to be compatible with the EZ-ICE
emulator, it must comply with the memory interface guide-
lines listed below.
PM, DM, BM, IOM, and CMDesign the Program Memory (PM), Data Memory (DM),
Byte Memory (BM), I/O Memory (IOM), and Composite
Memory (CM) external interfaces to comply with worst-
case device timing requirements and switching characteris-
tics as specified in this data sheet. The performance of the
EZ-ICE may approach published worst-case specification
for some memory access timing requirements and switching
characteristics.
Note: If the target does not meet the worst-case chip spec-ification for memory access parameters, the circuitry may
not be able to be emulated at the desired CLKIN frequency.
Depending on the severity of the specification violation, the
system may be difficult to manufacture, as DSP compo-
nents statistically vary in switching characteristic and timing
requirements, within published limits.
Restriction: All memory strobe signals on the ADSP-218xN (RD, WR, PMS, DMS, BMS, CMS, and IOMS)
used in the target system must have 10k� pull-up resistors
connected when the EZ-ICE is being used. The pull-up
resistors are necessary because there are no internal pull-
ups to guarantee their state during prolonged three-state
conditions resulting from typical EZ-ICE debugging ses-
sions. These resistors may be removed when the EZ-ICE is
not being used.
Target System Interface SignalsWhen the EZ-ICE board is installed, the performance on
some system signals changes. Design the system to be com-
patible with the following system interface signal changes
introduced by the EZ-ICE board:EZ-ICE emulation introduces an 8 ns propagation
delay between the target circuitry and the DSP on the
RESET signal.EZ-ICE emulation introduces an 8 ns propagation
delay between the target circuitry and the DSP on the BR
signal.EZ-ICE emulation ignores RESET and BR, when
single-stepping.EZ-ICE emulation ignores RESET and BR when in
Emulator Space (DSP halted).EZ-ICE emulation ignores the state of target BR in certain
modes. As a result, the target system may take control of
the DSP’s external memory bus only if bus grant (BG) is
asserted by the EZ-ICE board’s DSP.
Figure 15. Target Board Connector for EZ-ICE
SPECIFICATIONS
RECOMMENDED OPERATING CONDITIONS Specifications subject to change without notice.The ADSP-218xN is 3.3V tolerant (always accepts up to 3.6V max VIH), but voltage compliance (on outputs, VOH) depends on the input VDDEXT,
because VOH (max) approximately equals VDDEXT (max). This 3.3V tolerance applies to bidirectional pins (D23–D0, RFS0, RFS1, SCLK0, SCLK1,
TFS0, TFS1, A13–A1, PF7–PF0) and input-only pins (CLKIN, RESET, BR, DR0, DR1, PWD).
ELECTRICAL CHARACTERISTICS
ADSP-218xN Series
ABSOLUTE MAXIMUM RATINGSSpecifications subject to change without notice.Bidirectional pins: D23–0, RFS0, RFS1, SCLK0, SCLK1, TFS0, TFS1, A13–1, PF7–0.Input only pins: CLKIN, RESET, BR, DR0, DR1, PWD.Output pins: BG, PMS, DMS, BMS, IOMS, CMS, RD, WR, PWDACK, A0, DT0, DT1, CLKOUT, FL2–FL0, BGH.Although specified for TTL outputs, all ADSP-218xN outputs are CMOS-compatible and will drive to VDDEXT and GND, assuming no dc loads.Guaranteed but not tested.Three-statable pins: A13–A1, D23–D0, PMS, DMS, BMS, IOMS, CMS, RD, WR, DT0, DT1, SCLK0, SCLK1, TFS0, TFS1, RFS0, RFS1, PF7–PF0.0 V on BR.Idle refers to ADSP-218xN state of operation during execution of IDLE instruction. Deasserted pins are driven to either VDD or GND.IDD measurement taken with all instructions executing from internal memory. 50% of the instructions are multifunction (Types 1, 4, 5, 12, 13, 14), 30%
are Type 2 and Type 6, and 20% are idle instructions.VIN = 0V and 3 V. For typical values for supply currents, refer to Power Dissipation section.See ADSP-218x DSP Hardware Reference for details.Output pin capacitance is the capacitive load for any three-stated output pin.
ELECTRICAL CHARACTERISTICS (CONTINUED)Internal Supply Voltage (VDDINT)1. . . . . . . . –0.3 V to +2.2 V
External Supply Voltage (VDDEXT) . . . . . . . . –0.3 V to +4.0 V
Input Voltage2 . . . . . . . . . . . . . . . . . . . . . . –0.5 V to +4.0 V
Output Voltage Swing3. . . . . . . . . . .–0.5 V to VDDEXT +0.5 V
Operating Temperature Range . . . . . . . . . . .–40ºC to +85ºC
Storage Temperature Range . . . . . . . . . . . .–65ºC to +150ºC
Lead Temperature (5 sec) LQFP . . . . . . . . . . . . . . . –280ºCStresses greater than those listed above may cause permanent damage to the
device. These are stress ratings only. Functional operation of the device at these
or any other conditions greater than those indicated in the operational sections
of this specification is not implied. Exposure to absolute maximum rating condi-
tions for extended periods may affect device reliability.Applies to Bidirectional pins (D23–0, RFS0, RFS1, SCLK0, SCLK1, TFS0,
TFS1, A13–1, PF7–0) and Input only pins (CLKIN, RESET, BR, DR0, DR1,
PWD).Applies to Output pins (BG, PMS, DMS, BMS, IOMS, CMS, RD, WR,
PWDACK, A0, DT0, DT1, CLKOUT, FL2–0, BGH).
ESD SENSITIVITY
Power DissipationTo determine total power dissipation in a specific applica-
tion, the following equation should be applied for each
output: C � VDD2 � f
where: C = load capacitance, f = output switching frequency.
Example: In an application where external data memory is used and no other outputs are active, power dissipation is
calculated as follows:
Assumptions:External data memory is accessed every cycle with 50%
of the address pins switching.External data memory writes occur every other cycle with
50% of the data pins switching.Each address and data pin has a 10 pF total load at the pin.Application operates at VDDEXT = 3.3V and tCK = 30ns.otal Power Dissipation = PINT + (C �VDDEXT2 � f)
P INT = internal power dissipation from Figure20 on
page26.
(C � VDDEXT2 � f) is calculated for each output, as in the
example in Table13.
Total power dissipation for this example is
PINT+45.72mW.
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V
readily accumulate on the human body and test equipment and can discharge without
detection. Although the ADSP-218xN features proprietary ESD protection circuitry,
permanent damage may occur on devices subjected to high-energy electrostatic
discharges. Therefore, proper ESD precautions are recommended to avoid perfor-
mance degradation or loss of functionality.
CAUTION
Table 13. Example Power Dissipation Calculation
ADSP-218xN Series
Environmental Conditions
Test Conditions
Output Disable TimeOutput pins are considered to be disabled when they have
stopped driving and started a transition from the measured
output high or low voltage to a high impedance state. The
output disable time (tDIS) is the difference of tMEASURED and
tDECAY, as shown in Figure18. The time is the interval from
when a reference signal reaches a high or low voltage level
to when the output voltages have changed by 0.5V from the
measured output high or low voltage.
The decay time, tDECAY, is dependent on the capacitive load,
CL, and the current load, iL, on the output pin. It can be
approximated by the following equation:
from which
is calculated. If multiple pins (such as the data bus) are
disabled, the measurement value is that of the last pin to
stop driving.
Output Enable TimeOutput pins are considered to be enabled when they have
made a transition from a high-impedance state to when they
start driving. The output enable time (tENA) is the interval
from when a reference signal reaches a high or low voltage
level to when the output has reached a specified high or low
trip point, as shown in Figure18. If multiple pins (such as
the data bus) are enabled, the measurement value is that of
the first pin to start driving.
Table 14. Thermal ResistanceWhere the Ambient Temperature Rating (TAMB) is:
TAMB = TCASE – (PD × θCA)
TCASE = Case Temperature in °C
PD = Power Dissipation in W
Figure 16. Voltage Reference Levels for AC
Measurements (Except Output Enable/Disable)
Figure 17. Equivalent Loading for AC Measurements
(Including All Fixtures)
Figure 18. Output Enable/Disable
tDECAYL0.5V×L-------------------------=DIStMEASUREDtDECAY–=
